drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * S5P camera interface (video postprocessor) driver
   3  *
   4  * Copyright (c) 2010 Samsung Electronics Co., Ltd
   5  *
   6  * Sylwester Nawrocki, <s.nawrocki@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published
  10  * by the Free Software Foundation, either version 2 of the License,
  11  * or (at your option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/version.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/bug.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/device.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/list.h>
  24 #include <linux/io.h>
  25 #include <linux/slab.h>
  26 #include <linux/clk.h>
  27 #include <media/v4l2-ioctl.h>
  28 #include <media/videobuf2-core.h>
  29 #include <media/videobuf2-dma-contig.h>
  30
  31 #include "fimc-core.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc", "sclk_cam"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565X,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "XRGB-8-8-8-8, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M,
  62         }, {
  63                 .name           = "YUV 4:2:2 packed, YCbYCr",
  64                 .fourcc         = V4L2_PIX_FMT_YUYV,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_YCBYCR422,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  70                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  71         }, {
  72                 .name           = "YUV 4:2:2 packed, CbYCrY",
  73                 .fourcc         = V4L2_PIX_FMT_UYVY,
  74                 .depth          = { 16 },
  75                 .color          = S5P_FIMC_CBYCRY422,
  76                 .memplanes      = 1,
  77                 .colplanes      = 1,
  78                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  79                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  80         }, {
  81                 .name           = "YUV 4:2:2 packed, CrYCbY",
  82                 .fourcc         = V4L2_PIX_FMT_VYUY,
  83                 .depth          = { 16 },
  84                 .color          = S5P_FIMC_CRYCBY422,
  85                 .memplanes      = 1,
  86                 .colplanes      = 1,
  87                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
  88                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  89         }, {
  90                 .name           = "YUV 4:2:2 packed, YCrYCb",
  91                 .fourcc         = V4L2_PIX_FMT_YVYU,
  92                 .depth          = { 16 },
  93                 .color          = S5P_FIMC_YCRYCB422,
  94                 .memplanes      = 1,
  95                 .colplanes      = 1,
  96                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
  97                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  98         }, {
  99                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 100                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 101                 .depth          = { 12 },
 102                 .color          = S5P_FIMC_YCBYCR422,
 103                 .memplanes      = 1,
 104                 .colplanes      = 3,
 105                 .flags          = FMT_FLAGS_M2M,
 106         }, {
 107                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 108                 .fourcc         = V4L2_PIX_FMT_NV16,
 109                 .depth          = { 16 },
 110                 .color          = S5P_FIMC_YCBYCR422,
 111                 .memplanes      = 1,
 112                 .colplanes      = 2,
 113                 .flags          = FMT_FLAGS_M2M,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 116                 .fourcc         = V4L2_PIX_FMT_NV61,
 117                 .depth          = { 16 },
 118                 .color          = S5P_FIMC_YCRYCB422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 2,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:0 planar, YCbCr",
 124                 .fourcc         = V4L2_PIX_FMT_YUV420,
 125                 .depth          = { 12 },
 126                 .color          = S5P_FIMC_YCBCR420,
 127                 .memplanes      = 1,
 128                 .colplanes      = 3,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 132                 .fourcc         = V4L2_PIX_FMT_NV12,
 133                 .depth          = { 12 },
 134                 .color          = S5P_FIMC_YCBCR420,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 140                 .fourcc         = V4L2_PIX_FMT_NV12M,
 141                 .color          = S5P_FIMC_YCBCR420,
 142                 .depth          = { 8, 4 },
 143                 .memplanes      = 2,
 144                 .colplanes      = 2,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 148                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 149                 .color          = S5P_FIMC_YCBCR420,
 150                 .depth          = { 8, 2, 2 },
 151                 .memplanes      = 3,
 152                 .colplanes      = 3,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 156                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         },
 163 };
 164
 165 static struct v4l2_queryctrl fimc_ctrls[] = {
 166         {
 167                 .id             = V4L2_CID_HFLIP,
 168                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
 169                 .name           = "Horizontal flip",
 170                 .minimum        = 0,
 171                 .maximum        = 1,
 172                 .default_value  = 0,
 173         }, {
 174                 .id             = V4L2_CID_VFLIP,
 175                 .type           = V4L2_CTRL_TYPE_BOOLEAN,
 176                 .name           = "Vertical flip",
 177                 .minimum        = 0,
 178                 .maximum        = 1,
 179                 .default_value  = 0,
 180         }, {
 181                 .id             = V4L2_CID_ROTATE,
 182                 .type           = V4L2_CTRL_TYPE_INTEGER,
 183                 .name           = "Rotation (CCW)",
 184                 .minimum        = 0,
 185                 .maximum        = 270,
 186                 .step           = 90,
 187                 .default_value  = 0,
 188         },
 189 };
 190
 191
 192 static struct v4l2_queryctrl *get_ctrl(int id)
 193 {
 194         int i;
 195
 196         for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
 197                 if (id == fimc_ctrls[i].id)
 198                         return &fimc_ctrls[i];
 199         return NULL;
 200 }
 201
 202 int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
 203 {
 204         int tx, ty;
 205
 206         if (rot == 90 || rot == 270) {
 207                 ty = dw;
 208                 tx = dh;
 209         } else {
 210                 tx = dw;
 211                 ty = dh;
 212         }
 213
 214         if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
 215                 return -EINVAL;
 216
 217         return 0;
 218 }
 219
 220 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 221 {
 222         u32 sh = 6;
 223
 224         if (src >= 64 * tar)
 225                 return -EINVAL;
 226
 227         while (sh--) {
 228                 u32 tmp = 1 << sh;
 229                 if (src >= tar * tmp) {
 230                         *shift = sh, *ratio = tmp;
 231                         return 0;
 232                 }
 233         }
 234         *shift = 0, *ratio = 1;
 235         return 0;
 236 }
 237
 238 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 239 {
 240         struct fimc_scaler *sc = &ctx->scaler;
 241         struct fimc_frame *s_frame = &ctx->s_frame;
 242         struct fimc_frame *d_frame = &ctx->d_frame;
 243         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 244         int tx, ty, sx, sy;
 245         int ret;
 246
 247         if (ctx->rotation == 90 || ctx->rotation == 270) {
 248                 ty = d_frame->width;
 249                 tx = d_frame->height;
 250         } else {
 251                 tx = d_frame->width;
 252                 ty = d_frame->height;
 253         }
 254         if (tx <= 0 || ty <= 0) {
 255                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
 256                         "invalid target size: %d x %d", tx, ty);
 257                 return -EINVAL;
 258         }
 259
 260         sx = s_frame->width;
 261         sy = s_frame->height;
 262         if (sx <= 0 || sy <= 0) {
 263                 err("invalid source size: %d x %d", sx, sy);
 264                 return -EINVAL;
 265         }
 266         sc->real_width = sx;
 267         sc->real_height = sy;
 268
 269         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 270         if (ret)
 271                 return ret;
 272
 273         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 274         if (ret)
 275                 return ret;
 276
 277         sc->pre_dst_width = sx / sc->pre_hratio;
 278         sc->pre_dst_height = sy / sc->pre_vratio;
 279
 280         if (variant->has_mainscaler_ext) {
 281                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 282                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 283         } else {
 284                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 285                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 286
 287         }
 288
 289         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 290         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 291
 292         /* check to see if input and output size/format differ */
 293         if (s_frame->fmt->color == d_frame->fmt->color
 294                 && s_frame->width == d_frame->width
 295                 && s_frame->height == d_frame->height)
 296                 sc->copy_mode = 1;
 297         else
 298                 sc->copy_mode = 0;
 299
 300         return 0;
 301 }
 302
 303 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 304 {
 305         struct vb2_buffer *src_vb, *dst_vb;
 306         struct fimc_dev *fimc = ctx->fimc_dev;
 307
 308         if (!ctx || !ctx->m2m_ctx)
 309                 return;
 310
 311         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 312         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 313
 314         if (src_vb && dst_vb) {
 315                 v4l2_m2m_buf_done(src_vb, vb_state);
 316                 v4l2_m2m_buf_done(dst_vb, vb_state);
 317                 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
 318         }
 319 }
 320
 321 /* Complete the transaction which has been scheduled for execution. */
 322 static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
 323 {
 324         struct fimc_dev *fimc = ctx->fimc_dev;
 325         int ret;
 326
 327         if (!fimc_m2m_pending(fimc))
 328                 return;
 329
 330         fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
 331
 332         ret = wait_event_timeout(fimc->irq_queue,
 333                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 334                            FIMC_SHUTDOWN_TIMEOUT);
 335         /*
 336          * In case of a timeout the buffers are not released in the interrupt
 337          * handler so return them here with the error flag set, if there are
 338          * any on the queue.
 339          */
 340         if (ret == 0)
 341                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 342 }
 343
 344 static int stop_streaming(struct vb2_queue *q)
 345 {
 346         struct fimc_ctx *ctx = q->drv_priv;
 347
 348         fimc_m2m_shutdown(ctx);
 349
 350         return 0;
 351 }
 352
 353 static void fimc_capture_irq_handler(struct fimc_dev *fimc)
 354 {
 355         struct fimc_vid_cap *cap = &fimc->vid_cap;
 356         struct fimc_vid_buffer *v_buf;
 357         struct timeval *tv;
 358         struct timespec ts;
 359
 360         if (!list_empty(&cap->active_buf_q) &&
 361             test_bit(ST_CAPT_RUN, &fimc->state)) {
 362                 ktime_get_real_ts(&ts);
 363
 364                 v_buf = active_queue_pop(cap);
 365
 366                 tv = &v_buf->vb.v4l2_buf.timestamp;
 367                 tv->tv_sec = ts.tv_sec;
 368                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 369                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 370
 371                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 372         }
 373
 374         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 375                 wake_up(&fimc->irq_queue);
 376                 return;
 377         }
 378
 379         if (!list_empty(&cap->pending_buf_q)) {
 380
 381                 v_buf = pending_queue_pop(cap);
 382                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 383                 v_buf->index = cap->buf_index;
 384
 385                 /* Move the buffer to the capture active queue */
 386                 active_queue_add(cap, v_buf);
 387
 388                 dbg("next frame: %d, done frame: %d",
 389                     fimc_hw_get_frame_index(fimc), v_buf->index);
 390
 391                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 392                         cap->buf_index = 0;
 393         }
 394
 395         if (cap->active_buf_cnt == 0) {
 396                 clear_bit(ST_CAPT_RUN, &fimc->state);
 397
 398                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 399                         cap->buf_index = 0;
 400         } else {
 401                 set_bit(ST_CAPT_RUN, &fimc->state);
 402         }
 403
 404         dbg("frame: %d, active_buf_cnt: %d",
 405             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 406 }
 407
 408 static irqreturn_t fimc_isr(int irq, void *priv)
 409 {
 410         struct fimc_dev *fimc = priv;
 411         struct fimc_vid_cap *cap = &fimc->vid_cap;
 412         struct fimc_ctx *ctx;
 413
 414         fimc_hw_clear_irq(fimc);
 415
 416         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 417                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 418                 if (ctx != NULL) {
 419                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 420
 421                         spin_lock(&ctx->slock);
 422                         if (ctx->state & FIMC_CTX_SHUT) {
 423                                 ctx->state &= ~FIMC_CTX_SHUT;
 424                                 wake_up(&fimc->irq_queue);
 425                         }
 426                         spin_unlock(&ctx->slock);
 427                 }
 428
 429                 return IRQ_HANDLED;
 430         }
 431
 432         spin_lock(&fimc->slock);
 433
 434         if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 435                 fimc_capture_irq_handler(fimc);
 436
 437                 if (cap->active_buf_cnt == 1) {
 438                         fimc_deactivate_capture(fimc);
 439                         clear_bit(ST_CAPT_STREAM, &fimc->state);
 440                 }
 441         }
 442
 443         spin_unlock(&fimc->slock);
 444         return IRQ_HANDLED;
 445 }
 446
 447 /* The color format (colplanes, memplanes) must be already configured. */
 448 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 449                       struct fimc_frame *frame, struct fimc_addr *paddr)
 450 {
 451         int ret = 0;
 452         u32 pix_size;
 453
 454         if (vb == NULL || frame == NULL)
 455                 return -EINVAL;
 456
 457         pix_size = frame->width * frame->height;
 458
 459         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 460                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 461
 462         paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
 463
 464         if (frame->fmt->memplanes == 1) {
 465                 switch (frame->fmt->colplanes) {
 466                 case 1:
 467                         paddr->cb = 0;
 468                         paddr->cr = 0;
 469                         break;
 470                 case 2:
 471                         /* decompose Y into Y/Cb */
 472                         paddr->cb = (u32)(paddr->y + pix_size);
 473                         paddr->cr = 0;
 474                         break;
 475                 case 3:
 476                         paddr->cb = (u32)(paddr->y + pix_size);
 477                         /* decompose Y into Y/Cb/Cr */
 478                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 479                                 paddr->cr = (u32)(paddr->cb
 480                                                 + (pix_size >> 2));
 481                         else /* 422 */
 482                                 paddr->cr = (u32)(paddr->cb
 483                                                 + (pix_size >> 1));
 484                         break;
 485                 default:
 486                         return -EINVAL;
 487                 }
 488         } else {
 489                 if (frame->fmt->memplanes >= 2)
 490                         paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
 491
 492                 if (frame->fmt->memplanes == 3)
 493                         paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
 494         }
 495
 496         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 497             paddr->y, paddr->cb, paddr->cr, ret);
 498
 499         return ret;
 500 }
 501
 502 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 503 static void fimc_set_yuv_order(struct fimc_ctx *ctx)
 504 {
 505         /* The one only mode supported in SoC. */
 506         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 507         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 508
 509         /* Set order for 1 plane input formats. */
 510         switch (ctx->s_frame.fmt->color) {
 511         case S5P_FIMC_YCRYCB422:
 512                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 513                 break;
 514         case S5P_FIMC_CBYCRY422:
 515                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 516                 break;
 517         case S5P_FIMC_CRYCBY422:
 518                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 519                 break;
 520         case S5P_FIMC_YCBYCR422:
 521         default:
 522                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 523                 break;
 524         }
 525         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 526
 527         switch (ctx->d_frame.fmt->color) {
 528         case S5P_FIMC_YCRYCB422:
 529                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 530                 break;
 531         case S5P_FIMC_CBYCRY422:
 532                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 533                 break;
 534         case S5P_FIMC_CRYCBY422:
 535                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 536                 break;
 537         case S5P_FIMC_YCBYCR422:
 538         default:
 539                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 540                 break;
 541         }
 542         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 543 }
 544
 545 static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 546 {
 547         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 548         u32 i, depth = 0;
 549
 550         for (i = 0; i < f->fmt->colplanes; i++)
 551                 depth += f->fmt->depth[i];
 552
 553         f->dma_offset.y_h = f->offs_h;
 554         if (!variant->pix_hoff)
 555                 f->dma_offset.y_h *= (depth >> 3);
 556
 557         f->dma_offset.y_v = f->offs_v;
 558
 559         f->dma_offset.cb_h = f->offs_h;
 560         f->dma_offset.cb_v = f->offs_v;
 561
 562         f->dma_offset.cr_h = f->offs_h;
 563         f->dma_offset.cr_v = f->offs_v;
 564
 565         if (!variant->pix_hoff) {
 566                 if (f->fmt->colplanes == 3) {
 567                         f->dma_offset.cb_h >>= 1;
 568                         f->dma_offset.cr_h >>= 1;
 569                 }
 570                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 571                         f->dma_offset.cb_v >>= 1;
 572                         f->dma_offset.cr_v >>= 1;
 573                 }
 574         }
 575
 576         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 577             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 578 }
 579
 580 /**
 581  * fimc_prepare_config - check dimensions, operation and color mode
 582  *                       and pre-calculate offset and the scaling coefficients.
 583  *
 584  * @ctx: hardware context information
 585  * @flags: flags indicating which parameters to check/update
 586  *
 587  * Return: 0 if dimensions are valid or non zero otherwise.
 588  */
 589 int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
 590 {
 591         struct fimc_frame *s_frame, *d_frame;
 592         struct vb2_buffer *vb = NULL;
 593         int ret = 0;
 594
 595         s_frame = &ctx->s_frame;
 596         d_frame = &ctx->d_frame;
 597
 598         if (flags & FIMC_PARAMS) {
 599                 /* Prepare the DMA offset ratios for scaler. */
 600                 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
 601                 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
 602
 603                 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
 604                     s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
 605                         err("out of scaler range");
 606                         return -EINVAL;
 607                 }
 608                 fimc_set_yuv_order(ctx);
 609         }
 610
 611         /* Input DMA mode is not allowed when the scaler is disabled. */
 612         ctx->scaler.enabled = 1;
 613
 614         if (flags & FIMC_SRC_ADDR) {
 615                 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 616                 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
 617                 if (ret)
 618                         return ret;
 619         }
 620
 621         if (flags & FIMC_DST_ADDR) {
 622                 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 623                 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
 624         }
 625
 626         return ret;
 627 }
 628
 629 static void fimc_dma_run(void *priv)
 630 {
 631         struct fimc_ctx *ctx = priv;
 632         struct fimc_dev *fimc;
 633         unsigned long flags;
 634         u32 ret;
 635
 636         if (WARN(!ctx, "null hardware context\n"))
 637                 return;
 638
 639         fimc = ctx->fimc_dev;
 640
 641         spin_lock_irqsave(&ctx->slock, flags);
 642         set_bit(ST_M2M_PEND, &fimc->state);
 643
 644         ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
 645         ret = fimc_prepare_config(ctx, ctx->state);
 646         if (ret)
 647                 goto dma_unlock;
 648
 649         /* Reconfigure hardware if the context has changed. */
 650         if (fimc->m2m.ctx != ctx) {
 651                 ctx->state |= FIMC_PARAMS;
 652                 fimc->m2m.ctx = ctx;
 653         }
 654
 655         spin_lock(&fimc->slock);
 656         fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
 657
 658         if (ctx->state & FIMC_PARAMS) {
 659                 fimc_hw_set_input_path(ctx);
 660                 fimc_hw_set_in_dma(ctx);
 661                 ret = fimc_set_scaler_info(ctx);
 662                 if (ret) {
 663                         spin_unlock(&fimc->slock);
 664                         goto dma_unlock;
 665                 }
 666                 fimc_hw_set_prescaler(ctx);
 667                 fimc_hw_set_mainscaler(ctx);
 668                 fimc_hw_set_target_format(ctx);
 669                 fimc_hw_set_rotation(ctx);
 670                 fimc_hw_set_effect(ctx);
 671         }
 672
 673         fimc_hw_set_output_path(ctx);
 674         if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
 675                 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
 676
 677         if (ctx->state & FIMC_PARAMS)
 678                 fimc_hw_set_out_dma(ctx);
 679
 680         fimc_activate_capture(ctx);
 681
 682         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 683                        FIMC_SRC_FMT | FIMC_DST_FMT);
 684         fimc_hw_activate_input_dma(fimc, true);
 685         spin_unlock(&fimc->slock);
 686
 687 dma_unlock:
 688         spin_unlock_irqrestore(&ctx->slock, flags);
 689 }
 690
 691 static void fimc_job_abort(void *priv)
 692 {
 693         fimc_m2m_shutdown(priv);
 694 }
 695
 696 static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
 697                             unsigned int *num_planes, unsigned long sizes[],
 698                             void *allocators[])
 699 {
 700         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 701         struct fimc_frame *f;
 702         int i;
 703
 704         f = ctx_get_frame(ctx, vq->type);
 705         if (IS_ERR(f))
 706                 return PTR_ERR(f);
 707
 708         /*
 709          * Return number of non-contigous planes (plane buffers)
 710          * depending on the configured color format.
 711          */
 712         if (f->fmt)
 713                 *num_planes = f->fmt->memplanes;
 714
 715         for (i = 0; i < f->fmt->memplanes; i++) {
 716                 sizes[i] = (f->width * f->height * f->fmt->depth[i]) >> 3;
 717                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 718         }
 719
 720         if (*num_buffers == 0)
 721                 *num_buffers = 1;
 722
 723         return 0;
 724 }
 725
 726 static int fimc_buf_prepare(struct vb2_buffer *vb)
 727 {
 728         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 729         struct fimc_frame *frame;
 730         int i;
 731
 732         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 733         if (IS_ERR(frame))
 734                 return PTR_ERR(frame);
 735
 736         for (i = 0; i < frame->fmt->memplanes; i++)
 737                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 738
 739         return 0;
 740 }
 741
 742 static void fimc_buf_queue(struct vb2_buffer *vb)
 743 {
 744         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 745
 746         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 747
 748         if (ctx->m2m_ctx)
 749                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 750 }
 751
 752 static void fimc_lock(struct vb2_queue *vq)
 753 {
 754         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 755         mutex_lock(&ctx->fimc_dev->lock);
 756 }
 757
 758 static void fimc_unlock(struct vb2_queue *vq)
 759 {
 760         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 761         mutex_unlock(&ctx->fimc_dev->lock);
 762 }
 763
 764 static struct vb2_ops fimc_qops = {
 765         .queue_setup     = fimc_queue_setup,
 766         .buf_prepare     = fimc_buf_prepare,
 767         .buf_queue       = fimc_buf_queue,
 768         .wait_prepare    = fimc_unlock,
 769         .wait_finish     = fimc_lock,
 770         .stop_streaming  = stop_streaming,
 771 };
 772
 773 static int fimc_m2m_querycap(struct file *file, void *priv,
 774                            struct v4l2_capability *cap)
 775 {
 776         struct fimc_ctx *ctx = file->private_data;
 777         struct fimc_dev *fimc = ctx->fimc_dev;
 778
 779         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 780         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 781         cap->bus_info[0] = 0;
 782         cap->version = KERNEL_VERSION(1, 0, 0);
 783         cap->capabilities = V4L2_CAP_STREAMING |
 784                 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
 785                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 786
 787         return 0;
 788 }
 789
 790 int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
 791                                 struct v4l2_fmtdesc *f)
 792 {
 793         struct fimc_fmt *fmt;
 794
 795         if (f->index >= ARRAY_SIZE(fimc_formats))
 796                 return -EINVAL;
 797
 798         fmt = &fimc_formats[f->index];
 799         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 800         f->pixelformat = fmt->fourcc;
 801
 802         return 0;
 803 }
 804
 805 int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
 806                              struct v4l2_format *f)
 807 {
 808         struct fimc_ctx *ctx = priv;
 809         struct fimc_frame *frame;
 810         struct v4l2_pix_format_mplane *pixm;
 811         int i;
 812
 813         frame = ctx_get_frame(ctx, f->type);
 814         if (IS_ERR(frame))
 815                 return PTR_ERR(frame);
 816
 817         pixm = &f->fmt.pix_mp;
 818
 819         pixm->width             = frame->width;
 820         pixm->height            = frame->height;
 821         pixm->field             = V4L2_FIELD_NONE;
 822         pixm->pixelformat       = frame->fmt->fourcc;
 823         pixm->colorspace        = V4L2_COLORSPACE_JPEG;
 824         pixm->num_planes        = frame->fmt->memplanes;
 825
 826         for (i = 0; i < pixm->num_planes; ++i) {
 827                 int bpl = frame->o_width;
 828
 829                 if (frame->fmt->colplanes == 1) /* packed formats */
 830                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 831
 832                 pixm->plane_fmt[i].bytesperline = bpl;
 833
 834                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 835                         frame->o_height * frame->fmt->depth[i]) / 8;
 836         }
 837
 838         return 0;
 839 }
 840
 841 struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
 842 {
 843         struct fimc_fmt *fmt;
 844         unsigned int i;
 845
 846         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 847                 fmt = &fimc_formats[i];
 848                 if (fmt->fourcc == f->fmt.pix.pixelformat &&
 849                    (fmt->flags & mask))
 850                         break;
 851         }
 852
 853         return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
 854 }
 855
 856 struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
 857                                   unsigned int mask)
 858 {
 859         struct fimc_fmt *fmt;
 860         unsigned int i;
 861
 862         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
 863                 fmt = &fimc_formats[i];
 864                 if (fmt->mbus_code == f->code && (fmt->flags & mask))
 865                         break;
 866         }
 867
 868         return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
 869 }
 870
 871
 872 int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
 873                                struct v4l2_format *f)
 874 {
 875         struct fimc_ctx *ctx = priv;
 876         struct fimc_dev *fimc = ctx->fimc_dev;
 877         struct samsung_fimc_variant *variant = fimc->variant;
 878         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
 879         struct fimc_fmt *fmt;
 880         u32 max_width, mod_x, mod_y, mask;
 881         int i, is_output = 0;
 882
 883
 884         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 885                 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
 886                         return -EINVAL;
 887                 is_output = 1;
 888         } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
 889                 return -EINVAL;
 890         }
 891
 892         dbg("w: %d, h: %d", pix->width, pix->height);
 893
 894         mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
 895         fmt = find_format(f, mask);
 896         if (!fmt) {
 897                 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
 898                          pix->pixelformat);
 899                 return -EINVAL;
 900         }
 901
 902         if (pix->field == V4L2_FIELD_ANY)
 903                 pix->field = V4L2_FIELD_NONE;
 904         else if (V4L2_FIELD_NONE != pix->field)
 905                 return -EINVAL;
 906
 907         if (is_output) {
 908                 max_width = variant->pix_limit->scaler_dis_w;
 909                 mod_x = ffs(variant->min_inp_pixsize) - 1;
 910         } else {
 911                 max_width = variant->pix_limit->out_rot_dis_w;
 912                 mod_x = ffs(variant->min_out_pixsize) - 1;
 913         }
 914
 915         if (tiled_fmt(fmt)) {
 916                 mod_x = 6; /* 64 x 32 pixels tile */
 917                 mod_y = 5;
 918         } else {
 919                 if (fimc->id == 1 && variant->pix_hoff)
 920                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
 921                 else
 922                         mod_y = mod_x;
 923         }
 924
 925         dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
 926
 927         v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
 928                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
 929
 930         pix->num_planes = fmt->memplanes;
 931         pix->colorspace = V4L2_COLORSPACE_JPEG;
 932
 933
 934         for (i = 0; i < pix->num_planes; ++i) {
 935                 u32 bpl = pix->plane_fmt[i].bytesperline;
 936                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
 937
 938                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 939                         bpl = pix->width; /* Planar */
 940
 941                 if (fmt->colplanes == 1 && /* Packed */
 942                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 943                         bpl = (pix->width * fmt->depth[0]) / 8;
 944
 945                 if (i == 0) /* Same bytesperline for each plane. */
 946                         mod_x = bpl;
 947
 948                 pix->plane_fmt[i].bytesperline = mod_x;
 949                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
 950         }
 951
 952         return 0;
 953 }
 954
 955 static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
 956                                  struct v4l2_format *f)
 957 {
 958         struct fimc_ctx *ctx = priv;
 959         struct fimc_dev *fimc = ctx->fimc_dev;
 960         struct vb2_queue *vq;
 961         struct fimc_frame *frame;
 962         struct v4l2_pix_format_mplane *pix;
 963         int i, ret = 0;
 964
 965         ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
 966         if (ret)
 967                 return ret;
 968
 969         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
 970
 971         if (vb2_is_busy(vq)) {
 972                 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
 973                 return -EBUSY;
 974         }
 975
 976         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
 977                 frame = &ctx->s_frame;
 978         } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
 979                 frame = &ctx->d_frame;
 980         } else {
 981                 v4l2_err(&fimc->m2m.v4l2_dev,
 982                          "Wrong buffer/video queue type (%d)\n", f->type);
 983                 return -EINVAL;
 984         }
 985
 986         pix = &f->fmt.pix_mp;
 987         frame->fmt = find_format(f, FMT_FLAGS_M2M);
 988         if (!frame->fmt)
 989                 return -EINVAL;
 990
 991         for (i = 0; i < frame->fmt->colplanes; i++) {
 992                 frame->payload[i] =
 993                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
 994         }
 995
 996         frame->f_width  = pix->plane_fmt[0].bytesperline * 8 /
 997                 frame->fmt->depth[0];
 998         frame->f_height = pix->height;
 999         frame->width    = pix->width;
1000         frame->height   = pix->height;
1001         frame->o_width  = pix->width;
1002         frame->o_height = pix->height;
1003         frame->offs_h   = 0;
1004         frame->offs_v   = 0;
1005
1006         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1007                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1008         else
1009                 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1010
1011         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1012
1013         return 0;
1014 }
1015
1016 static int fimc_m2m_reqbufs(struct file *file, void *priv,
1017                           struct v4l2_requestbuffers *reqbufs)
1018 {
1019         struct fimc_ctx *ctx = priv;
1020         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1021 }
1022
1023 static int fimc_m2m_querybuf(struct file *file, void *priv,
1024                            struct v4l2_buffer *buf)
1025 {
1026         struct fimc_ctx *ctx = priv;
1027         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1028 }
1029
1030 static int fimc_m2m_qbuf(struct file *file, void *priv,
1031                           struct v4l2_buffer *buf)
1032 {
1033         struct fimc_ctx *ctx = priv;
1034
1035         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1036 }
1037
1038 static int fimc_m2m_dqbuf(struct file *file, void *priv,
1039                            struct v4l2_buffer *buf)
1040 {
1041         struct fimc_ctx *ctx = priv;
1042         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1043 }
1044
1045 static int fimc_m2m_streamon(struct file *file, void *priv,
1046                            enum v4l2_buf_type type)
1047 {
1048         struct fimc_ctx *ctx = priv;
1049
1050         /* The source and target color format need to be set */
1051         if (V4L2_TYPE_IS_OUTPUT(type)) {
1052                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1053                         return -EINVAL;
1054         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1055                 return -EINVAL;
1056         }
1057
1058         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1059 }
1060
1061 static int fimc_m2m_streamoff(struct file *file, void *priv,
1062                             enum v4l2_buf_type type)
1063 {
1064         struct fimc_ctx *ctx = priv;
1065         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1066 }
1067
1068 int fimc_vidioc_queryctrl(struct file *file, void *priv,
1069                             struct v4l2_queryctrl *qc)
1070 {
1071         struct fimc_ctx *ctx = priv;
1072         struct v4l2_queryctrl *c;
1073         int ret = -EINVAL;
1074
1075         c = get_ctrl(qc->id);
1076         if (c) {
1077                 *qc = *c;
1078                 return 0;
1079         }
1080
1081         if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1082                 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1083                                         core, queryctrl, qc);
1084         }
1085         return ret;
1086 }
1087
1088 int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1089                          struct v4l2_control *ctrl)
1090 {
1091         struct fimc_ctx *ctx = priv;
1092         struct fimc_dev *fimc = ctx->fimc_dev;
1093
1094         switch (ctrl->id) {
1095         case V4L2_CID_HFLIP:
1096                 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1097                 break;
1098         case V4L2_CID_VFLIP:
1099                 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1100                 break;
1101         case V4L2_CID_ROTATE:
1102                 ctrl->value = ctx->rotation;
1103                 break;
1104         default:
1105                 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1106                         return v4l2_subdev_call(fimc->vid_cap.sd, core,
1107                                                 g_ctrl, ctrl);
1108                 } else {
1109                         v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1110                         return -EINVAL;
1111                 }
1112         }
1113         dbg("ctrl->value= %d", ctrl->value);
1114
1115         return 0;
1116 }
1117
1118 int check_ctrl_val(struct fimc_ctx *ctx,  struct v4l2_control *ctrl)
1119 {
1120         struct v4l2_queryctrl *c;
1121         c = get_ctrl(ctrl->id);
1122         if (!c)
1123                 return -EINVAL;
1124
1125         if (ctrl->value < c->minimum || ctrl->value > c->maximum
1126                 || (c->step != 0 && ctrl->value % c->step != 0)) {
1127                 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1128                 "Invalid control value\n");
1129                 return -ERANGE;
1130         }
1131
1132         return 0;
1133 }
1134
1135 int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1136 {
1137         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1138         struct fimc_dev *fimc = ctx->fimc_dev;
1139         int ret = 0;
1140
1141         switch (ctrl->id) {
1142         case V4L2_CID_HFLIP:
1143                 if (ctrl->value)
1144                         ctx->flip |= FLIP_X_AXIS;
1145                 else
1146                         ctx->flip &= ~FLIP_X_AXIS;
1147                 break;
1148
1149         case V4L2_CID_VFLIP:
1150                 if (ctrl->value)
1151                         ctx->flip |= FLIP_Y_AXIS;
1152                 else
1153                         ctx->flip &= ~FLIP_Y_AXIS;
1154                 break;
1155
1156         case V4L2_CID_ROTATE:
1157                 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1158                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1159                                         ctx->s_frame.height, ctx->d_frame.width,
1160                                         ctx->d_frame.height, ctrl->value);
1161                 }
1162
1163                 if (ret) {
1164                         v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1165                         return -EINVAL;
1166                 }
1167
1168                 /* Check for the output rotator availability */
1169                 if ((ctrl->value == 90 || ctrl->value == 270) &&
1170                     (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1171                         return -EINVAL;
1172                 ctx->rotation = ctrl->value;
1173                 break;
1174
1175         default:
1176                 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1177                 return -EINVAL;
1178         }
1179
1180         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1181
1182         return 0;
1183 }
1184
1185 static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1186                            struct v4l2_control *ctrl)
1187 {
1188         struct fimc_ctx *ctx = priv;
1189         int ret = 0;
1190
1191         ret = check_ctrl_val(ctx, ctrl);
1192         if (ret)
1193                 return ret;
1194
1195         ret = fimc_s_ctrl(ctx, ctrl);
1196         return 0;
1197 }
1198
1199 static int fimc_m2m_cropcap(struct file *file, void *fh,
1200                         struct v4l2_cropcap *cr)
1201 {
1202         struct fimc_frame *frame;
1203         struct fimc_ctx *ctx = fh;
1204
1205         frame = ctx_get_frame(ctx, cr->type);
1206         if (IS_ERR(frame))
1207                 return PTR_ERR(frame);
1208
1209         cr->bounds.left         = 0;
1210         cr->bounds.top          = 0;
1211         cr->bounds.width        = frame->f_width;
1212         cr->bounds.height       = frame->f_height;
1213         cr->defrect             = cr->bounds;
1214
1215         return 0;
1216 }
1217
1218 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1219 {
1220         struct fimc_frame *frame;
1221         struct fimc_ctx *ctx = file->private_data;
1222
1223         frame = ctx_get_frame(ctx, cr->type);
1224         if (IS_ERR(frame))
1225                 return PTR_ERR(frame);
1226
1227         cr->c.left = frame->offs_h;
1228         cr->c.top = frame->offs_v;
1229         cr->c.width = frame->width;
1230         cr->c.height = frame->height;
1231
1232         return 0;
1233 }
1234
1235 int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1236 {
1237         struct fimc_dev *fimc = ctx->fimc_dev;
1238         struct fimc_frame *f;
1239         u32 min_size, halign, depth = 0;
1240         bool is_capture_ctx;
1241         int i;
1242
1243         if (cr->c.top < 0 || cr->c.left < 0) {
1244                 v4l2_err(&fimc->m2m.v4l2_dev,
1245                         "doesn't support negative values for top & left\n");
1246                 return -EINVAL;
1247         }
1248
1249         is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1250
1251         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1252                 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1253         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1254                  !is_capture_ctx)
1255                 f = &ctx->s_frame;
1256         else
1257                 return -EINVAL;
1258
1259         min_size = (f == &ctx->s_frame) ?
1260                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1261
1262         /* Get pixel alignment constraints. */
1263         if (is_capture_ctx) {
1264                 min_size = 16;
1265                 halign = 4;
1266         } else {
1267                 if (fimc->id == 1 && fimc->variant->pix_hoff)
1268                         halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1269                 else
1270                         halign = ffs(min_size) - 1;
1271         }
1272
1273         for (i = 0; i < f->fmt->colplanes; i++)
1274                 depth += f->fmt->depth[i];
1275
1276         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1277                               ffs(min_size) - 1,
1278                               &cr->c.height, min_size, f->o_height,
1279                               halign, 64/(ALIGN(depth, 8)));
1280
1281         /* adjust left/top if cropping rectangle is out of bounds */
1282         if (cr->c.left + cr->c.width > f->o_width)
1283                 cr->c.left = f->o_width - cr->c.width;
1284         if (cr->c.top + cr->c.height > f->o_height)
1285                 cr->c.top = f->o_height - cr->c.height;
1286
1287         cr->c.left = round_down(cr->c.left, min_size);
1288         cr->c.top  = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1289
1290         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1291             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1292             f->f_width, f->f_height);
1293
1294         return 0;
1295 }
1296
1297 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1298 {
1299         struct fimc_ctx *ctx = file->private_data;
1300         struct fimc_dev *fimc = ctx->fimc_dev;
1301         struct fimc_frame *f;
1302         int ret;
1303
1304         ret = fimc_try_crop(ctx, cr);
1305         if (ret)
1306                 return ret;
1307
1308         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1309                 &ctx->s_frame : &ctx->d_frame;
1310
1311         /* Check to see if scaling ratio is within supported range */
1312         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1313                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1314                         ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1315                                                       ctx->d_frame.width,
1316                                                       ctx->d_frame.height,
1317                                                       ctx->rotation);
1318                 } else {
1319                         ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1320                                                       ctx->s_frame.height,
1321                                                       cr->c.width, cr->c.height,
1322                                                       ctx->rotation);
1323                 }
1324                 if (ret) {
1325                         v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1326                         return -EINVAL;
1327                 }
1328         }
1329
1330         f->offs_h = cr->c.left;
1331         f->offs_v = cr->c.top;
1332         f->width  = cr->c.width;
1333         f->height = cr->c.height;
1334
1335         fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1336
1337         return 0;
1338 }
1339
1340 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1341         .vidioc_querycap                = fimc_m2m_querycap,
1342
1343         .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1344         .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1345
1346         .vidioc_g_fmt_vid_cap_mplane    = fimc_vidioc_g_fmt_mplane,
1347         .vidioc_g_fmt_vid_out_mplane    = fimc_vidioc_g_fmt_mplane,
1348
1349         .vidioc_try_fmt_vid_cap_mplane  = fimc_vidioc_try_fmt_mplane,
1350         .vidioc_try_fmt_vid_out_mplane  = fimc_vidioc_try_fmt_mplane,
1351
1352         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1353         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1354
1355         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1356         .vidioc_querybuf                = fimc_m2m_querybuf,
1357
1358         .vidioc_qbuf                    = fimc_m2m_qbuf,
1359         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1360
1361         .vidioc_streamon                = fimc_m2m_streamon,
1362         .vidioc_streamoff               = fimc_m2m_streamoff,
1363
1364         .vidioc_queryctrl               = fimc_vidioc_queryctrl,
1365         .vidioc_g_ctrl                  = fimc_vidioc_g_ctrl,
1366         .vidioc_s_ctrl                  = fimc_m2m_s_ctrl,
1367
1368         .vidioc_g_crop                  = fimc_m2m_g_crop,
1369         .vidioc_s_crop                  = fimc_m2m_s_crop,
1370         .vidioc_cropcap                 = fimc_m2m_cropcap
1371
1372 };
1373
1374 static int queue_init(void *priv, struct vb2_queue *src_vq,
1375                       struct vb2_queue *dst_vq)
1376 {
1377         struct fimc_ctx *ctx = priv;
1378         int ret;
1379
1380         memset(src_vq, 0, sizeof(*src_vq));
1381         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1382         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1383         src_vq->drv_priv = ctx;
1384         src_vq->ops = &fimc_qops;
1385         src_vq->mem_ops = &vb2_dma_contig_memops;
1386         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1387
1388         ret = vb2_queue_init(src_vq);
1389         if (ret)
1390                 return ret;
1391
1392         memset(dst_vq, 0, sizeof(*dst_vq));
1393         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1394         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1395         dst_vq->drv_priv = ctx;
1396         dst_vq->ops = &fimc_qops;
1397         dst_vq->mem_ops = &vb2_dma_contig_memops;
1398         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1399
1400         return vb2_queue_init(dst_vq);
1401 }
1402
1403 static int fimc_m2m_open(struct file *file)
1404 {
1405         struct fimc_dev *fimc = video_drvdata(file);
1406         struct fimc_ctx *ctx = NULL;
1407
1408         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1409                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1410
1411         /*
1412          * Return if the corresponding video capture node
1413          * is already opened.
1414          */
1415         if (fimc->vid_cap.refcnt > 0)
1416                 return -EBUSY;
1417
1418         fimc->m2m.refcnt++;
1419         set_bit(ST_OUTDMA_RUN, &fimc->state);
1420
1421         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1422         if (!ctx)
1423                 return -ENOMEM;
1424
1425         file->private_data = ctx;
1426         ctx->fimc_dev = fimc;
1427         /* Default color format */
1428         ctx->s_frame.fmt = &fimc_formats[0];
1429         ctx->d_frame.fmt = &fimc_formats[0];
1430         /* Setup the device context for mem2mem mode. */
1431         ctx->state = FIMC_CTX_M2M;
1432         ctx->flags = 0;
1433         ctx->in_path = FIMC_DMA;
1434         ctx->out_path = FIMC_DMA;
1435         spin_lock_init(&ctx->slock);
1436
1437         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1438         if (IS_ERR(ctx->m2m_ctx)) {
1439                 int err = PTR_ERR(ctx->m2m_ctx);
1440                 kfree(ctx);
1441                 return err;
1442         }
1443
1444         return 0;
1445 }
1446
1447 static int fimc_m2m_release(struct file *file)
1448 {
1449         struct fimc_ctx *ctx = file->private_data;
1450         struct fimc_dev *fimc = ctx->fimc_dev;
1451
1452         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1453                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1454
1455         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1456         kfree(ctx);
1457         if (--fimc->m2m.refcnt <= 0)
1458                 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1459
1460         return 0;
1461 }
1462
1463 static unsigned int fimc_m2m_poll(struct file *file,
1464                                      struct poll_table_struct *wait)
1465 {
1466         struct fimc_ctx *ctx = file->private_data;
1467
1468         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1469 }
1470
1471
1472 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1473 {
1474         struct fimc_ctx *ctx = file->private_data;
1475
1476         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1477 }
1478
1479 static const struct v4l2_file_operations fimc_m2m_fops = {
1480         .owner          = THIS_MODULE,
1481         .open           = fimc_m2m_open,
1482         .release        = fimc_m2m_release,
1483         .poll           = fimc_m2m_poll,
1484         .unlocked_ioctl = video_ioctl2,
1485         .mmap           = fimc_m2m_mmap,
1486 };
1487
1488 static struct v4l2_m2m_ops m2m_ops = {
1489         .device_run     = fimc_dma_run,
1490         .job_abort      = fimc_job_abort,
1491 };
1492
1493 static int fimc_register_m2m_device(struct fimc_dev *fimc)
1494 {
1495         struct video_device *vfd;
1496         struct platform_device *pdev;
1497         struct v4l2_device *v4l2_dev;
1498         int ret = 0;
1499
1500         if (!fimc)
1501                 return -ENODEV;
1502
1503         pdev = fimc->pdev;
1504         v4l2_dev = &fimc->m2m.v4l2_dev;
1505
1506         /* set name if it is empty */
1507         if (!v4l2_dev->name[0])
1508                 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1509                          "%s.m2m", dev_name(&pdev->dev));
1510
1511         ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1512         if (ret)
1513                 goto err_m2m_r1;
1514
1515         vfd = video_device_alloc();
1516         if (!vfd) {
1517                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1518                 goto err_m2m_r1;
1519         }
1520
1521         vfd->fops       = &fimc_m2m_fops;
1522         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1523         vfd->minor      = -1;
1524         vfd->release    = video_device_release;
1525         vfd->lock       = &fimc->lock;
1526
1527         snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1528
1529         video_set_drvdata(vfd, fimc);
1530         platform_set_drvdata(pdev, fimc);
1531
1532         fimc->m2m.vfd = vfd;
1533         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1534         if (IS_ERR(fimc->m2m.m2m_dev)) {
1535                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1536                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1537                 goto err_m2m_r2;
1538         }
1539
1540         ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1541         if (ret) {
1542                 v4l2_err(v4l2_dev,
1543                          "%s(): failed to register video device\n", __func__);
1544                 goto err_m2m_r3;
1545         }
1546         v4l2_info(v4l2_dev,
1547                   "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1548
1549         return 0;
1550
1551 err_m2m_r3:
1552         v4l2_m2m_release(fimc->m2m.m2m_dev);
1553 err_m2m_r2:
1554         video_device_release(fimc->m2m.vfd);
1555 err_m2m_r1:
1556         v4l2_device_unregister(v4l2_dev);
1557
1558         return ret;
1559 }
1560
1561 static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1562 {
1563         if (fimc) {
1564                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1565                 video_unregister_device(fimc->m2m.vfd);
1566
1567                 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1568         }
1569 }
1570
1571 static void fimc_clk_release(struct fimc_dev *fimc)
1572 {
1573         int i;
1574         for (i = 0; i < fimc->num_clocks; i++) {
1575                 if (fimc->clock[i]) {
1576                         clk_disable(fimc->clock[i]);
1577                         clk_put(fimc->clock[i]);
1578                 }
1579         }
1580 }
1581
1582 static int fimc_clk_get(struct fimc_dev *fimc)
1583 {
1584         int i;
1585         for (i = 0; i < fimc->num_clocks; i++) {
1586                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1587
1588                 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1589                         clk_enable(fimc->clock[i]);
1590                         continue;
1591                 }
1592                 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1593                         fimc_clocks[i]);
1594                 return -ENXIO;
1595         }
1596         return 0;
1597 }
1598
1599 static int fimc_probe(struct platform_device *pdev)
1600 {
1601         struct fimc_dev *fimc;
1602         struct resource *res;
1603         struct samsung_fimc_driverdata *drv_data;
1604         struct s5p_platform_fimc *pdata;
1605         int ret = 0;
1606         int cap_input_index = -1;
1607
1608         dev_dbg(&pdev->dev, "%s():\n", __func__);
1609
1610         drv_data = (struct samsung_fimc_driverdata *)
1611                 platform_get_device_id(pdev)->driver_data;
1612
1613         if (pdev->id >= drv_data->num_entities) {
1614                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1615                         pdev->id);
1616                 return -EINVAL;
1617         }
1618
1619         fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1620         if (!fimc)
1621                 return -ENOMEM;
1622
1623         fimc->id = pdev->id;
1624         fimc->variant = drv_data->variant[fimc->id];
1625         fimc->pdev = pdev;
1626         pdata = pdev->dev.platform_data;
1627         fimc->pdata = pdata;
1628         fimc->state = ST_IDLE;
1629
1630         init_waitqueue_head(&fimc->irq_queue);
1631         spin_lock_init(&fimc->slock);
1632
1633         mutex_init(&fimc->lock);
1634
1635         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1636         if (!res) {
1637                 dev_err(&pdev->dev, "failed to find the registers\n");
1638                 ret = -ENOENT;
1639                 goto err_info;
1640         }
1641
1642         fimc->regs_res = request_mem_region(res->start, resource_size(res),
1643                         dev_name(&pdev->dev));
1644         if (!fimc->regs_res) {
1645                 dev_err(&pdev->dev, "failed to obtain register region\n");
1646                 ret = -ENOENT;
1647                 goto err_info;
1648         }
1649
1650         fimc->regs = ioremap(res->start, resource_size(res));
1651         if (!fimc->regs) {
1652                 dev_err(&pdev->dev, "failed to map registers\n");
1653                 ret = -ENXIO;
1654                 goto err_req_region;
1655         }
1656
1657         fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1658
1659         /* Check if a video capture node needs to be registered. */
1660         if (pdata && pdata->num_clients > 0) {
1661                 cap_input_index = 0;
1662                 fimc->num_clocks++;
1663         }
1664
1665         ret = fimc_clk_get(fimc);
1666         if (ret)
1667                 goto err_regs_unmap;
1668         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1669
1670         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1671         if (!res) {
1672                 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1673                 ret = -ENXIO;
1674                 goto err_clk;
1675         }
1676         fimc->irq = res->start;
1677
1678         fimc_hw_reset(fimc);
1679
1680         ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1681         if (ret) {
1682                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1683                 goto err_clk;
1684         }
1685
1686         /* Initialize contiguous memory allocator */
1687         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1688         if (IS_ERR(fimc->alloc_ctx)) {
1689                 ret = PTR_ERR(fimc->alloc_ctx);
1690                 goto err_irq;
1691         }
1692
1693         ret = fimc_register_m2m_device(fimc);
1694         if (ret)
1695                 goto err_irq;
1696
1697         /* At least one camera sensor is required to register capture node */
1698         if (cap_input_index >= 0) {
1699                 ret = fimc_register_capture_device(fimc);
1700                 if (ret)
1701                         goto err_m2m;
1702                 clk_disable(fimc->clock[CLK_CAM]);
1703         }
1704         /*
1705          * Exclude the additional output DMA address registers by masking
1706          * them out on HW revisions that provide extended capabilites.
1707          */
1708         if (fimc->variant->out_buf_count > 4)
1709                 fimc_hw_set_dma_seq(fimc, 0xF);
1710
1711         dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1712                 __func__, fimc->id);
1713
1714         return 0;
1715
1716 err_m2m:
1717         fimc_unregister_m2m_device(fimc);
1718 err_irq:
1719         free_irq(fimc->irq, fimc);
1720 err_clk:
1721         fimc_clk_release(fimc);
1722 err_regs_unmap:
1723         iounmap(fimc->regs);
1724 err_req_region:
1725         release_resource(fimc->regs_res);
1726         kfree(fimc->regs_res);
1727 err_info:
1728         kfree(fimc);
1729
1730         return ret;
1731 }
1732
1733 static int __devexit fimc_remove(struct platform_device *pdev)
1734 {
1735         struct fimc_dev *fimc =
1736                 (struct fimc_dev *)platform_get_drvdata(pdev);
1737
1738         free_irq(fimc->irq, fimc);
1739         fimc_hw_reset(fimc);
1740
1741         fimc_unregister_m2m_device(fimc);
1742         fimc_unregister_capture_device(fimc);
1743
1744         fimc_clk_release(fimc);
1745
1746         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1747
1748         iounmap(fimc->regs);
1749         release_resource(fimc->regs_res);
1750         kfree(fimc->regs_res);
1751         kfree(fimc);
1752
1753         dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1754         return 0;
1755 }
1756
1757 /* Image pixel limits, similar across several FIMC HW revisions. */
1758 static struct fimc_pix_limit s5p_pix_limit[4] = {
1759         [0] = {
1760                 .scaler_en_w    = 3264,
1761                 .scaler_dis_w   = 8192,
1762                 .in_rot_en_h    = 1920,
1763                 .in_rot_dis_w   = 8192,
1764                 .out_rot_en_w   = 1920,
1765                 .out_rot_dis_w  = 4224,
1766         },
1767         [1] = {
1768                 .scaler_en_w    = 4224,
1769                 .scaler_dis_w   = 8192,
1770                 .in_rot_en_h    = 1920,
1771                 .in_rot_dis_w   = 8192,
1772                 .out_rot_en_w   = 1920,
1773                 .out_rot_dis_w  = 4224,
1774         },
1775         [2] = {
1776                 .scaler_en_w    = 1920,
1777                 .scaler_dis_w   = 8192,
1778                 .in_rot_en_h    = 1280,
1779                 .in_rot_dis_w   = 8192,
1780                 .out_rot_en_w   = 1280,
1781                 .out_rot_dis_w  = 1920,
1782         },
1783         [3] = {
1784                 .scaler_en_w    = 1920,
1785                 .scaler_dis_w   = 8192,
1786                 .in_rot_en_h    = 1366,
1787                 .in_rot_dis_w   = 8192,
1788                 .out_rot_en_w   = 1366,
1789                 .out_rot_dis_w  = 1920,
1790         },
1791 };
1792
1793 static struct samsung_fimc_variant fimc0_variant_s5p = {
1794         .has_inp_rot     = 1,
1795         .has_out_rot     = 1,
1796         .min_inp_pixsize = 16,
1797         .min_out_pixsize = 16,
1798         .hor_offs_align  = 8,
1799         .out_buf_count   = 4,
1800         .pix_limit       = &s5p_pix_limit[0],
1801 };
1802
1803 static struct samsung_fimc_variant fimc2_variant_s5p = {
1804         .min_inp_pixsize = 16,
1805         .min_out_pixsize = 16,
1806         .hor_offs_align  = 8,
1807         .out_buf_count   = 4,
1808         .pix_limit = &s5p_pix_limit[1],
1809 };
1810
1811 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1812         .pix_hoff        = 1,
1813         .has_inp_rot     = 1,
1814         .has_out_rot     = 1,
1815         .min_inp_pixsize = 16,
1816         .min_out_pixsize = 16,
1817         .hor_offs_align  = 8,
1818         .out_buf_count   = 4,
1819         .pix_limit       = &s5p_pix_limit[1],
1820 };
1821
1822 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1823         .pix_hoff        = 1,
1824         .has_inp_rot     = 1,
1825         .has_out_rot     = 1,
1826         .has_mainscaler_ext = 1,
1827         .min_inp_pixsize = 16,
1828         .min_out_pixsize = 16,
1829         .hor_offs_align  = 1,
1830         .out_buf_count   = 4,
1831         .pix_limit       = &s5p_pix_limit[2],
1832 };
1833
1834 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1835         .pix_hoff        = 1,
1836         .min_inp_pixsize = 16,
1837         .min_out_pixsize = 16,
1838         .hor_offs_align  = 8,
1839         .out_buf_count   = 4,
1840         .pix_limit       = &s5p_pix_limit[2],
1841 };
1842
1843 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1844         .pix_hoff        = 1,
1845         .has_inp_rot     = 1,
1846         .has_out_rot     = 1,
1847         .has_cistatus2   = 1,
1848         .has_mainscaler_ext = 1,
1849         .min_inp_pixsize = 16,
1850         .min_out_pixsize = 16,
1851         .hor_offs_align  = 1,
1852         .out_buf_count   = 32,
1853         .pix_limit       = &s5p_pix_limit[1],
1854 };
1855
1856 static struct samsung_fimc_variant fimc2_variant_exynos4 = {
1857         .pix_hoff        = 1,
1858         .has_cistatus2   = 1,
1859         .has_mainscaler_ext = 1,
1860         .min_inp_pixsize = 16,
1861         .min_out_pixsize = 16,
1862         .hor_offs_align  = 1,
1863         .out_buf_count   = 32,
1864         .pix_limit       = &s5p_pix_limit[3],
1865 };
1866
1867 /* S5PC100 */
1868 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1869         .variant = {
1870                 [0] = &fimc0_variant_s5p,
1871                 [1] = &fimc0_variant_s5p,
1872                 [2] = &fimc2_variant_s5p,
1873         },
1874         .num_entities = 3,
1875         .lclk_frequency = 133000000UL,
1876 };
1877
1878 /* S5PV210, S5PC110 */
1879 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1880         .variant = {
1881                 [0] = &fimc0_variant_s5pv210,
1882                 [1] = &fimc1_variant_s5pv210,
1883                 [2] = &fimc2_variant_s5pv210,
1884         },
1885         .num_entities = 3,
1886         .lclk_frequency = 166000000UL,
1887 };
1888
1889 /* S5PV310, S5PC210 */
1890 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1891         .variant = {
1892                 [0] = &fimc0_variant_exynos4,
1893                 [1] = &fimc0_variant_exynos4,
1894                 [2] = &fimc0_variant_exynos4,
1895                 [3] = &fimc2_variant_exynos4,
1896         },
1897         .num_entities = 4,
1898         .lclk_frequency = 166000000UL,
1899 };
1900
1901 static struct platform_device_id fimc_driver_ids[] = {
1902         {
1903                 .name           = "s5p-fimc",
1904                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1905         }, {
1906                 .name           = "s5pv210-fimc",
1907                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1908         }, {
1909                 .name           = "exynos4-fimc",
1910                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1911         },
1912         {},
1913 };
1914 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1915
1916 static struct platform_driver fimc_driver = {
1917         .probe          = fimc_probe,
1918         .remove = __devexit_p(fimc_remove),
1919         .id_table       = fimc_driver_ids,
1920         .driver = {
1921                 .name   = MODULE_NAME,
1922                 .owner  = THIS_MODULE,
1923         }
1924 };
1925
1926 static int __init fimc_init(void)
1927 {
1928         int ret = platform_driver_register(&fimc_driver);
1929         if (ret)
1930                 err("platform_driver_register failed: %d\n", ret);
1931         return ret;
1932 }
1933
1934 static void __exit fimc_exit(void)
1935 {
1936         platform_driver_unregister(&fimc_driver);
1937 }
1938
1939 module_init(fimc_init);
1940 module_exit(fimc_exit);
1941
1942 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1943 MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1944 MODULE_LICENSE("GPL");