2 * Kernel-based Virtual Machine driver for Linux
4 * derived from drivers/kvm/kvm_main.c
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
27 #include "kvm_cache_regs.h"
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <trace/events/kvm.h>
51 #define CREATE_TRACE_POINTS
54 #include <asm/debugreg.h>
61 #include <asm/pvclock.h>
62 #include <asm/div64.h>
64 #define MAX_IO_MSRS 256
65 #define KVM_MAX_MCE_BANKS 32
66 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
68 #define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
77 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
79 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
82 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
85 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
86 static void process_nmi(struct kvm_vcpu *vcpu);
88 struct kvm_x86_ops *kvm_x86_ops;
89 EXPORT_SYMBOL_GPL(kvm_x86_ops);
91 static bool ignore_msrs = 0;
92 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
94 bool kvm_has_tsc_control;
95 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96 u32 kvm_max_guest_tsc_khz;
97 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99 #define KVM_NR_SHARED_MSRS 16
101 struct kvm_shared_msrs_global {
103 u32 msrs[KVM_NR_SHARED_MSRS];
106 struct kvm_shared_msrs {
107 struct user_return_notifier urn;
109 struct kvm_shared_msr_values {
112 } values[KVM_NR_SHARED_MSRS];
115 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116 static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
118 struct kvm_stats_debugfs_item debugfs_entries[] = {
119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
131 { "hypercalls", VCPU_STAT(hypercalls) },
132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
139 { "irq_injections", VCPU_STAT(irq_injections) },
140 { "nmi_injections", VCPU_STAT(nmi_injections) },
141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
148 { "mmu_unsync", VM_STAT(mmu_unsync) },
149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
150 { "largepages", VM_STAT(lpages) },
154 u64 __read_mostly host_xcr0;
156 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
158 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
165 static void kvm_on_user_return(struct user_return_notifier *urn)
168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
170 struct kvm_shared_msr_values *values;
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
183 static void shared_msr_update(unsigned slot, u32 msr)
185 struct kvm_shared_msrs *smsr;
188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
200 void kvm_define_shared_msr(unsigned slot, u32 msr)
202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
208 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
210 static void kvm_shared_msr_cpu_online(void)
214 for (i = 0; i < shared_msrs_global.nr; ++i)
215 shared_msr_update(i, shared_msrs_global.msrs[i]);
218 void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
232 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
234 static void drop_user_return_notifiers(void *ignore)
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
242 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
244 if (irqchip_in_kernel(vcpu->kvm))
245 return vcpu->arch.apic_base;
247 return vcpu->arch.apic_base;
249 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
251 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
257 vcpu->arch.apic_base = data;
259 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
261 #define EXCPT_BENIGN 0
262 #define EXCPT_CONTRIBUTORY 1
265 static int exception_class(int vector)
275 return EXCPT_CONTRIBUTORY;
282 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
283 unsigned nr, bool has_error, u32 error_code,
289 kvm_make_request(KVM_REQ_EVENT, vcpu);
291 if (!vcpu->arch.exception.pending) {
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
297 vcpu->arch.exception.reinject = reinject;
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
324 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
326 kvm_multiple_exception(vcpu, nr, false, 0, false);
328 EXPORT_SYMBOL_GPL(kvm_queue_exception);
330 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
334 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
336 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
339 kvm_inject_gp(vcpu, 0);
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
343 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
345 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
347 ++vcpu->stat.pf_guest;
348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
351 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
353 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
361 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
363 atomic_inc(&vcpu->arch.nmi_queued);
364 kvm_make_request(KVM_REQ_NMI, vcpu);
366 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
368 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
372 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
374 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
378 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
384 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
391 EXPORT_SYMBOL_GPL(kvm_require_cpl);
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
398 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
410 real_gfn = gpa_to_gfn(real_gfn);
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
414 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
416 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
424 * Load the pae pdptrs. Return true is they are all valid.
426 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
442 if (is_present_gpte(pdpte[i]) &&
443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
459 EXPORT_SYMBOL_GPL(load_pdptrs);
461 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
488 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
497 if (cr0 & 0xffffffff00000000UL)
501 cr0 &= ~CR0_RESERVED_BITS;
503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
511 if ((vcpu->arch.efer & EFER_LME)) {
516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
526 kvm_x86_ops->set_cr0(vcpu, cr0);
528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
529 kvm_clear_async_pf_completion_queue(vcpu);
530 kvm_async_pf_hash_reset(vcpu);
533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
537 EXPORT_SYMBOL_GPL(kvm_set_cr0);
539 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
543 EXPORT_SYMBOL_GPL(kvm_lmsw);
545 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
555 if (!(xcr0 & XSTATE_FP))
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
559 if (xcr0 & ~host_xcr0)
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
566 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
574 EXPORT_SYMBOL_GPL(kvm_set_xcr);
576 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
578 unsigned long old_cr4 = kvm_read_cr4(vcpu);
579 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
580 X86_CR4_PAE | X86_CR4_SMEP;
581 if (cr4 & CR4_RESERVED_BITS)
584 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593 if (is_long_mode(vcpu)) {
594 if (!(cr4 & X86_CR4_PAE))
596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
602 if (kvm_x86_ops->set_cr4(vcpu, cr4))
605 if ((cr4 ^ old_cr4) & pdptr_bits)
606 kvm_mmu_reset_context(vcpu);
608 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
609 kvm_update_cpuid(vcpu);
613 EXPORT_SYMBOL_GPL(kvm_set_cr4);
615 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
617 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
618 kvm_mmu_sync_roots(vcpu);
619 kvm_mmu_flush_tlb(vcpu);
623 if (is_long_mode(vcpu)) {
624 if (cr3 & CR3_L_MODE_RESERVED_BITS)
628 if (cr3 & CR3_PAE_RESERVED_BITS)
630 if (is_paging(vcpu) &&
631 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
635 * We don't check reserved bits in nonpae mode, because
636 * this isn't enforced, and VMware depends on this.
641 * Does the new cr3 value map to physical memory? (Note, we
642 * catch an invalid cr3 even in real-mode, because it would
643 * cause trouble later on when we turn on paging anyway.)
645 * A real CPU would silently accept an invalid cr3 and would
646 * attempt to use it - with largely undefined (and often hard
647 * to debug) behavior on the guest side.
649 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
651 vcpu->arch.cr3 = cr3;
652 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
653 vcpu->arch.mmu.new_cr3(vcpu);
656 EXPORT_SYMBOL_GPL(kvm_set_cr3);
658 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
660 if (cr8 & CR8_RESERVED_BITS)
662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
665 vcpu->arch.cr8 = cr8;
668 EXPORT_SYMBOL_GPL(kvm_set_cr8);
670 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
672 if (irqchip_in_kernel(vcpu->kvm))
673 return kvm_lapic_get_cr8(vcpu);
675 return vcpu->arch.cr8;
677 EXPORT_SYMBOL_GPL(kvm_get_cr8);
679 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
683 vcpu->arch.db[dr] = val;
684 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
685 vcpu->arch.eff_db[dr] = val;
688 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
692 if (val & 0xffffffff00000000ULL)
694 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
697 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
701 if (val & 0xffffffff00000000ULL)
703 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
704 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
705 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
706 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
714 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
718 res = __kvm_set_dr(vcpu, dr, val);
720 kvm_queue_exception(vcpu, UD_VECTOR);
722 kvm_inject_gp(vcpu, 0);
726 EXPORT_SYMBOL_GPL(kvm_set_dr);
728 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
732 *val = vcpu->arch.db[dr];
735 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
739 *val = vcpu->arch.dr6;
742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
746 *val = vcpu->arch.dr7;
753 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
755 if (_kvm_get_dr(vcpu, dr, val)) {
756 kvm_queue_exception(vcpu, UD_VECTOR);
761 EXPORT_SYMBOL_GPL(kvm_get_dr);
763 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
765 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
769 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
772 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
773 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
776 EXPORT_SYMBOL_GPL(kvm_rdpmc);
779 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
780 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
782 * This list is modified at module load time to reflect the
783 * capabilities of the host cpu. This capabilities test skips MSRs that are
784 * kvm-specific. Those are put in the beginning of the list.
787 #define KVM_SAVE_MSRS_BEGIN 9
788 static u32 msrs_to_save[] = {
789 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
790 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
791 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
792 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
793 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
796 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
798 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
801 static unsigned num_msrs_to_save;
803 static u32 emulated_msrs[] = {
804 MSR_IA32_TSCDEADLINE,
805 MSR_IA32_MISC_ENABLE,
810 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
812 u64 old_efer = vcpu->arch.efer;
814 if (efer & efer_reserved_bits)
818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
838 efer |= vcpu->arch.efer & EFER_LMA;
840 kvm_x86_ops->set_efer(vcpu, efer);
842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
851 void kvm_enable_efer_bits(u64 mask)
853 efer_reserved_bits &= ~mask;
855 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
863 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
869 * Adapt set_msr() to msr_io()'s calling convention
871 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
873 return kvm_set_msr(vcpu, index, *data);
876 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
880 struct pvclock_wall_clock wc;
881 struct timespec boot;
886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
891 ++version; /* first time write, random junk */
895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
898 * The guest calculates current wall clock time by adding
899 * system time (updated by kvm_guest_time_update below) to the
900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
915 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
917 uint32_t quotient, remainder;
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
927 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
942 tps32 = (uint32_t)tps64;
943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
952 *pmultiplier = div_frac(scaled64, tps32);
954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
958 static inline u64 get_kernel_ns(void)
962 WARN_ON(preemptible());
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
968 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
969 unsigned long max_tsc_khz;
971 static inline int kvm_tsc_changes_freq(void)
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
980 u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
985 return __this_cpu_read(cpu_tsc_khz);
988 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
996 ret = nsec * vcpu_tsc_khz(vcpu);
997 do_div(ret, USEC_PER_SEC);
1001 static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
1009 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
1014 tsc += vcpu->arch.last_tsc_write;
1018 void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1020 struct kvm *kvm = vcpu->kvm;
1021 u64 offset, ns, elapsed;
1022 unsigned long flags;
1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1027 ns = get_kernel_ns();
1028 elapsed = ns - kvm->arch.last_tsc_nsec;
1029 sdiff = data - kvm->arch.last_tsc_write;
1034 * Special case: close write to TSC within 5 seconds of
1035 * another CPU is interpreted as an attempt to synchronize
1036 * The 5 seconds is to accommodate host load / swapping as
1037 * well as any reset of TSC during the boot process.
1039 * In that case, for a reliable TSC, we can match TSC offsets,
1040 * or make a best guest using elapsed value.
1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
1043 elapsed < 5ULL * NSEC_PER_SEC) {
1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1052 ns = kvm->arch.last_tsc_nsec;
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
1065 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1067 static int kvm_guest_time_update(struct kvm_vcpu *v)
1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1072 unsigned long this_tsc_khz;
1073 s64 kernel_ns, max_kernel_ns;
1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
1078 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
1079 kernel_ns = get_kernel_ns();
1080 this_tsc_khz = vcpu_tsc_khz(v);
1081 if (unlikely(this_tsc_khz == 0)) {
1082 local_irq_restore(flags);
1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1105 local_irq_restore(flags);
1107 if (!vcpu->time_page)
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
1145 vcpu->hw_tsc_khz = this_tsc_khz;
1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1151 /* With all the info we got, fill in the values */
1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1154 vcpu->last_kernel_ns = kernel_ns;
1155 vcpu->last_guest_tsc = tsc_timestamp;
1156 vcpu->hv_clock.flags = 0;
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
1161 * state, we just increase by 2 at the end.
1163 vcpu->hv_clock.version += 2;
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
1168 sizeof(vcpu->hv_clock));
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
1176 static bool msr_mtrr_valid(unsigned msr)
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1200 static bool valid_pat_type(unsigned t)
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1205 static bool valid_mtrr_type(unsigned t)
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1210 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1214 if (!msr_mtrr_valid(msr))
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1222 } else if (msr == MSR_MTRRdefType) {
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1237 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1241 if (!mtrr_valid(vcpu, msr, data))
1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1270 kvm_mmu_reset_context(vcpu);
1274 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1280 case MSR_IA32_MCG_STATUS:
1281 vcpu->arch.mcg_status = data;
1283 case MSR_IA32_MCG_CTL:
1284 if (!(mcg_cap & MCG_CTL_P))
1286 if (data != 0 && data != ~(u64)0)
1288 vcpu->arch.mcg_ctl = data;
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1299 if ((offset & 0x3) == 0 &&
1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
1302 vcpu->arch.mce_banks[offset] = data;
1310 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1324 if (page_num >= blob_size)
1327 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1332 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1341 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1343 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1346 static bool kvm_hv_msr_partition_wide(u32 msr)
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 case HV_X64_MSR_HYPERCALL:
1359 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361 struct kvm *kvm = vcpu->kvm;
1364 case HV_X64_MSR_GUEST_OS_ID:
1365 kvm->arch.hv_guest_os_id = data;
1366 /* setting guest os id to zero disables hypercall page */
1367 if (!kvm->arch.hv_guest_os_id)
1368 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1370 case HV_X64_MSR_HYPERCALL: {
1375 /* if guest os id is not set hypercall should remain disabled */
1376 if (!kvm->arch.hv_guest_os_id)
1378 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1379 kvm->arch.hv_hypercall = data;
1382 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1383 addr = gfn_to_hva(kvm, gfn);
1384 if (kvm_is_error_hva(addr))
1386 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1387 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1388 if (__copy_to_user((void __user *)addr, instructions, 4))
1390 kvm->arch.hv_hypercall = data;
1394 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1395 "data 0x%llx\n", msr, data);
1401 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1404 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1407 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1408 vcpu->arch.hv_vapic = data;
1411 addr = gfn_to_hva(vcpu->kvm, data >>
1412 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1413 if (kvm_is_error_hva(addr))
1415 if (__clear_user((void __user *)addr, PAGE_SIZE))
1417 vcpu->arch.hv_vapic = data;
1420 case HV_X64_MSR_EOI:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1422 case HV_X64_MSR_ICR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1424 case HV_X64_MSR_TPR:
1425 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1427 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1428 "data 0x%llx\n", msr, data);
1435 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1437 gpa_t gpa = data & ~0x3f;
1439 /* Bits 2:5 are resrved, Should be zero */
1443 vcpu->arch.apf.msr_val = data;
1445 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1446 kvm_clear_async_pf_completion_queue(vcpu);
1447 kvm_async_pf_hash_reset(vcpu);
1451 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1454 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1455 kvm_async_pf_wakeup_all(vcpu);
1459 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1461 if (vcpu->arch.time_page) {
1462 kvm_release_page_dirty(vcpu->arch.time_page);
1463 vcpu->arch.time_page = NULL;
1467 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1471 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1474 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1475 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1476 vcpu->arch.st.accum_steal = delta;
1479 static void record_steal_time(struct kvm_vcpu *vcpu)
1481 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1484 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1485 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1488 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1489 vcpu->arch.st.steal.version += 2;
1490 vcpu->arch.st.accum_steal = 0;
1492 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1493 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1496 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1502 return set_efer(vcpu, data);
1504 data &= ~(u64)0x40; /* ignore flush filter disable */
1505 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1507 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1512 case MSR_FAM10H_MMIO_CONF_BASE:
1514 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1519 case MSR_AMD64_NB_CFG:
1521 case MSR_IA32_DEBUGCTLMSR:
1523 /* We support the non-activated case already */
1525 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1526 /* Values other than LBR and BTF are vendor-specific,
1527 thus reserved and should throw a #GP */
1530 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1533 case MSR_IA32_UCODE_REV:
1534 case MSR_IA32_UCODE_WRITE:
1535 case MSR_VM_HSAVE_PA:
1536 case MSR_AMD64_PATCH_LOADER:
1538 case 0x200 ... 0x2ff:
1539 return set_msr_mtrr(vcpu, msr, data);
1540 case MSR_IA32_APICBASE:
1541 kvm_set_apic_base(vcpu, data);
1543 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1544 return kvm_x2apic_msr_write(vcpu, msr, data);
1545 case MSR_IA32_TSCDEADLINE:
1546 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1548 case MSR_IA32_MISC_ENABLE:
1549 vcpu->arch.ia32_misc_enable_msr = data;
1551 case MSR_KVM_WALL_CLOCK_NEW:
1552 case MSR_KVM_WALL_CLOCK:
1553 vcpu->kvm->arch.wall_clock = data;
1554 kvm_write_wall_clock(vcpu->kvm, data);
1556 case MSR_KVM_SYSTEM_TIME_NEW:
1557 case MSR_KVM_SYSTEM_TIME: {
1558 kvmclock_reset(vcpu);
1560 vcpu->arch.time = data;
1561 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
1563 /* we verify if the enable bit is set... */
1567 /* ...but clean it before doing the actual write */
1568 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1570 vcpu->arch.time_page =
1571 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
1573 if (is_error_page(vcpu->arch.time_page)) {
1574 kvm_release_page_clean(vcpu->arch.time_page);
1575 vcpu->arch.time_page = NULL;
1579 case MSR_KVM_ASYNC_PF_EN:
1580 if (kvm_pv_enable_async_pf(vcpu, data))
1583 case MSR_KVM_STEAL_TIME:
1585 if (unlikely(!sched_info_on()))
1588 if (data & KVM_STEAL_RESERVED_MASK)
1591 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1592 data & KVM_STEAL_VALID_BITS))
1595 vcpu->arch.st.msr_val = data;
1597 if (!(data & KVM_MSR_ENABLED))
1600 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1603 accumulate_steal_time(vcpu);
1606 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1610 case MSR_IA32_MCG_CTL:
1611 case MSR_IA32_MCG_STATUS:
1612 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1613 return set_msr_mce(vcpu, msr, data);
1615 /* Performance counters are not protected by a CPUID bit,
1616 * so we should check all of them in the generic path for the sake of
1617 * cross vendor migration.
1618 * Writing a zero into the event select MSRs disables them,
1619 * which we perfectly emulate ;-). Any other value should be at least
1620 * reported, some guests depend on them.
1622 case MSR_K7_EVNTSEL0:
1623 case MSR_K7_EVNTSEL1:
1624 case MSR_K7_EVNTSEL2:
1625 case MSR_K7_EVNTSEL3:
1627 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1628 "0x%x data 0x%llx\n", msr, data);
1630 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1631 * so we ignore writes to make it happy.
1633 case MSR_K7_PERFCTR0:
1634 case MSR_K7_PERFCTR1:
1635 case MSR_K7_PERFCTR2:
1636 case MSR_K7_PERFCTR3:
1637 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1638 "0x%x data 0x%llx\n", msr, data);
1640 case MSR_P6_PERFCTR0:
1641 case MSR_P6_PERFCTR1:
1643 case MSR_P6_EVNTSEL0:
1644 case MSR_P6_EVNTSEL1:
1645 if (kvm_pmu_msr(vcpu, msr))
1646 return kvm_pmu_set_msr(vcpu, msr, data);
1648 if (pr || data != 0)
1649 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1650 "0x%x data 0x%llx\n", msr, data);
1652 case MSR_K7_CLK_CTL:
1654 * Ignore all writes to this no longer documented MSR.
1655 * Writes are only relevant for old K7 processors,
1656 * all pre-dating SVM, but a recommended workaround from
1657 * AMD for these chips. It is possible to speicify the
1658 * affected processor models on the command line, hence
1659 * the need to ignore the workaround.
1662 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1663 if (kvm_hv_msr_partition_wide(msr)) {
1665 mutex_lock(&vcpu->kvm->lock);
1666 r = set_msr_hyperv_pw(vcpu, msr, data);
1667 mutex_unlock(&vcpu->kvm->lock);
1670 return set_msr_hyperv(vcpu, msr, data);
1672 case MSR_IA32_BBL_CR_CTL3:
1673 /* Drop writes to this legacy MSR -- see rdmsr
1674 * counterpart for further detail.
1676 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1678 case MSR_AMD64_OSVW_ID_LENGTH:
1679 if (!guest_cpuid_has_osvw(vcpu))
1681 vcpu->arch.osvw.length = data;
1683 case MSR_AMD64_OSVW_STATUS:
1684 if (!guest_cpuid_has_osvw(vcpu))
1686 vcpu->arch.osvw.status = data;
1689 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1690 return xen_hvm_config(vcpu, data);
1691 if (kvm_pmu_msr(vcpu, msr))
1692 return kvm_pmu_set_msr(vcpu, msr, data);
1694 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1698 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1705 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1709 * Reads an msr value (of 'msr_index') into 'pdata'.
1710 * Returns 0 on success, non-0 otherwise.
1711 * Assumes vcpu_load() was already called.
1713 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1715 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1718 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1720 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1722 if (!msr_mtrr_valid(msr))
1725 if (msr == MSR_MTRRdefType)
1726 *pdata = vcpu->arch.mtrr_state.def_type +
1727 (vcpu->arch.mtrr_state.enabled << 10);
1728 else if (msr == MSR_MTRRfix64K_00000)
1730 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1731 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1732 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1733 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1734 else if (msr == MSR_IA32_CR_PAT)
1735 *pdata = vcpu->arch.pat;
1736 else { /* Variable MTRRs */
1737 int idx, is_mtrr_mask;
1740 idx = (msr - 0x200) / 2;
1741 is_mtrr_mask = msr - 0x200 - 2 * idx;
1744 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1747 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1754 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1757 u64 mcg_cap = vcpu->arch.mcg_cap;
1758 unsigned bank_num = mcg_cap & 0xff;
1761 case MSR_IA32_P5_MC_ADDR:
1762 case MSR_IA32_P5_MC_TYPE:
1765 case MSR_IA32_MCG_CAP:
1766 data = vcpu->arch.mcg_cap;
1768 case MSR_IA32_MCG_CTL:
1769 if (!(mcg_cap & MCG_CTL_P))
1771 data = vcpu->arch.mcg_ctl;
1773 case MSR_IA32_MCG_STATUS:
1774 data = vcpu->arch.mcg_status;
1777 if (msr >= MSR_IA32_MC0_CTL &&
1778 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1779 u32 offset = msr - MSR_IA32_MC0_CTL;
1780 data = vcpu->arch.mce_banks[offset];
1789 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1792 struct kvm *kvm = vcpu->kvm;
1795 case HV_X64_MSR_GUEST_OS_ID:
1796 data = kvm->arch.hv_guest_os_id;
1798 case HV_X64_MSR_HYPERCALL:
1799 data = kvm->arch.hv_hypercall;
1802 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1810 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1815 case HV_X64_MSR_VP_INDEX: {
1818 kvm_for_each_vcpu(r, v, vcpu->kvm)
1823 case HV_X64_MSR_EOI:
1824 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1825 case HV_X64_MSR_ICR:
1826 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1827 case HV_X64_MSR_TPR:
1828 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
1829 case HV_X64_MSR_APIC_ASSIST_PAGE:
1830 data = vcpu->arch.hv_vapic;
1833 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1840 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1845 case MSR_IA32_PLATFORM_ID:
1846 case MSR_IA32_EBL_CR_POWERON:
1847 case MSR_IA32_DEBUGCTLMSR:
1848 case MSR_IA32_LASTBRANCHFROMIP:
1849 case MSR_IA32_LASTBRANCHTOIP:
1850 case MSR_IA32_LASTINTFROMIP:
1851 case MSR_IA32_LASTINTTOIP:
1854 case MSR_VM_HSAVE_PA:
1855 case MSR_K7_EVNTSEL0:
1856 case MSR_K7_PERFCTR0:
1857 case MSR_K8_INT_PENDING_MSG:
1858 case MSR_AMD64_NB_CFG:
1859 case MSR_FAM10H_MMIO_CONF_BASE:
1862 case MSR_P6_PERFCTR0:
1863 case MSR_P6_PERFCTR1:
1864 case MSR_P6_EVNTSEL0:
1865 case MSR_P6_EVNTSEL1:
1866 if (kvm_pmu_msr(vcpu, msr))
1867 return kvm_pmu_get_msr(vcpu, msr, pdata);
1870 case MSR_IA32_UCODE_REV:
1871 data = 0x100000000ULL;
1874 data = 0x500 | KVM_NR_VAR_MTRR;
1876 case 0x200 ... 0x2ff:
1877 return get_msr_mtrr(vcpu, msr, pdata);
1878 case 0xcd: /* fsb frequency */
1882 * MSR_EBC_FREQUENCY_ID
1883 * Conservative value valid for even the basic CPU models.
1884 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1885 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1886 * and 266MHz for model 3, or 4. Set Core Clock
1887 * Frequency to System Bus Frequency Ratio to 1 (bits
1888 * 31:24) even though these are only valid for CPU
1889 * models > 2, however guests may end up dividing or
1890 * multiplying by zero otherwise.
1892 case MSR_EBC_FREQUENCY_ID:
1895 case MSR_IA32_APICBASE:
1896 data = kvm_get_apic_base(vcpu);
1898 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1899 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1901 case MSR_IA32_TSCDEADLINE:
1902 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1904 case MSR_IA32_MISC_ENABLE:
1905 data = vcpu->arch.ia32_misc_enable_msr;
1907 case MSR_IA32_PERF_STATUS:
1908 /* TSC increment by tick */
1910 /* CPU multiplier */
1911 data |= (((uint64_t)4ULL) << 40);
1914 data = vcpu->arch.efer;
1916 case MSR_KVM_WALL_CLOCK:
1917 case MSR_KVM_WALL_CLOCK_NEW:
1918 data = vcpu->kvm->arch.wall_clock;
1920 case MSR_KVM_SYSTEM_TIME:
1921 case MSR_KVM_SYSTEM_TIME_NEW:
1922 data = vcpu->arch.time;
1924 case MSR_KVM_ASYNC_PF_EN:
1925 data = vcpu->arch.apf.msr_val;
1927 case MSR_KVM_STEAL_TIME:
1928 data = vcpu->arch.st.msr_val;
1930 case MSR_IA32_P5_MC_ADDR:
1931 case MSR_IA32_P5_MC_TYPE:
1932 case MSR_IA32_MCG_CAP:
1933 case MSR_IA32_MCG_CTL:
1934 case MSR_IA32_MCG_STATUS:
1935 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1936 return get_msr_mce(vcpu, msr, pdata);
1937 case MSR_K7_CLK_CTL:
1939 * Provide expected ramp-up count for K7. All other
1940 * are set to zero, indicating minimum divisors for
1943 * This prevents guest kernels on AMD host with CPU
1944 * type 6, model 8 and higher from exploding due to
1945 * the rdmsr failing.
1949 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1950 if (kvm_hv_msr_partition_wide(msr)) {
1952 mutex_lock(&vcpu->kvm->lock);
1953 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1954 mutex_unlock(&vcpu->kvm->lock);
1957 return get_msr_hyperv(vcpu, msr, pdata);
1959 case MSR_IA32_BBL_CR_CTL3:
1960 /* This legacy MSR exists but isn't fully documented in current
1961 * silicon. It is however accessed by winxp in very narrow
1962 * scenarios where it sets bit #19, itself documented as
1963 * a "reserved" bit. Best effort attempt to source coherent
1964 * read data here should the balance of the register be
1965 * interpreted by the guest:
1967 * L2 cache control register 3: 64GB range, 256KB size,
1968 * enabled, latency 0x1, configured
1972 case MSR_AMD64_OSVW_ID_LENGTH:
1973 if (!guest_cpuid_has_osvw(vcpu))
1975 data = vcpu->arch.osvw.length;
1977 case MSR_AMD64_OSVW_STATUS:
1978 if (!guest_cpuid_has_osvw(vcpu))
1980 data = vcpu->arch.osvw.status;
1983 if (kvm_pmu_msr(vcpu, msr))
1984 return kvm_pmu_get_msr(vcpu, msr, pdata);
1986 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1989 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1997 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2000 * Read or write a bunch of msrs. All parameters are kernel addresses.
2002 * @return number of msrs set successfully.
2004 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2005 struct kvm_msr_entry *entries,
2006 int (*do_msr)(struct kvm_vcpu *vcpu,
2007 unsigned index, u64 *data))
2011 idx = srcu_read_lock(&vcpu->kvm->srcu);
2012 for (i = 0; i < msrs->nmsrs; ++i)
2013 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2015 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2021 * Read or write a bunch of msrs. Parameters are user addresses.
2023 * @return number of msrs set successfully.
2025 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2026 int (*do_msr)(struct kvm_vcpu *vcpu,
2027 unsigned index, u64 *data),
2030 struct kvm_msrs msrs;
2031 struct kvm_msr_entry *entries;
2036 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2040 if (msrs.nmsrs >= MAX_IO_MSRS)
2043 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2044 entries = memdup_user(user_msrs->entries, size);
2045 if (IS_ERR(entries)) {
2046 r = PTR_ERR(entries);
2050 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2055 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2066 int kvm_dev_ioctl_check_extension(long ext)
2071 case KVM_CAP_IRQCHIP:
2073 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2074 case KVM_CAP_SET_TSS_ADDR:
2075 case KVM_CAP_EXT_CPUID:
2076 case KVM_CAP_CLOCKSOURCE:
2078 case KVM_CAP_NOP_IO_DELAY:
2079 case KVM_CAP_MP_STATE:
2080 case KVM_CAP_SYNC_MMU:
2081 case KVM_CAP_USER_NMI:
2082 case KVM_CAP_REINJECT_CONTROL:
2083 case KVM_CAP_IRQ_INJECT_STATUS:
2084 case KVM_CAP_ASSIGN_DEV_IRQ:
2086 case KVM_CAP_IOEVENTFD:
2088 case KVM_CAP_PIT_STATE2:
2089 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2090 case KVM_CAP_XEN_HVM:
2091 case KVM_CAP_ADJUST_CLOCK:
2092 case KVM_CAP_VCPU_EVENTS:
2093 case KVM_CAP_HYPERV:
2094 case KVM_CAP_HYPERV_VAPIC:
2095 case KVM_CAP_HYPERV_SPIN:
2096 case KVM_CAP_PCI_SEGMENT:
2097 case KVM_CAP_DEBUGREGS:
2098 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2100 case KVM_CAP_ASYNC_PF:
2101 case KVM_CAP_GET_TSC_KHZ:
2104 case KVM_CAP_COALESCED_MMIO:
2105 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2108 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2110 case KVM_CAP_NR_VCPUS:
2111 r = KVM_SOFT_MAX_VCPUS;
2113 case KVM_CAP_MAX_VCPUS:
2116 case KVM_CAP_NR_MEMSLOTS:
2117 r = KVM_MEMORY_SLOTS;
2119 case KVM_CAP_PV_MMU: /* obsolete */
2123 r = iommu_present(&pci_bus_type);
2126 r = KVM_MAX_MCE_BANKS;
2131 case KVM_CAP_TSC_CONTROL:
2132 r = kvm_has_tsc_control;
2134 case KVM_CAP_TSC_DEADLINE_TIMER:
2135 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2145 long kvm_arch_dev_ioctl(struct file *filp,
2146 unsigned int ioctl, unsigned long arg)
2148 void __user *argp = (void __user *)arg;
2152 case KVM_GET_MSR_INDEX_LIST: {
2153 struct kvm_msr_list __user *user_msr_list = argp;
2154 struct kvm_msr_list msr_list;
2158 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2161 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2162 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2165 if (n < msr_list.nmsrs)
2168 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2169 num_msrs_to_save * sizeof(u32)))
2171 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2173 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2178 case KVM_GET_SUPPORTED_CPUID: {
2179 struct kvm_cpuid2 __user *cpuid_arg = argp;
2180 struct kvm_cpuid2 cpuid;
2183 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2185 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2186 cpuid_arg->entries);
2191 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2196 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2199 mce_cap = KVM_MCE_CAP_SUPPORTED;
2201 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2213 static void wbinvd_ipi(void *garbage)
2218 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2220 return vcpu->kvm->arch.iommu_domain &&
2221 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2224 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2226 /* Address WBINVD may be executed by guest */
2227 if (need_emulate_wbinvd(vcpu)) {
2228 if (kvm_x86_ops->has_wbinvd_exit())
2229 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2230 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2231 smp_call_function_single(vcpu->cpu,
2232 wbinvd_ipi, NULL, 1);
2235 kvm_x86_ops->vcpu_load(vcpu, cpu);
2236 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2237 /* Make sure TSC doesn't go backwards */
2241 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2242 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2243 tsc - vcpu->arch.last_guest_tsc;
2246 mark_tsc_unstable("KVM discovered backwards TSC");
2247 if (check_tsc_unstable()) {
2248 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
2249 vcpu->arch.tsc_catchup = 1;
2251 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2252 if (vcpu->cpu != cpu)
2253 kvm_migrate_timers(vcpu);
2257 accumulate_steal_time(vcpu);
2258 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2261 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2263 kvm_x86_ops->vcpu_put(vcpu);
2264 kvm_put_guest_fpu(vcpu);
2265 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
2268 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2269 struct kvm_lapic_state *s)
2271 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2276 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2277 struct kvm_lapic_state *s)
2279 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2280 kvm_apic_post_state_restore(vcpu);
2281 update_cr8_intercept(vcpu);
2286 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2287 struct kvm_interrupt *irq)
2289 if (irq->irq < 0 || irq->irq >= 256)
2291 if (irqchip_in_kernel(vcpu->kvm))
2294 kvm_queue_interrupt(vcpu, irq->irq, false);
2295 kvm_make_request(KVM_REQ_EVENT, vcpu);
2300 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2302 kvm_inject_nmi(vcpu);
2307 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2308 struct kvm_tpr_access_ctl *tac)
2312 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2316 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2320 unsigned bank_num = mcg_cap & 0xff, bank;
2323 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2325 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2328 vcpu->arch.mcg_cap = mcg_cap;
2329 /* Init IA32_MCG_CTL to all 1s */
2330 if (mcg_cap & MCG_CTL_P)
2331 vcpu->arch.mcg_ctl = ~(u64)0;
2332 /* Init IA32_MCi_CTL to all 1s */
2333 for (bank = 0; bank < bank_num; bank++)
2334 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2339 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2340 struct kvm_x86_mce *mce)
2342 u64 mcg_cap = vcpu->arch.mcg_cap;
2343 unsigned bank_num = mcg_cap & 0xff;
2344 u64 *banks = vcpu->arch.mce_banks;
2346 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2349 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2350 * reporting is disabled
2352 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2353 vcpu->arch.mcg_ctl != ~(u64)0)
2355 banks += 4 * mce->bank;
2357 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2358 * reporting is disabled for the bank
2360 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2362 if (mce->status & MCI_STATUS_UC) {
2363 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2364 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2365 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2368 if (banks[1] & MCI_STATUS_VAL)
2369 mce->status |= MCI_STATUS_OVER;
2370 banks[2] = mce->addr;
2371 banks[3] = mce->misc;
2372 vcpu->arch.mcg_status = mce->mcg_status;
2373 banks[1] = mce->status;
2374 kvm_queue_exception(vcpu, MC_VECTOR);
2375 } else if (!(banks[1] & MCI_STATUS_VAL)
2376 || !(banks[1] & MCI_STATUS_UC)) {
2377 if (banks[1] & MCI_STATUS_VAL)
2378 mce->status |= MCI_STATUS_OVER;
2379 banks[2] = mce->addr;
2380 banks[3] = mce->misc;
2381 banks[1] = mce->status;
2383 banks[1] |= MCI_STATUS_OVER;
2387 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2388 struct kvm_vcpu_events *events)
2391 events->exception.injected =
2392 vcpu->arch.exception.pending &&
2393 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2394 events->exception.nr = vcpu->arch.exception.nr;
2395 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2396 events->exception.pad = 0;
2397 events->exception.error_code = vcpu->arch.exception.error_code;
2399 events->interrupt.injected =
2400 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2401 events->interrupt.nr = vcpu->arch.interrupt.nr;
2402 events->interrupt.soft = 0;
2403 events->interrupt.shadow =
2404 kvm_x86_ops->get_interrupt_shadow(vcpu,
2405 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2407 events->nmi.injected = vcpu->arch.nmi_injected;
2408 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2409 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2410 events->nmi.pad = 0;
2412 events->sipi_vector = vcpu->arch.sipi_vector;
2414 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2415 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2416 | KVM_VCPUEVENT_VALID_SHADOW);
2417 memset(&events->reserved, 0, sizeof(events->reserved));
2420 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2421 struct kvm_vcpu_events *events)
2423 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2424 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2425 | KVM_VCPUEVENT_VALID_SHADOW))
2429 vcpu->arch.exception.pending = events->exception.injected;
2430 vcpu->arch.exception.nr = events->exception.nr;
2431 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2432 vcpu->arch.exception.error_code = events->exception.error_code;
2434 vcpu->arch.interrupt.pending = events->interrupt.injected;
2435 vcpu->arch.interrupt.nr = events->interrupt.nr;
2436 vcpu->arch.interrupt.soft = events->interrupt.soft;
2437 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2438 kvm_x86_ops->set_interrupt_shadow(vcpu,
2439 events->interrupt.shadow);
2441 vcpu->arch.nmi_injected = events->nmi.injected;
2442 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2443 vcpu->arch.nmi_pending = events->nmi.pending;
2444 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2446 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2447 vcpu->arch.sipi_vector = events->sipi_vector;
2449 kvm_make_request(KVM_REQ_EVENT, vcpu);
2454 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2455 struct kvm_debugregs *dbgregs)
2457 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2458 dbgregs->dr6 = vcpu->arch.dr6;
2459 dbgregs->dr7 = vcpu->arch.dr7;
2461 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2464 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2465 struct kvm_debugregs *dbgregs)
2470 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2471 vcpu->arch.dr6 = dbgregs->dr6;
2472 vcpu->arch.dr7 = dbgregs->dr7;
2477 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2478 struct kvm_xsave *guest_xsave)
2481 memcpy(guest_xsave->region,
2482 &vcpu->arch.guest_fpu.state->xsave,
2485 memcpy(guest_xsave->region,
2486 &vcpu->arch.guest_fpu.state->fxsave,
2487 sizeof(struct i387_fxsave_struct));
2488 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2493 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2494 struct kvm_xsave *guest_xsave)
2497 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2500 memcpy(&vcpu->arch.guest_fpu.state->xsave,
2501 guest_xsave->region, xstate_size);
2503 if (xstate_bv & ~XSTATE_FPSSE)
2505 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2506 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2511 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2512 struct kvm_xcrs *guest_xcrs)
2514 if (!cpu_has_xsave) {
2515 guest_xcrs->nr_xcrs = 0;
2519 guest_xcrs->nr_xcrs = 1;
2520 guest_xcrs->flags = 0;
2521 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2522 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2525 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2526 struct kvm_xcrs *guest_xcrs)
2533 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2536 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2537 /* Only support XCR0 currently */
2538 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2539 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2540 guest_xcrs->xcrs[0].value);
2548 long kvm_arch_vcpu_ioctl(struct file *filp,
2549 unsigned int ioctl, unsigned long arg)
2551 struct kvm_vcpu *vcpu = filp->private_data;
2552 void __user *argp = (void __user *)arg;
2555 struct kvm_lapic_state *lapic;
2556 struct kvm_xsave *xsave;
2557 struct kvm_xcrs *xcrs;
2563 case KVM_GET_LAPIC: {
2565 if (!vcpu->arch.apic)
2567 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2572 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
2576 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
2581 case KVM_SET_LAPIC: {
2583 if (!vcpu->arch.apic)
2585 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2586 if (IS_ERR(u.lapic)) {
2587 r = PTR_ERR(u.lapic);
2591 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
2597 case KVM_INTERRUPT: {
2598 struct kvm_interrupt irq;
2601 if (copy_from_user(&irq, argp, sizeof irq))
2603 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2610 r = kvm_vcpu_ioctl_nmi(vcpu);
2616 case KVM_SET_CPUID: {
2617 struct kvm_cpuid __user *cpuid_arg = argp;
2618 struct kvm_cpuid cpuid;
2621 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2623 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2628 case KVM_SET_CPUID2: {
2629 struct kvm_cpuid2 __user *cpuid_arg = argp;
2630 struct kvm_cpuid2 cpuid;
2633 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2635 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
2636 cpuid_arg->entries);
2641 case KVM_GET_CPUID2: {
2642 struct kvm_cpuid2 __user *cpuid_arg = argp;
2643 struct kvm_cpuid2 cpuid;
2646 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2648 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
2649 cpuid_arg->entries);
2653 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2659 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2662 r = msr_io(vcpu, argp, do_set_msr, 0);
2664 case KVM_TPR_ACCESS_REPORTING: {
2665 struct kvm_tpr_access_ctl tac;
2668 if (copy_from_user(&tac, argp, sizeof tac))
2670 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2674 if (copy_to_user(argp, &tac, sizeof tac))
2679 case KVM_SET_VAPIC_ADDR: {
2680 struct kvm_vapic_addr va;
2683 if (!irqchip_in_kernel(vcpu->kvm))
2686 if (copy_from_user(&va, argp, sizeof va))
2689 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2692 case KVM_X86_SETUP_MCE: {
2696 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2698 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2701 case KVM_X86_SET_MCE: {
2702 struct kvm_x86_mce mce;
2705 if (copy_from_user(&mce, argp, sizeof mce))
2707 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2710 case KVM_GET_VCPU_EVENTS: {
2711 struct kvm_vcpu_events events;
2713 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2716 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2721 case KVM_SET_VCPU_EVENTS: {
2722 struct kvm_vcpu_events events;
2725 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2728 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2731 case KVM_GET_DEBUGREGS: {
2732 struct kvm_debugregs dbgregs;
2734 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2737 if (copy_to_user(argp, &dbgregs,
2738 sizeof(struct kvm_debugregs)))
2743 case KVM_SET_DEBUGREGS: {
2744 struct kvm_debugregs dbgregs;
2747 if (copy_from_user(&dbgregs, argp,
2748 sizeof(struct kvm_debugregs)))
2751 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2754 case KVM_GET_XSAVE: {
2755 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2760 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2763 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2768 case KVM_SET_XSAVE: {
2769 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2770 if (IS_ERR(u.xsave)) {
2771 r = PTR_ERR(u.xsave);
2775 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2778 case KVM_GET_XCRS: {
2779 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2784 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2787 if (copy_to_user(argp, u.xcrs,
2788 sizeof(struct kvm_xcrs)))
2793 case KVM_SET_XCRS: {
2794 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2795 if (IS_ERR(u.xcrs)) {
2796 r = PTR_ERR(u.xcrs);
2800 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2803 case KVM_SET_TSC_KHZ: {
2807 if (!kvm_has_tsc_control)
2810 user_tsc_khz = (u32)arg;
2812 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2815 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
2820 case KVM_GET_TSC_KHZ: {
2822 if (check_tsc_unstable())
2825 r = vcpu_tsc_khz(vcpu);
2837 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2839 return VM_FAULT_SIGBUS;
2842 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2846 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2848 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2852 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2855 kvm->arch.ept_identity_map_addr = ident_addr;
2859 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2860 u32 kvm_nr_mmu_pages)
2862 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2865 mutex_lock(&kvm->slots_lock);
2866 spin_lock(&kvm->mmu_lock);
2868 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
2869 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
2871 spin_unlock(&kvm->mmu_lock);
2872 mutex_unlock(&kvm->slots_lock);
2876 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2878 return kvm->arch.n_max_mmu_pages;
2881 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2886 switch (chip->chip_id) {
2887 case KVM_IRQCHIP_PIC_MASTER:
2888 memcpy(&chip->chip.pic,
2889 &pic_irqchip(kvm)->pics[0],
2890 sizeof(struct kvm_pic_state));
2892 case KVM_IRQCHIP_PIC_SLAVE:
2893 memcpy(&chip->chip.pic,
2894 &pic_irqchip(kvm)->pics[1],
2895 sizeof(struct kvm_pic_state));
2897 case KVM_IRQCHIP_IOAPIC:
2898 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
2907 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2912 switch (chip->chip_id) {
2913 case KVM_IRQCHIP_PIC_MASTER:
2914 spin_lock(&pic_irqchip(kvm)->lock);
2915 memcpy(&pic_irqchip(kvm)->pics[0],
2917 sizeof(struct kvm_pic_state));
2918 spin_unlock(&pic_irqchip(kvm)->lock);
2920 case KVM_IRQCHIP_PIC_SLAVE:
2921 spin_lock(&pic_irqchip(kvm)->lock);
2922 memcpy(&pic_irqchip(kvm)->pics[1],
2924 sizeof(struct kvm_pic_state));
2925 spin_unlock(&pic_irqchip(kvm)->lock);
2927 case KVM_IRQCHIP_IOAPIC:
2928 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
2934 kvm_pic_update_irq(pic_irqchip(kvm));
2938 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2942 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2943 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2944 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2948 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2952 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2953 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2954 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2955 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2959 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2963 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2964 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2965 sizeof(ps->channels));
2966 ps->flags = kvm->arch.vpit->pit_state.flags;
2967 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2968 memset(&ps->reserved, 0, sizeof(ps->reserved));
2972 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2974 int r = 0, start = 0;
2975 u32 prev_legacy, cur_legacy;
2976 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2977 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2978 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2979 if (!prev_legacy && cur_legacy)
2981 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2982 sizeof(kvm->arch.vpit->pit_state.channels));
2983 kvm->arch.vpit->pit_state.flags = ps->flags;
2984 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
2985 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2989 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2990 struct kvm_reinject_control *control)
2992 if (!kvm->arch.vpit)
2994 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2995 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2996 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3001 * write_protect_slot - write protect a slot for dirty logging
3002 * @kvm: the kvm instance
3003 * @memslot: the slot we protect
3004 * @dirty_bitmap: the bitmap indicating which pages are dirty
3005 * @nr_dirty_pages: the number of dirty pages
3007 * We have two ways to find all sptes to protect:
3008 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3009 * checks ones that have a spte mapping a page in the slot.
3010 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3012 * Generally speaking, if there are not so many dirty pages compared to the
3013 * number of shadow pages, we should use the latter.
3015 * Note that letting others write into a page marked dirty in the old bitmap
3016 * by using the remaining tlb entry is not a problem. That page will become
3017 * write protected again when we flush the tlb and then be reported dirty to
3018 * the user space by copying the old bitmap.
3020 static void write_protect_slot(struct kvm *kvm,
3021 struct kvm_memory_slot *memslot,
3022 unsigned long *dirty_bitmap,
3023 unsigned long nr_dirty_pages)
3025 /* Not many dirty pages compared to # of shadow pages. */
3026 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3027 unsigned long gfn_offset;
3029 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3030 unsigned long gfn = memslot->base_gfn + gfn_offset;
3032 spin_lock(&kvm->mmu_lock);
3033 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3034 spin_unlock(&kvm->mmu_lock);
3036 kvm_flush_remote_tlbs(kvm);
3038 spin_lock(&kvm->mmu_lock);
3039 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3040 spin_unlock(&kvm->mmu_lock);
3045 * Get (and clear) the dirty memory log for a memory slot.
3047 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3048 struct kvm_dirty_log *log)
3051 struct kvm_memory_slot *memslot;
3052 unsigned long n, nr_dirty_pages;
3054 mutex_lock(&kvm->slots_lock);
3057 if (log->slot >= KVM_MEMORY_SLOTS)
3060 memslot = id_to_memslot(kvm->memslots, log->slot);
3062 if (!memslot->dirty_bitmap)
3065 n = kvm_dirty_bitmap_bytes(memslot);
3066 nr_dirty_pages = memslot->nr_dirty_pages;
3068 /* If nothing is dirty, don't bother messing with page tables. */
3069 if (nr_dirty_pages) {
3070 struct kvm_memslots *slots, *old_slots;
3071 unsigned long *dirty_bitmap, *dirty_bitmap_head;
3073 dirty_bitmap = memslot->dirty_bitmap;
3074 dirty_bitmap_head = memslot->dirty_bitmap_head;
3075 if (dirty_bitmap == dirty_bitmap_head)
3076 dirty_bitmap_head += n / sizeof(long);
3077 memset(dirty_bitmap_head, 0, n);
3080 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
3084 memslot = id_to_memslot(slots, log->slot);
3085 memslot->nr_dirty_pages = 0;
3086 memslot->dirty_bitmap = dirty_bitmap_head;
3087 update_memslots(slots, NULL);
3089 old_slots = kvm->memslots;
3090 rcu_assign_pointer(kvm->memslots, slots);
3091 synchronize_srcu_expedited(&kvm->srcu);
3094 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
3097 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
3101 if (clear_user(log->dirty_bitmap, n))
3107 mutex_unlock(&kvm->slots_lock);
3111 long kvm_arch_vm_ioctl(struct file *filp,
3112 unsigned int ioctl, unsigned long arg)
3114 struct kvm *kvm = filp->private_data;
3115 void __user *argp = (void __user *)arg;
3118 * This union makes it completely explicit to gcc-3.x
3119 * that these two variables' stack usage should be
3120 * combined, not added together.
3123 struct kvm_pit_state ps;
3124 struct kvm_pit_state2 ps2;
3125 struct kvm_pit_config pit_config;
3129 case KVM_SET_TSS_ADDR:
3130 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3134 case KVM_SET_IDENTITY_MAP_ADDR: {
3138 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3140 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3145 case KVM_SET_NR_MMU_PAGES:
3146 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3150 case KVM_GET_NR_MMU_PAGES:
3151 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3153 case KVM_CREATE_IRQCHIP: {
3154 struct kvm_pic *vpic;
3156 mutex_lock(&kvm->lock);
3159 goto create_irqchip_unlock;
3161 vpic = kvm_create_pic(kvm);
3163 r = kvm_ioapic_init(kvm);
3165 mutex_lock(&kvm->slots_lock);
3166 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3168 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3170 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3172 mutex_unlock(&kvm->slots_lock);
3174 goto create_irqchip_unlock;
3177 goto create_irqchip_unlock;
3179 kvm->arch.vpic = vpic;
3181 r = kvm_setup_default_irq_routing(kvm);
3183 mutex_lock(&kvm->slots_lock);
3184 mutex_lock(&kvm->irq_lock);
3185 kvm_ioapic_destroy(kvm);
3186 kvm_destroy_pic(kvm);
3187 mutex_unlock(&kvm->irq_lock);
3188 mutex_unlock(&kvm->slots_lock);
3190 create_irqchip_unlock:
3191 mutex_unlock(&kvm->lock);
3194 case KVM_CREATE_PIT:
3195 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3197 case KVM_CREATE_PIT2:
3199 if (copy_from_user(&u.pit_config, argp,
3200 sizeof(struct kvm_pit_config)))
3203 mutex_lock(&kvm->slots_lock);
3206 goto create_pit_unlock;
3208 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3212 mutex_unlock(&kvm->slots_lock);
3214 case KVM_IRQ_LINE_STATUS:
3215 case KVM_IRQ_LINE: {
3216 struct kvm_irq_level irq_event;
3219 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3222 if (irqchip_in_kernel(kvm)) {
3224 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3225 irq_event.irq, irq_event.level);
3226 if (ioctl == KVM_IRQ_LINE_STATUS) {
3228 irq_event.status = status;
3229 if (copy_to_user(argp, &irq_event,
3237 case KVM_GET_IRQCHIP: {
3238 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3239 struct kvm_irqchip *chip;
3241 chip = memdup_user(argp, sizeof(*chip));
3248 if (!irqchip_in_kernel(kvm))
3249 goto get_irqchip_out;
3250 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3252 goto get_irqchip_out;
3254 if (copy_to_user(argp, chip, sizeof *chip))
3255 goto get_irqchip_out;
3263 case KVM_SET_IRQCHIP: {
3264 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3265 struct kvm_irqchip *chip;
3267 chip = memdup_user(argp, sizeof(*chip));
3274 if (!irqchip_in_kernel(kvm))
3275 goto set_irqchip_out;
3276 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3278 goto set_irqchip_out;
3288 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3291 if (!kvm->arch.vpit)
3293 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3297 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3304 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3307 if (!kvm->arch.vpit)
3309 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3315 case KVM_GET_PIT2: {
3317 if (!kvm->arch.vpit)
3319 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3323 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3328 case KVM_SET_PIT2: {
3330 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3333 if (!kvm->arch.vpit)
3335 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3341 case KVM_REINJECT_CONTROL: {
3342 struct kvm_reinject_control control;
3344 if (copy_from_user(&control, argp, sizeof(control)))
3346 r = kvm_vm_ioctl_reinject(kvm, &control);
3352 case KVM_XEN_HVM_CONFIG: {
3354 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3355 sizeof(struct kvm_xen_hvm_config)))
3358 if (kvm->arch.xen_hvm_config.flags)
3363 case KVM_SET_CLOCK: {
3364 struct kvm_clock_data user_ns;
3369 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3377 local_irq_disable();
3378 now_ns = get_kernel_ns();
3379 delta = user_ns.clock - now_ns;
3381 kvm->arch.kvmclock_offset = delta;
3384 case KVM_GET_CLOCK: {
3385 struct kvm_clock_data user_ns;
3388 local_irq_disable();
3389 now_ns = get_kernel_ns();
3390 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3393 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3396 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3409 static void kvm_init_msr_list(void)
3414 /* skip the first msrs in the list. KVM-specific */
3415 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3416 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3419 msrs_to_save[j] = msrs_to_save[i];
3422 num_msrs_to_save = j;
3425 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3433 if (!(vcpu->arch.apic &&
3434 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3435 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3446 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3453 if (!(vcpu->arch.apic &&
3454 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3455 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3457 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3467 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3468 struct kvm_segment *var, int seg)
3470 kvm_x86_ops->set_segment(vcpu, var, seg);
3473 void kvm_get_segment(struct kvm_vcpu *vcpu,
3474 struct kvm_segment *var, int seg)
3476 kvm_x86_ops->get_segment(vcpu, var, seg);
3479 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3482 struct x86_exception exception;
3484 BUG_ON(!mmu_is_nested(vcpu));
3486 /* NPT walks are always user-walks */
3487 access |= PFERR_USER_MASK;
3488 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3493 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3494 struct x86_exception *exception)
3496 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3497 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3500 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3501 struct x86_exception *exception)
3503 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3504 access |= PFERR_FETCH_MASK;
3505 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3508 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3509 struct x86_exception *exception)
3511 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3512 access |= PFERR_WRITE_MASK;
3513 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3516 /* uses this to access any guest's mapped memory without checking CPL */
3517 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3518 struct x86_exception *exception)
3520 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3523 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3524 struct kvm_vcpu *vcpu, u32 access,
3525 struct x86_exception *exception)
3528 int r = X86EMUL_CONTINUE;
3531 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3533 unsigned offset = addr & (PAGE_SIZE-1);
3534 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3537 if (gpa == UNMAPPED_GVA)
3538 return X86EMUL_PROPAGATE_FAULT;
3539 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3541 r = X86EMUL_IO_NEEDED;
3553 /* used for instruction fetching */
3554 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3555 gva_t addr, void *val, unsigned int bytes,
3556 struct x86_exception *exception)
3558 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3559 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3561 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3562 access | PFERR_FETCH_MASK,
3566 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3567 gva_t addr, void *val, unsigned int bytes,
3568 struct x86_exception *exception)
3570 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3571 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3573 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3576 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
3578 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3579 gva_t addr, void *val, unsigned int bytes,
3580 struct x86_exception *exception)
3582 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3583 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
3586 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3587 gva_t addr, void *val,
3589 struct x86_exception *exception)
3591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3593 int r = X86EMUL_CONTINUE;
3596 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3599 unsigned offset = addr & (PAGE_SIZE-1);
3600 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3603 if (gpa == UNMAPPED_GVA)
3604 return X86EMUL_PROPAGATE_FAULT;
3605 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3607 r = X86EMUL_IO_NEEDED;
3618 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
3620 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3621 gpa_t *gpa, struct x86_exception *exception,
3624 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3626 if (vcpu_match_mmio_gva(vcpu, gva) &&
3627 check_write_user_access(vcpu, write, access,
3628 vcpu->arch.access)) {
3629 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3630 (gva & (PAGE_SIZE - 1));
3631 trace_vcpu_match_mmio(gva, *gpa, write, false);
3636 access |= PFERR_WRITE_MASK;
3638 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3640 if (*gpa == UNMAPPED_GVA)
3643 /* For APIC access vmexit */
3644 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3647 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3648 trace_vcpu_match_mmio(gva, *gpa, write, true);
3655 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
3656 const void *val, int bytes)
3660 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
3663 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
3667 struct read_write_emulator_ops {
3668 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3670 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3671 void *val, int bytes);
3672 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3673 int bytes, void *val);
3674 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3675 void *val, int bytes);
3679 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3681 if (vcpu->mmio_read_completed) {
3682 memcpy(val, vcpu->mmio_data, bytes);
3683 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3684 vcpu->mmio_phys_addr, *(u64 *)val);
3685 vcpu->mmio_read_completed = 0;
3692 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3693 void *val, int bytes)
3695 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3698 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3699 void *val, int bytes)
3701 return emulator_write_phys(vcpu, gpa, val, bytes);
3704 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3706 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3707 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3710 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3711 void *val, int bytes)
3713 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3714 return X86EMUL_IO_NEEDED;
3717 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3718 void *val, int bytes)
3720 memcpy(vcpu->mmio_data, val, bytes);
3721 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3722 return X86EMUL_CONTINUE;
3725 static struct read_write_emulator_ops read_emultor = {
3726 .read_write_prepare = read_prepare,
3727 .read_write_emulate = read_emulate,
3728 .read_write_mmio = vcpu_mmio_read,
3729 .read_write_exit_mmio = read_exit_mmio,
3732 static struct read_write_emulator_ops write_emultor = {
3733 .read_write_emulate = write_emulate,
3734 .read_write_mmio = write_mmio,
3735 .read_write_exit_mmio = write_exit_mmio,
3739 static int emulator_read_write_onepage(unsigned long addr, void *val,
3741 struct x86_exception *exception,
3742 struct kvm_vcpu *vcpu,
3743 struct read_write_emulator_ops *ops)
3747 bool write = ops->write;
3749 if (ops->read_write_prepare &&
3750 ops->read_write_prepare(vcpu, val, bytes))
3751 return X86EMUL_CONTINUE;
3753 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
3756 return X86EMUL_PROPAGATE_FAULT;
3758 /* For APIC access vmexit */
3762 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
3763 return X86EMUL_CONTINUE;
3767 * Is this MMIO handled locally?
3769 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
3770 if (handled == bytes)
3771 return X86EMUL_CONTINUE;
3777 vcpu->mmio_needed = 1;
3778 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3779 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3780 vcpu->mmio_size = bytes;
3781 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
3782 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
3783 vcpu->mmio_index = 0;
3785 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
3788 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3789 void *val, unsigned int bytes,
3790 struct x86_exception *exception,
3791 struct read_write_emulator_ops *ops)
3793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3795 /* Crossing a page boundary? */
3796 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3799 now = -addr & ~PAGE_MASK;
3800 rc = emulator_read_write_onepage(addr, val, now, exception,
3803 if (rc != X86EMUL_CONTINUE)
3810 return emulator_read_write_onepage(addr, val, bytes, exception,
3814 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3818 struct x86_exception *exception)
3820 return emulator_read_write(ctxt, addr, val, bytes,
3821 exception, &read_emultor);
3824 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3828 struct x86_exception *exception)
3830 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3831 exception, &write_emultor);
3834 #define CMPXCHG_TYPE(t, ptr, old, new) \
3835 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3837 #ifdef CONFIG_X86_64
3838 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3840 # define CMPXCHG64(ptr, old, new) \
3841 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
3844 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3849 struct x86_exception *exception)
3851 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3857 /* guests cmpxchg8b have to be emulated atomically */
3858 if (bytes > 8 || (bytes & (bytes - 1)))
3861 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
3863 if (gpa == UNMAPPED_GVA ||
3864 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3867 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3870 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3871 if (is_error_page(page)) {
3872 kvm_release_page_clean(page);
3876 kaddr = kmap_atomic(page, KM_USER0);
3877 kaddr += offset_in_page(gpa);
3880 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3883 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3886 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3889 exchanged = CMPXCHG64(kaddr, old, new);
3894 kunmap_atomic(kaddr, KM_USER0);
3895 kvm_release_page_dirty(page);
3898 return X86EMUL_CMPXCHG_FAILED;
3900 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
3902 return X86EMUL_CONTINUE;
3905 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
3907 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
3910 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3912 /* TODO: String I/O for in kernel device */
3915 if (vcpu->arch.pio.in)
3916 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3917 vcpu->arch.pio.size, pd);
3919 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3920 vcpu->arch.pio.port, vcpu->arch.pio.size,
3925 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3926 unsigned short port, void *val,
3927 unsigned int count, bool in)
3929 trace_kvm_pio(!in, port, size, count);
3931 vcpu->arch.pio.port = port;
3932 vcpu->arch.pio.in = in;
3933 vcpu->arch.pio.count = count;
3934 vcpu->arch.pio.size = size;
3936 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3937 vcpu->arch.pio.count = 0;
3941 vcpu->run->exit_reason = KVM_EXIT_IO;
3942 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
3943 vcpu->run->io.size = size;
3944 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3945 vcpu->run->io.count = count;
3946 vcpu->run->io.port = port;
3951 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3952 int size, unsigned short port, void *val,
3955 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3958 if (vcpu->arch.pio.count)
3961 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3964 memcpy(val, vcpu->arch.pio_data, size * count);
3965 vcpu->arch.pio.count = 0;
3972 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3973 int size, unsigned short port,
3974 const void *val, unsigned int count)
3976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3978 memcpy(vcpu->arch.pio_data, val, size * count);
3979 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3982 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3984 return kvm_x86_ops->get_segment_base(vcpu, seg);
3987 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
3989 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
3992 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3994 if (!need_emulate_wbinvd(vcpu))
3995 return X86EMUL_CONTINUE;
3997 if (kvm_x86_ops->has_wbinvd_exit()) {
3998 int cpu = get_cpu();
4000 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4001 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4002 wbinvd_ipi, NULL, 1);
4004 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4007 return X86EMUL_CONTINUE;
4009 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4011 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4013 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4016 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4018 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4021 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4024 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4027 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4029 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4032 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4035 unsigned long value;
4039 value = kvm_read_cr0(vcpu);
4042 value = vcpu->arch.cr2;
4045 value = kvm_read_cr3(vcpu);
4048 value = kvm_read_cr4(vcpu);
4051 value = kvm_get_cr8(vcpu);
4054 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4061 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4063 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4068 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4071 vcpu->arch.cr2 = val;
4074 res = kvm_set_cr3(vcpu, val);
4077 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4080 res = kvm_set_cr8(vcpu, val);
4083 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4090 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4092 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4095 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4097 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4100 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4102 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4105 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4107 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4110 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4112 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4115 static unsigned long emulator_get_cached_segment_base(
4116 struct x86_emulate_ctxt *ctxt, int seg)
4118 return get_segment_base(emul_to_vcpu(ctxt), seg);
4121 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4122 struct desc_struct *desc, u32 *base3,
4125 struct kvm_segment var;
4127 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4128 *selector = var.selector;
4135 set_desc_limit(desc, var.limit);
4136 set_desc_base(desc, (unsigned long)var.base);
4137 #ifdef CONFIG_X86_64
4139 *base3 = var.base >> 32;
4141 desc->type = var.type;
4143 desc->dpl = var.dpl;
4144 desc->p = var.present;
4145 desc->avl = var.avl;
4153 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4154 struct desc_struct *desc, u32 base3,
4157 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4158 struct kvm_segment var;
4160 var.selector = selector;
4161 var.base = get_desc_base(desc);
4162 #ifdef CONFIG_X86_64
4163 var.base |= ((u64)base3) << 32;
4165 var.limit = get_desc_limit(desc);
4167 var.limit = (var.limit << 12) | 0xfff;
4168 var.type = desc->type;
4169 var.present = desc->p;
4170 var.dpl = desc->dpl;
4175 var.avl = desc->avl;
4176 var.present = desc->p;
4177 var.unusable = !var.present;
4180 kvm_set_segment(vcpu, &var, seg);
4184 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4185 u32 msr_index, u64 *pdata)
4187 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4190 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4191 u32 msr_index, u64 data)
4193 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4196 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4197 u32 pmc, u64 *pdata)
4199 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4202 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4204 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4207 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4210 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4212 * CR0.TS may reference the host fpu state, not the guest fpu state,
4213 * so it may be clear at this point.
4218 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4223 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4224 struct x86_instruction_info *info,
4225 enum x86_intercept_stage stage)
4227 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4230 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4231 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4233 struct kvm_cpuid_entry2 *cpuid = NULL;
4236 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4252 static struct x86_emulate_ops emulate_ops = {
4253 .read_std = kvm_read_guest_virt_system,
4254 .write_std = kvm_write_guest_virt_system,
4255 .fetch = kvm_fetch_guest_virt,
4256 .read_emulated = emulator_read_emulated,
4257 .write_emulated = emulator_write_emulated,
4258 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4259 .invlpg = emulator_invlpg,
4260 .pio_in_emulated = emulator_pio_in_emulated,
4261 .pio_out_emulated = emulator_pio_out_emulated,
4262 .get_segment = emulator_get_segment,
4263 .set_segment = emulator_set_segment,
4264 .get_cached_segment_base = emulator_get_cached_segment_base,
4265 .get_gdt = emulator_get_gdt,
4266 .get_idt = emulator_get_idt,
4267 .set_gdt = emulator_set_gdt,
4268 .set_idt = emulator_set_idt,
4269 .get_cr = emulator_get_cr,
4270 .set_cr = emulator_set_cr,
4271 .cpl = emulator_get_cpl,
4272 .get_dr = emulator_get_dr,
4273 .set_dr = emulator_set_dr,
4274 .set_msr = emulator_set_msr,
4275 .get_msr = emulator_get_msr,
4276 .read_pmc = emulator_read_pmc,
4277 .halt = emulator_halt,
4278 .wbinvd = emulator_wbinvd,
4279 .fix_hypercall = emulator_fix_hypercall,
4280 .get_fpu = emulator_get_fpu,
4281 .put_fpu = emulator_put_fpu,
4282 .intercept = emulator_intercept,
4283 .get_cpuid = emulator_get_cpuid,
4286 static void cache_all_regs(struct kvm_vcpu *vcpu)
4288 kvm_register_read(vcpu, VCPU_REGS_RAX);
4289 kvm_register_read(vcpu, VCPU_REGS_RSP);
4290 kvm_register_read(vcpu, VCPU_REGS_RIP);
4291 vcpu->arch.regs_dirty = ~0;
4294 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4296 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4298 * an sti; sti; sequence only disable interrupts for the first
4299 * instruction. So, if the last instruction, be it emulated or
4300 * not, left the system with the INT_STI flag enabled, it
4301 * means that the last instruction is an sti. We should not
4302 * leave the flag on in this case. The same goes for mov ss
4304 if (!(int_shadow & mask))
4305 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4308 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4310 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4311 if (ctxt->exception.vector == PF_VECTOR)
4312 kvm_propagate_fault(vcpu, &ctxt->exception);
4313 else if (ctxt->exception.error_code_valid)
4314 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4315 ctxt->exception.error_code);
4317 kvm_queue_exception(vcpu, ctxt->exception.vector);
4320 static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
4321 const unsigned long *regs)
4323 memset(&ctxt->twobyte, 0,
4324 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4325 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
4327 ctxt->fetch.start = 0;
4328 ctxt->fetch.end = 0;
4329 ctxt->io_read.pos = 0;
4330 ctxt->io_read.end = 0;
4331 ctxt->mem_read.pos = 0;
4332 ctxt->mem_read.end = 0;
4335 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4337 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4341 * TODO: fix emulate.c to use guest_read/write_register
4342 * instead of direct ->regs accesses, can save hundred cycles
4343 * on Intel for instructions that don't read/change RSP, for
4346 cache_all_regs(vcpu);
4348 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4350 ctxt->eflags = kvm_get_rflags(vcpu);
4351 ctxt->eip = kvm_rip_read(vcpu);
4352 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4353 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4354 cs_l ? X86EMUL_MODE_PROT64 :
4355 cs_db ? X86EMUL_MODE_PROT32 :
4356 X86EMUL_MODE_PROT16;
4357 ctxt->guest_mode = is_guest_mode(vcpu);
4359 init_decode_cache(ctxt, vcpu->arch.regs);
4360 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4363 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4365 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4368 init_emulate_ctxt(vcpu);
4372 ctxt->_eip = ctxt->eip + inc_eip;
4373 ret = emulate_int_real(ctxt, irq);
4375 if (ret != X86EMUL_CONTINUE)
4376 return EMULATE_FAIL;
4378 ctxt->eip = ctxt->_eip;
4379 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4380 kvm_rip_write(vcpu, ctxt->eip);
4381 kvm_set_rflags(vcpu, ctxt->eflags);
4383 if (irq == NMI_VECTOR)
4384 vcpu->arch.nmi_pending = 0;
4386 vcpu->arch.interrupt.pending = false;
4388 return EMULATE_DONE;
4390 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4392 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4394 int r = EMULATE_DONE;
4396 ++vcpu->stat.insn_emulation_fail;
4397 trace_kvm_emulate_insn_failed(vcpu);
4398 if (!is_guest_mode(vcpu)) {
4399 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4400 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4401 vcpu->run->internal.ndata = 0;
4404 kvm_queue_exception(vcpu, UD_VECTOR);
4409 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4417 * if emulation was due to access to shadowed page table
4418 * and it failed try to unshadow page and re-entetr the
4419 * guest to let CPU execute the instruction.
4421 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4424 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4426 if (gpa == UNMAPPED_GVA)
4427 return true; /* let cpu generate fault */
4429 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4435 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4436 unsigned long cr2, int emulation_type)
4438 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4439 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4441 last_retry_eip = vcpu->arch.last_retry_eip;
4442 last_retry_addr = vcpu->arch.last_retry_addr;
4445 * If the emulation is caused by #PF and it is non-page_table
4446 * writing instruction, it means the VM-EXIT is caused by shadow
4447 * page protected, we can zap the shadow page and retry this
4448 * instruction directly.
4450 * Note: if the guest uses a non-page-table modifying instruction
4451 * on the PDE that points to the instruction, then we will unmap
4452 * the instruction and go to an infinite loop. So, we cache the
4453 * last retried eip and the last fault address, if we meet the eip
4454 * and the address again, we can break out of the potential infinite
4457 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4459 if (!(emulation_type & EMULTYPE_RETRY))
4462 if (x86_page_table_writing_insn(ctxt))
4465 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4468 vcpu->arch.last_retry_eip = ctxt->eip;
4469 vcpu->arch.last_retry_addr = cr2;
4471 if (!vcpu->arch.mmu.direct_map)
4472 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4474 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4479 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4486 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4487 bool writeback = true;
4489 kvm_clear_exception_queue(vcpu);
4491 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4492 init_emulate_ctxt(vcpu);
4493 ctxt->interruptibility = 0;
4494 ctxt->have_exception = false;
4495 ctxt->perm_ok = false;
4497 ctxt->only_vendor_specific_insn
4498 = emulation_type & EMULTYPE_TRAP_UD;
4500 r = x86_decode_insn(ctxt, insn, insn_len);
4502 trace_kvm_emulate_insn_start(vcpu);
4503 ++vcpu->stat.insn_emulation;
4504 if (r != EMULATION_OK) {
4505 if (emulation_type & EMULTYPE_TRAP_UD)
4506 return EMULATE_FAIL;
4507 if (reexecute_instruction(vcpu, cr2))
4508 return EMULATE_DONE;
4509 if (emulation_type & EMULTYPE_SKIP)
4510 return EMULATE_FAIL;
4511 return handle_emulation_failure(vcpu);
4515 if (emulation_type & EMULTYPE_SKIP) {
4516 kvm_rip_write(vcpu, ctxt->_eip);
4517 return EMULATE_DONE;
4520 if (retry_instruction(ctxt, cr2, emulation_type))
4521 return EMULATE_DONE;
4523 /* this is needed for vmware backdoor interface to work since it
4524 changes registers values during IO operation */
4525 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4526 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4527 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
4531 r = x86_emulate_insn(ctxt);
4533 if (r == EMULATION_INTERCEPTED)
4534 return EMULATE_DONE;
4536 if (r == EMULATION_FAILED) {
4537 if (reexecute_instruction(vcpu, cr2))
4538 return EMULATE_DONE;
4540 return handle_emulation_failure(vcpu);
4543 if (ctxt->have_exception) {
4544 inject_emulated_exception(vcpu);
4546 } else if (vcpu->arch.pio.count) {
4547 if (!vcpu->arch.pio.in)
4548 vcpu->arch.pio.count = 0;
4551 r = EMULATE_DO_MMIO;
4552 } else if (vcpu->mmio_needed) {
4553 if (!vcpu->mmio_is_write)
4555 r = EMULATE_DO_MMIO;
4556 } else if (r == EMULATION_RESTART)
4562 toggle_interruptibility(vcpu, ctxt->interruptibility);
4563 kvm_set_rflags(vcpu, ctxt->eflags);
4564 kvm_make_request(KVM_REQ_EVENT, vcpu);
4565 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
4566 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4567 kvm_rip_write(vcpu, ctxt->eip);
4569 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
4573 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
4575 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
4577 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4578 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4579 size, port, &val, 1);
4580 /* do not return to emulator after return from userspace */
4581 vcpu->arch.pio.count = 0;
4584 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
4586 static void tsc_bad(void *info)
4588 __this_cpu_write(cpu_tsc_khz, 0);
4591 static void tsc_khz_changed(void *data)
4593 struct cpufreq_freqs *freq = data;
4594 unsigned long khz = 0;
4598 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4599 khz = cpufreq_quick_get(raw_smp_processor_id());
4602 __this_cpu_write(cpu_tsc_khz, khz);
4605 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4608 struct cpufreq_freqs *freq = data;
4610 struct kvm_vcpu *vcpu;
4611 int i, send_ipi = 0;
4614 * We allow guests to temporarily run on slowing clocks,
4615 * provided we notify them after, or to run on accelerating
4616 * clocks, provided we notify them before. Thus time never
4619 * However, we have a problem. We can't atomically update
4620 * the frequency of a given CPU from this function; it is
4621 * merely a notifier, which can be called from any CPU.
4622 * Changing the TSC frequency at arbitrary points in time
4623 * requires a recomputation of local variables related to
4624 * the TSC for each VCPU. We must flag these local variables
4625 * to be updated and be sure the update takes place with the
4626 * new frequency before any guests proceed.
4628 * Unfortunately, the combination of hotplug CPU and frequency
4629 * change creates an intractable locking scenario; the order
4630 * of when these callouts happen is undefined with respect to
4631 * CPU hotplug, and they can race with each other. As such,
4632 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4633 * undefined; you can actually have a CPU frequency change take
4634 * place in between the computation of X and the setting of the
4635 * variable. To protect against this problem, all updates of
4636 * the per_cpu tsc_khz variable are done in an interrupt
4637 * protected IPI, and all callers wishing to update the value
4638 * must wait for a synchronous IPI to complete (which is trivial
4639 * if the caller is on the CPU already). This establishes the
4640 * necessary total order on variable updates.
4642 * Note that because a guest time update may take place
4643 * anytime after the setting of the VCPU's request bit, the
4644 * correct TSC value must be set before the request. However,
4645 * to ensure the update actually makes it to any guest which
4646 * starts running in hardware virtualization between the set
4647 * and the acquisition of the spinlock, we must also ping the
4648 * CPU after setting the request bit.
4652 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4654 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4657 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4659 raw_spin_lock(&kvm_lock);
4660 list_for_each_entry(kvm, &vm_list, vm_list) {
4661 kvm_for_each_vcpu(i, vcpu, kvm) {
4662 if (vcpu->cpu != freq->cpu)
4664 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4665 if (vcpu->cpu != smp_processor_id())
4669 raw_spin_unlock(&kvm_lock);
4671 if (freq->old < freq->new && send_ipi) {
4673 * We upscale the frequency. Must make the guest
4674 * doesn't see old kvmclock values while running with
4675 * the new frequency, otherwise we risk the guest sees
4676 * time go backwards.
4678 * In case we update the frequency for another cpu
4679 * (which might be in guest context) send an interrupt
4680 * to kick the cpu out of guest context. Next time
4681 * guest context is entered kvmclock will be updated,
4682 * so the guest will not see stale values.
4684 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
4689 static struct notifier_block kvmclock_cpufreq_notifier_block = {
4690 .notifier_call = kvmclock_cpufreq_notifier
4693 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4694 unsigned long action, void *hcpu)
4696 unsigned int cpu = (unsigned long)hcpu;
4700 case CPU_DOWN_FAILED:
4701 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4703 case CPU_DOWN_PREPARE:
4704 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4710 static struct notifier_block kvmclock_cpu_notifier_block = {
4711 .notifier_call = kvmclock_cpu_notifier,
4712 .priority = -INT_MAX
4715 static void kvm_timer_init(void)
4719 max_tsc_khz = tsc_khz;
4720 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4721 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
4722 #ifdef CONFIG_CPU_FREQ
4723 struct cpufreq_policy policy;
4724 memset(&policy, 0, sizeof(policy));
4726 cpufreq_get_policy(&policy, cpu);
4727 if (policy.cpuinfo.max_freq)
4728 max_tsc_khz = policy.cpuinfo.max_freq;
4731 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4732 CPUFREQ_TRANSITION_NOTIFIER);
4734 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
4735 for_each_online_cpu(cpu)
4736 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4739 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4741 int kvm_is_in_guest(void)
4743 return __this_cpu_read(current_vcpu) != NULL;
4746 static int kvm_is_user_mode(void)
4750 if (__this_cpu_read(current_vcpu))
4751 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
4753 return user_mode != 0;
4756 static unsigned long kvm_get_guest_ip(void)
4758 unsigned long ip = 0;
4760 if (__this_cpu_read(current_vcpu))
4761 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
4766 static struct perf_guest_info_callbacks kvm_guest_cbs = {
4767 .is_in_guest = kvm_is_in_guest,
4768 .is_user_mode = kvm_is_user_mode,
4769 .get_guest_ip = kvm_get_guest_ip,
4772 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4774 __this_cpu_write(current_vcpu, vcpu);
4776 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4778 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4780 __this_cpu_write(current_vcpu, NULL);
4782 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4784 static void kvm_set_mmio_spte_mask(void)
4787 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4790 * Set the reserved bits and the present bit of an paging-structure
4791 * entry to generate page fault with PFER.RSV = 1.
4793 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4796 #ifdef CONFIG_X86_64
4798 * If reserved bit is not supported, clear the present bit to disable
4801 if (maxphyaddr == 52)
4805 kvm_mmu_set_mmio_spte_mask(mask);
4808 int kvm_arch_init(void *opaque)
4811 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4814 printk(KERN_ERR "kvm: already loaded the other module\n");
4819 if (!ops->cpu_has_kvm_support()) {
4820 printk(KERN_ERR "kvm: no hardware support\n");
4824 if (ops->disabled_by_bios()) {
4825 printk(KERN_ERR "kvm: disabled by bios\n");
4830 r = kvm_mmu_module_init();
4834 kvm_set_mmio_spte_mask();
4835 kvm_init_msr_list();
4838 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4839 PT_DIRTY_MASK, PT64_NX_MASK, 0);
4843 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4846 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4854 void kvm_arch_exit(void)
4856 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4858 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4859 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4860 CPUFREQ_TRANSITION_NOTIFIER);
4861 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
4863 kvm_mmu_module_exit();
4866 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4868 ++vcpu->stat.halt_exits;
4869 if (irqchip_in_kernel(vcpu->kvm)) {
4870 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
4873 vcpu->run->exit_reason = KVM_EXIT_HLT;
4877 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4879 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4881 u64 param, ingpa, outgpa, ret;
4882 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4883 bool fast, longmode;
4887 * hypercall generates UD from non zero cpl and real mode
4890 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
4891 kvm_queue_exception(vcpu, UD_VECTOR);
4895 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4896 longmode = is_long_mode(vcpu) && cs_l == 1;
4899 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4900 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4901 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4902 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4903 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4904 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
4906 #ifdef CONFIG_X86_64
4908 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4909 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4910 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4914 code = param & 0xffff;
4915 fast = (param >> 16) & 0x1;
4916 rep_cnt = (param >> 32) & 0xfff;
4917 rep_idx = (param >> 48) & 0xfff;
4919 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4922 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4923 kvm_vcpu_on_spin(vcpu);
4926 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4930 ret = res | (((u64)rep_done & 0xfff) << 32);
4932 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4934 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4935 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4941 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4943 unsigned long nr, a0, a1, a2, a3, ret;
4946 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4947 return kvm_hv_hypercall(vcpu);
4949 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4950 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4951 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4952 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4953 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
4955 trace_kvm_hypercall(nr, a0, a1, a2, a3);
4957 if (!is_long_mode(vcpu)) {
4965 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4971 case KVM_HC_VAPIC_POLL_IRQ:
4979 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4980 ++vcpu->stat.hypercalls;
4983 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4985 int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
4987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4988 char instruction[3];
4989 unsigned long rip = kvm_rip_read(vcpu);
4992 * Blow out the MMU to ensure that no other VCPU has an active mapping
4993 * to ensure that the updated hypercall appears atomically across all
4996 kvm_mmu_zap_all(vcpu->kvm);
4998 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5000 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5004 * Check if userspace requested an interrupt window, and that the
5005 * interrupt window is open.
5007 * No need to exit to userspace if we already have an interrupt queued.
5009 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5011 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5012 vcpu->run->request_interrupt_window &&
5013 kvm_arch_interrupt_allowed(vcpu));
5016 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5018 struct kvm_run *kvm_run = vcpu->run;
5020 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5021 kvm_run->cr8 = kvm_get_cr8(vcpu);
5022 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5023 if (irqchip_in_kernel(vcpu->kvm))
5024 kvm_run->ready_for_interrupt_injection = 1;
5026 kvm_run->ready_for_interrupt_injection =
5027 kvm_arch_interrupt_allowed(vcpu) &&
5028 !kvm_cpu_has_interrupt(vcpu) &&
5029 !kvm_event_needs_reinjection(vcpu);
5032 static void vapic_enter(struct kvm_vcpu *vcpu)
5034 struct kvm_lapic *apic = vcpu->arch.apic;
5037 if (!apic || !apic->vapic_addr)
5040 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5042 vcpu->arch.apic->vapic_page = page;
5045 static void vapic_exit(struct kvm_vcpu *vcpu)
5047 struct kvm_lapic *apic = vcpu->arch.apic;
5050 if (!apic || !apic->vapic_addr)
5053 idx = srcu_read_lock(&vcpu->kvm->srcu);
5054 kvm_release_page_dirty(apic->vapic_page);
5055 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
5056 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5059 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5063 if (!kvm_x86_ops->update_cr8_intercept)
5066 if (!vcpu->arch.apic)
5069 if (!vcpu->arch.apic->vapic_addr)
5070 max_irr = kvm_lapic_find_highest_irr(vcpu);
5077 tpr = kvm_lapic_get_cr8(vcpu);
5079 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5082 static void inject_pending_event(struct kvm_vcpu *vcpu)
5084 /* try to reinject previous events if any */
5085 if (vcpu->arch.exception.pending) {
5086 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5087 vcpu->arch.exception.has_error_code,
5088 vcpu->arch.exception.error_code);
5089 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5090 vcpu->arch.exception.has_error_code,
5091 vcpu->arch.exception.error_code,
5092 vcpu->arch.exception.reinject);
5096 if (vcpu->arch.nmi_injected) {
5097 kvm_x86_ops->set_nmi(vcpu);
5101 if (vcpu->arch.interrupt.pending) {
5102 kvm_x86_ops->set_irq(vcpu);
5106 /* try to inject new event if pending */
5107 if (vcpu->arch.nmi_pending) {
5108 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5109 --vcpu->arch.nmi_pending;
5110 vcpu->arch.nmi_injected = true;
5111 kvm_x86_ops->set_nmi(vcpu);
5113 } else if (kvm_cpu_has_interrupt(vcpu)) {
5114 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5115 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5117 kvm_x86_ops->set_irq(vcpu);
5122 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5124 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5125 !vcpu->guest_xcr0_loaded) {
5126 /* kvm_set_xcr() also depends on this */
5127 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5128 vcpu->guest_xcr0_loaded = 1;
5132 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5134 if (vcpu->guest_xcr0_loaded) {
5135 if (vcpu->arch.xcr0 != host_xcr0)
5136 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5137 vcpu->guest_xcr0_loaded = 0;
5141 static void process_nmi(struct kvm_vcpu *vcpu)
5146 * x86 is limited to one NMI running, and one NMI pending after it.
5147 * If an NMI is already in progress, limit further NMIs to just one.
5148 * Otherwise, allow two (and we'll inject the first one immediately).
5150 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5153 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5154 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5155 kvm_make_request(KVM_REQ_EVENT, vcpu);
5158 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5161 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5162 vcpu->run->request_interrupt_window;
5163 bool req_immediate_exit = 0;
5165 if (vcpu->requests) {
5166 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5167 kvm_mmu_unload(vcpu);
5168 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5169 __kvm_migrate_timers(vcpu);
5170 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5171 r = kvm_guest_time_update(vcpu);
5175 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5176 kvm_mmu_sync_roots(vcpu);
5177 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5178 kvm_x86_ops->tlb_flush(vcpu);
5179 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5180 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5184 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5185 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5189 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5190 vcpu->fpu_active = 0;
5191 kvm_x86_ops->fpu_deactivate(vcpu);
5193 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5194 /* Page is swapped out. Do synthetic halt */
5195 vcpu->arch.apf.halted = true;
5199 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5200 record_steal_time(vcpu);
5201 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5203 req_immediate_exit =
5204 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
5205 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5206 kvm_handle_pmu_event(vcpu);
5207 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5208 kvm_deliver_pmi(vcpu);
5211 r = kvm_mmu_reload(vcpu);
5215 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5216 inject_pending_event(vcpu);
5218 /* enable NMI/IRQ window open exits if needed */
5219 if (vcpu->arch.nmi_pending)
5220 kvm_x86_ops->enable_nmi_window(vcpu);
5221 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5222 kvm_x86_ops->enable_irq_window(vcpu);
5224 if (kvm_lapic_enabled(vcpu)) {
5225 update_cr8_intercept(vcpu);
5226 kvm_lapic_sync_to_vapic(vcpu);
5232 kvm_x86_ops->prepare_guest_switch(vcpu);
5233 if (vcpu->fpu_active)
5234 kvm_load_guest_fpu(vcpu);
5235 kvm_load_guest_xcr0(vcpu);
5237 vcpu->mode = IN_GUEST_MODE;
5239 /* We should set ->mode before check ->requests,
5240 * see the comment in make_all_cpus_request.
5244 local_irq_disable();
5246 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5247 || need_resched() || signal_pending(current)) {
5248 vcpu->mode = OUTSIDE_GUEST_MODE;
5252 kvm_x86_ops->cancel_injection(vcpu);
5257 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5259 if (req_immediate_exit)
5260 smp_send_reschedule(vcpu->cpu);
5264 if (unlikely(vcpu->arch.switch_db_regs)) {
5266 set_debugreg(vcpu->arch.eff_db[0], 0);
5267 set_debugreg(vcpu->arch.eff_db[1], 1);
5268 set_debugreg(vcpu->arch.eff_db[2], 2);
5269 set_debugreg(vcpu->arch.eff_db[3], 3);
5272 trace_kvm_entry(vcpu->vcpu_id);
5273 kvm_x86_ops->run(vcpu);
5276 * If the guest has used debug registers, at least dr7
5277 * will be disabled while returning to the host.
5278 * If we don't have active breakpoints in the host, we don't
5279 * care about the messed up debug address registers. But if
5280 * we have some of them active, restore the old state.
5282 if (hw_breakpoint_active())
5283 hw_breakpoint_restore();
5285 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
5287 vcpu->mode = OUTSIDE_GUEST_MODE;
5294 * We must have an instruction between local_irq_enable() and
5295 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5296 * the interrupt shadow. The stat.exits increment will do nicely.
5297 * But we need to prevent reordering, hence this barrier():
5305 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5308 * Profile KVM exit RIPs:
5310 if (unlikely(prof_on == KVM_PROFILING)) {
5311 unsigned long rip = kvm_rip_read(vcpu);
5312 profile_hit(KVM_PROFILING, (void *)rip);
5316 kvm_lapic_sync_from_vapic(vcpu);
5318 r = kvm_x86_ops->handle_exit(vcpu);
5324 static int __vcpu_run(struct kvm_vcpu *vcpu)
5327 struct kvm *kvm = vcpu->kvm;
5329 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
5330 pr_debug("vcpu %d received sipi with vector # %x\n",
5331 vcpu->vcpu_id, vcpu->arch.sipi_vector);
5332 kvm_lapic_reset(vcpu);
5333 r = kvm_arch_vcpu_reset(vcpu);
5336 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5339 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5344 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5345 !vcpu->arch.apf.halted)
5346 r = vcpu_enter_guest(vcpu);
5348 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5349 kvm_vcpu_block(vcpu);
5350 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5351 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
5353 switch(vcpu->arch.mp_state) {
5354 case KVM_MP_STATE_HALTED:
5355 vcpu->arch.mp_state =
5356 KVM_MP_STATE_RUNNABLE;
5357 case KVM_MP_STATE_RUNNABLE:
5358 vcpu->arch.apf.halted = false;
5360 case KVM_MP_STATE_SIPI_RECEIVED:
5371 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5372 if (kvm_cpu_has_pending_timer(vcpu))
5373 kvm_inject_pending_timer_irqs(vcpu);
5375 if (dm_request_for_irq_injection(vcpu)) {
5377 vcpu->run->exit_reason = KVM_EXIT_INTR;
5378 ++vcpu->stat.request_irq_exits;
5381 kvm_check_async_pf_completion(vcpu);
5383 if (signal_pending(current)) {
5385 vcpu->run->exit_reason = KVM_EXIT_INTR;
5386 ++vcpu->stat.signal_exits;
5388 if (need_resched()) {
5389 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5391 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5395 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5402 static int complete_mmio(struct kvm_vcpu *vcpu)
5404 struct kvm_run *run = vcpu->run;
5407 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5410 if (vcpu->mmio_needed) {
5411 vcpu->mmio_needed = 0;
5412 if (!vcpu->mmio_is_write)
5413 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5415 vcpu->mmio_index += 8;
5416 if (vcpu->mmio_index < vcpu->mmio_size) {
5417 run->exit_reason = KVM_EXIT_MMIO;
5418 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5419 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5420 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5421 run->mmio.is_write = vcpu->mmio_is_write;
5422 vcpu->mmio_needed = 1;
5425 if (vcpu->mmio_is_write)
5427 vcpu->mmio_read_completed = 1;
5429 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5430 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5431 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5432 if (r != EMULATE_DONE)
5437 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5442 if (!tsk_used_math(current) && init_fpu(current))
5445 if (vcpu->sigset_active)
5446 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5448 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
5449 kvm_vcpu_block(vcpu);
5450 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
5455 /* re-sync apic's tpr */
5456 if (!irqchip_in_kernel(vcpu->kvm)) {
5457 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5463 r = complete_mmio(vcpu);
5467 r = __vcpu_run(vcpu);
5470 post_kvm_run_save(vcpu);
5471 if (vcpu->sigset_active)
5472 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5477 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5479 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5481 * We are here if userspace calls get_regs() in the middle of
5482 * instruction emulation. Registers state needs to be copied
5483 * back from emulation context to vcpu. Usrapace shouldn't do
5484 * that usually, but some bad designed PV devices (vmware
5485 * backdoor interface) need this to work
5487 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5488 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5489 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5491 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5492 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5493 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5494 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5495 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5496 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5497 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5498 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5499 #ifdef CONFIG_X86_64
5500 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5501 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5502 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5503 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5504 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5505 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5506 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5507 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
5510 regs->rip = kvm_rip_read(vcpu);
5511 regs->rflags = kvm_get_rflags(vcpu);
5516 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5518 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5519 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5521 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5522 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5523 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5524 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5525 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5526 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5527 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5528 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
5529 #ifdef CONFIG_X86_64
5530 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5531 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5532 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5533 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5534 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5535 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5536 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5537 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
5540 kvm_rip_write(vcpu, regs->rip);
5541 kvm_set_rflags(vcpu, regs->rflags);
5543 vcpu->arch.exception.pending = false;
5545 kvm_make_request(KVM_REQ_EVENT, vcpu);
5550 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5552 struct kvm_segment cs;
5554 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
5558 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5560 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5561 struct kvm_sregs *sregs)
5565 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5566 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5567 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5568 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5569 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5570 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5572 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5573 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5575 kvm_x86_ops->get_idt(vcpu, &dt);
5576 sregs->idt.limit = dt.size;
5577 sregs->idt.base = dt.address;
5578 kvm_x86_ops->get_gdt(vcpu, &dt);
5579 sregs->gdt.limit = dt.size;
5580 sregs->gdt.base = dt.address;
5582 sregs->cr0 = kvm_read_cr0(vcpu);
5583 sregs->cr2 = vcpu->arch.cr2;
5584 sregs->cr3 = kvm_read_cr3(vcpu);
5585 sregs->cr4 = kvm_read_cr4(vcpu);
5586 sregs->cr8 = kvm_get_cr8(vcpu);
5587 sregs->efer = vcpu->arch.efer;
5588 sregs->apic_base = kvm_get_apic_base(vcpu);
5590 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
5592 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
5593 set_bit(vcpu->arch.interrupt.nr,
5594 (unsigned long *)sregs->interrupt_bitmap);
5599 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5600 struct kvm_mp_state *mp_state)
5602 mp_state->mp_state = vcpu->arch.mp_state;
5606 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5607 struct kvm_mp_state *mp_state)
5609 vcpu->arch.mp_state = mp_state->mp_state;
5610 kvm_make_request(KVM_REQ_EVENT, vcpu);
5614 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5615 bool has_error_code, u32 error_code)
5617 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5620 init_emulate_ctxt(vcpu);
5622 ret = emulator_task_switch(ctxt, tss_selector, reason,
5623 has_error_code, error_code);
5626 return EMULATE_FAIL;
5628 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
5629 kvm_rip_write(vcpu, ctxt->eip);
5630 kvm_set_rflags(vcpu, ctxt->eflags);
5631 kvm_make_request(KVM_REQ_EVENT, vcpu);
5632 return EMULATE_DONE;
5634 EXPORT_SYMBOL_GPL(kvm_task_switch);
5636 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5637 struct kvm_sregs *sregs)
5639 int mmu_reset_needed = 0;
5640 int pending_vec, max_bits, idx;
5643 dt.size = sregs->idt.limit;
5644 dt.address = sregs->idt.base;
5645 kvm_x86_ops->set_idt(vcpu, &dt);
5646 dt.size = sregs->gdt.limit;
5647 dt.address = sregs->gdt.base;
5648 kvm_x86_ops->set_gdt(vcpu, &dt);
5650 vcpu->arch.cr2 = sregs->cr2;
5651 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
5652 vcpu->arch.cr3 = sregs->cr3;
5653 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
5655 kvm_set_cr8(vcpu, sregs->cr8);
5657 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
5658 kvm_x86_ops->set_efer(vcpu, sregs->efer);
5659 kvm_set_apic_base(vcpu, sregs->apic_base);
5661 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
5662 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
5663 vcpu->arch.cr0 = sregs->cr0;
5665 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
5666 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
5667 if (sregs->cr4 & X86_CR4_OSXSAVE)
5668 kvm_update_cpuid(vcpu);
5670 idx = srcu_read_lock(&vcpu->kvm->srcu);
5671 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
5672 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
5673 mmu_reset_needed = 1;
5675 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5677 if (mmu_reset_needed)
5678 kvm_mmu_reset_context(vcpu);
5680 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5681 pending_vec = find_first_bit(
5682 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5683 if (pending_vec < max_bits) {
5684 kvm_queue_interrupt(vcpu, pending_vec, false);
5685 pr_debug("Set back pending irq %d\n", pending_vec);
5688 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5689 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5690 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5691 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5692 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5693 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
5695 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5696 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
5698 update_cr8_intercept(vcpu);
5700 /* Older userspace won't unhalt the vcpu on reset. */
5701 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
5702 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
5704 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5706 kvm_make_request(KVM_REQ_EVENT, vcpu);
5711 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5712 struct kvm_guest_debug *dbg)
5714 unsigned long rflags;
5717 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5719 if (vcpu->arch.exception.pending)
5721 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5722 kvm_queue_exception(vcpu, DB_VECTOR);
5724 kvm_queue_exception(vcpu, BP_VECTOR);
5728 * Read rflags as long as potentially injected trace flags are still
5731 rflags = kvm_get_rflags(vcpu);
5733 vcpu->guest_debug = dbg->control;
5734 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5735 vcpu->guest_debug = 0;
5737 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5738 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5739 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5740 vcpu->arch.switch_db_regs =
5741 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5743 for (i = 0; i < KVM_NR_DB_REGS; i++)
5744 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5745 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5748 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5749 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5750 get_segment_base(vcpu, VCPU_SREG_CS);
5753 * Trigger an rflags update that will inject or remove the trace
5756 kvm_set_rflags(vcpu, rflags);
5758 kvm_x86_ops->set_guest_debug(vcpu, dbg);
5768 * Translate a guest virtual address to a guest physical address.
5770 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5771 struct kvm_translation *tr)
5773 unsigned long vaddr = tr->linear_address;
5777 idx = srcu_read_lock(&vcpu->kvm->srcu);
5778 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
5779 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5780 tr->physical_address = gpa;
5781 tr->valid = gpa != UNMAPPED_GVA;
5788 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5790 struct i387_fxsave_struct *fxsave =
5791 &vcpu->arch.guest_fpu.state->fxsave;
5793 memcpy(fpu->fpr, fxsave->st_space, 128);
5794 fpu->fcw = fxsave->cwd;
5795 fpu->fsw = fxsave->swd;
5796 fpu->ftwx = fxsave->twd;
5797 fpu->last_opcode = fxsave->fop;
5798 fpu->last_ip = fxsave->rip;
5799 fpu->last_dp = fxsave->rdp;
5800 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5805 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5807 struct i387_fxsave_struct *fxsave =
5808 &vcpu->arch.guest_fpu.state->fxsave;
5810 memcpy(fxsave->st_space, fpu->fpr, 128);
5811 fxsave->cwd = fpu->fcw;
5812 fxsave->swd = fpu->fsw;
5813 fxsave->twd = fpu->ftwx;
5814 fxsave->fop = fpu->last_opcode;
5815 fxsave->rip = fpu->last_ip;
5816 fxsave->rdp = fpu->last_dp;
5817 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5822 int fx_init(struct kvm_vcpu *vcpu)
5826 err = fpu_alloc(&vcpu->arch.guest_fpu);
5830 fpu_finit(&vcpu->arch.guest_fpu);
5833 * Ensure guest xcr0 is valid for loading
5835 vcpu->arch.xcr0 = XSTATE_FP;
5837 vcpu->arch.cr0 |= X86_CR0_ET;
5841 EXPORT_SYMBOL_GPL(fx_init);
5843 static void fx_free(struct kvm_vcpu *vcpu)
5845 fpu_free(&vcpu->arch.guest_fpu);
5848 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5850 if (vcpu->guest_fpu_loaded)
5854 * Restore all possible states in the guest,
5855 * and assume host would use all available bits.
5856 * Guest xcr0 would be loaded later.
5858 kvm_put_guest_xcr0(vcpu);
5859 vcpu->guest_fpu_loaded = 1;
5860 unlazy_fpu(current);
5861 fpu_restore_checking(&vcpu->arch.guest_fpu);
5865 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5867 kvm_put_guest_xcr0(vcpu);
5869 if (!vcpu->guest_fpu_loaded)
5872 vcpu->guest_fpu_loaded = 0;
5873 fpu_save_init(&vcpu->arch.guest_fpu);
5874 ++vcpu->stat.fpu_reload;
5875 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
5879 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5881 kvmclock_reset(vcpu);
5883 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
5885 kvm_x86_ops->vcpu_free(vcpu);
5888 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5891 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5892 printk_once(KERN_WARNING
5893 "kvm: SMP vm created on host with unstable TSC; "
5894 "guest TSC will not be reliable\n");
5895 return kvm_x86_ops->vcpu_create(kvm, id);
5898 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5902 vcpu->arch.mtrr_state.have_fixed = 1;
5904 r = kvm_arch_vcpu_reset(vcpu);
5906 r = kvm_mmu_setup(vcpu);
5912 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
5914 vcpu->arch.apf.msr_val = 0;
5917 kvm_mmu_unload(vcpu);
5921 kvm_x86_ops->vcpu_free(vcpu);
5924 int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5926 atomic_set(&vcpu->arch.nmi_queued, 0);
5927 vcpu->arch.nmi_pending = 0;
5928 vcpu->arch.nmi_injected = false;
5930 vcpu->arch.switch_db_regs = 0;
5931 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5932 vcpu->arch.dr6 = DR6_FIXED_1;
5933 vcpu->arch.dr7 = DR7_FIXED_1;
5935 kvm_make_request(KVM_REQ_EVENT, vcpu);
5936 vcpu->arch.apf.msr_val = 0;
5937 vcpu->arch.st.msr_val = 0;
5939 kvmclock_reset(vcpu);
5941 kvm_clear_async_pf_completion_queue(vcpu);
5942 kvm_async_pf_hash_reset(vcpu);
5943 vcpu->arch.apf.halted = false;
5945 kvm_pmu_reset(vcpu);
5947 return kvm_x86_ops->vcpu_reset(vcpu);
5950 int kvm_arch_hardware_enable(void *garbage)
5953 struct kvm_vcpu *vcpu;
5956 kvm_shared_msr_cpu_online();
5957 list_for_each_entry(kvm, &vm_list, vm_list)
5958 kvm_for_each_vcpu(i, vcpu, kvm)
5959 if (vcpu->cpu == smp_processor_id())
5960 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5961 return kvm_x86_ops->hardware_enable(garbage);
5964 void kvm_arch_hardware_disable(void *garbage)
5966 kvm_x86_ops->hardware_disable(garbage);
5967 drop_user_return_notifiers(garbage);
5970 int kvm_arch_hardware_setup(void)
5972 return kvm_x86_ops->hardware_setup();
5975 void kvm_arch_hardware_unsetup(void)
5977 kvm_x86_ops->hardware_unsetup();
5980 void kvm_arch_check_processor_compat(void *rtn)
5982 kvm_x86_ops->check_processor_compatibility(rtn);
5985 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5991 BUG_ON(vcpu->kvm == NULL);
5994 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
5995 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
5996 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5998 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6000 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6005 vcpu->arch.pio_data = page_address(page);
6007 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
6009 r = kvm_mmu_create(vcpu);
6011 goto fail_free_pio_data;
6013 if (irqchip_in_kernel(kvm)) {
6014 r = kvm_create_lapic(vcpu);
6016 goto fail_mmu_destroy;
6019 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6021 if (!vcpu->arch.mce_banks) {
6023 goto fail_free_lapic;
6025 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6027 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6028 goto fail_free_mce_banks;
6030 kvm_async_pf_hash_reset(vcpu);
6034 fail_free_mce_banks:
6035 kfree(vcpu->arch.mce_banks);
6037 kvm_free_lapic(vcpu);
6039 kvm_mmu_destroy(vcpu);
6041 free_page((unsigned long)vcpu->arch.pio_data);
6046 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6050 kvm_pmu_destroy(vcpu);
6051 kfree(vcpu->arch.mce_banks);
6052 kvm_free_lapic(vcpu);
6053 idx = srcu_read_lock(&vcpu->kvm->srcu);
6054 kvm_mmu_destroy(vcpu);
6055 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6056 free_page((unsigned long)vcpu->arch.pio_data);
6059 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6064 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6065 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6067 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6068 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6070 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6075 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6078 kvm_mmu_unload(vcpu);
6082 static void kvm_free_vcpus(struct kvm *kvm)
6085 struct kvm_vcpu *vcpu;
6088 * Unpin any mmu pages first.
6090 kvm_for_each_vcpu(i, vcpu, kvm) {
6091 kvm_clear_async_pf_completion_queue(vcpu);
6092 kvm_unload_vcpu_mmu(vcpu);
6094 kvm_for_each_vcpu(i, vcpu, kvm)
6095 kvm_arch_vcpu_free(vcpu);
6097 mutex_lock(&kvm->lock);
6098 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6099 kvm->vcpus[i] = NULL;
6101 atomic_set(&kvm->online_vcpus, 0);
6102 mutex_unlock(&kvm->lock);
6105 void kvm_arch_sync_events(struct kvm *kvm)
6107 kvm_free_all_assigned_devices(kvm);
6111 void kvm_arch_destroy_vm(struct kvm *kvm)
6113 kvm_iommu_unmap_guest(kvm);
6114 kfree(kvm->arch.vpic);
6115 kfree(kvm->arch.vioapic);
6116 kvm_free_vcpus(kvm);
6117 if (kvm->arch.apic_access_page)
6118 put_page(kvm->arch.apic_access_page);
6119 if (kvm->arch.ept_identity_pagetable)
6120 put_page(kvm->arch.ept_identity_pagetable);
6123 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6124 struct kvm_memory_slot *memslot,
6125 struct kvm_memory_slot old,
6126 struct kvm_userspace_memory_region *mem,
6129 int npages = memslot->npages;
6130 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6132 /* Prevent internal slot pages from being moved by fork()/COW. */
6133 if (memslot->id >= KVM_MEMORY_SLOTS)
6134 map_flags = MAP_SHARED | MAP_ANONYMOUS;
6136 /*To keep backward compatibility with older userspace,
6137 *x86 needs to hanlde !user_alloc case.
6140 if (npages && !old.rmap) {
6141 unsigned long userspace_addr;
6143 down_write(¤t->mm->mmap_sem);
6144 userspace_addr = do_mmap(NULL, 0,
6146 PROT_READ | PROT_WRITE,
6149 up_write(¤t->mm->mmap_sem);
6151 if (IS_ERR((void *)userspace_addr))
6152 return PTR_ERR((void *)userspace_addr);
6154 memslot->userspace_addr = userspace_addr;
6162 void kvm_arch_commit_memory_region(struct kvm *kvm,
6163 struct kvm_userspace_memory_region *mem,
6164 struct kvm_memory_slot old,
6168 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
6170 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6173 down_write(¤t->mm->mmap_sem);
6174 ret = do_munmap(current->mm, old.userspace_addr,
6175 old.npages * PAGE_SIZE);
6176 up_write(¤t->mm->mmap_sem);
6179 "kvm_vm_ioctl_set_memory_region: "
6180 "failed to munmap memory\n");
6183 if (!kvm->arch.n_requested_mmu_pages)
6184 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6186 spin_lock(&kvm->mmu_lock);
6188 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6189 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
6190 spin_unlock(&kvm->mmu_lock);
6193 void kvm_arch_flush_shadow(struct kvm *kvm)
6195 kvm_mmu_zap_all(kvm);
6196 kvm_reload_remote_mmus(kvm);
6199 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6201 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6202 !vcpu->arch.apf.halted)
6203 || !list_empty_careful(&vcpu->async_pf.done)
6204 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6205 || atomic_read(&vcpu->arch.nmi_queued) ||
6206 (kvm_arch_interrupt_allowed(vcpu) &&
6207 kvm_cpu_has_interrupt(vcpu));
6210 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6213 int cpu = vcpu->cpu;
6215 if (waitqueue_active(&vcpu->wq)) {
6216 wake_up_interruptible(&vcpu->wq);
6217 ++vcpu->stat.halt_wakeup;
6221 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6222 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
6223 smp_send_reschedule(cpu);
6227 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6229 return kvm_x86_ops->interrupt_allowed(vcpu);
6232 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6234 unsigned long current_rip = kvm_rip_read(vcpu) +
6235 get_segment_base(vcpu, VCPU_SREG_CS);
6237 return current_rip == linear_rip;
6239 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6241 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6243 unsigned long rflags;
6245 rflags = kvm_x86_ops->get_rflags(vcpu);
6246 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6247 rflags &= ~X86_EFLAGS_TF;
6250 EXPORT_SYMBOL_GPL(kvm_get_rflags);
6252 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6254 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
6255 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
6256 rflags |= X86_EFLAGS_TF;
6257 kvm_x86_ops->set_rflags(vcpu, rflags);
6258 kvm_make_request(KVM_REQ_EVENT, vcpu);
6260 EXPORT_SYMBOL_GPL(kvm_set_rflags);
6262 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6266 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
6267 is_error_page(work->page))
6270 r = kvm_mmu_reload(vcpu);
6274 if (!vcpu->arch.mmu.direct_map &&
6275 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6278 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6281 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6283 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6286 static inline u32 kvm_async_pf_next_probe(u32 key)
6288 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6291 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6293 u32 key = kvm_async_pf_hash_fn(gfn);
6295 while (vcpu->arch.apf.gfns[key] != ~0)
6296 key = kvm_async_pf_next_probe(key);
6298 vcpu->arch.apf.gfns[key] = gfn;
6301 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6304 u32 key = kvm_async_pf_hash_fn(gfn);
6306 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
6307 (vcpu->arch.apf.gfns[key] != gfn &&
6308 vcpu->arch.apf.gfns[key] != ~0); i++)
6309 key = kvm_async_pf_next_probe(key);
6314 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6316 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6319 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6323 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6325 vcpu->arch.apf.gfns[i] = ~0;
6327 j = kvm_async_pf_next_probe(j);
6328 if (vcpu->arch.apf.gfns[j] == ~0)
6330 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6332 * k lies cyclically in ]i,j]
6334 * |....j i.k.| or |.k..j i...|
6336 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6337 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6342 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6345 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6349 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6350 struct kvm_async_pf *work)
6352 struct x86_exception fault;
6354 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
6355 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
6357 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
6358 (vcpu->arch.apf.send_user_only &&
6359 kvm_x86_ops->get_cpl(vcpu) == 0))
6360 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6361 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6362 fault.vector = PF_VECTOR;
6363 fault.error_code_valid = true;
6364 fault.error_code = 0;
6365 fault.nested_page_fault = false;
6366 fault.address = work->arch.token;
6367 kvm_inject_page_fault(vcpu, &fault);
6371 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6372 struct kvm_async_pf *work)
6374 struct x86_exception fault;
6376 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6377 if (is_error_page(work->page))
6378 work->arch.token = ~0; /* broadcast wakeup */
6380 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6382 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6383 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6384 fault.vector = PF_VECTOR;
6385 fault.error_code_valid = true;
6386 fault.error_code = 0;
6387 fault.nested_page_fault = false;
6388 fault.address = work->arch.token;
6389 kvm_inject_page_fault(vcpu, &fault);
6391 vcpu->arch.apf.halted = false;
6394 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6396 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6399 return !kvm_event_needs_reinjection(vcpu) &&
6400 kvm_x86_ops->interrupt_allowed(vcpu);
6403 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6404 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6405 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6406 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6407 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
6408 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
6409 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
6410 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
6411 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
6412 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
6413 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
6414 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);