arch/x86/include/mach-xen/asm/system.h

   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9 #include <asm/hypervisor.h>
  10
  11 #include <linux/kernel.h>
  12 #include <linux/irqflags.h>
  13
  14 /* entries in ARCH_DLINFO: */
  15 #ifdef CONFIG_IA32_EMULATION
  16 # define AT_VECTOR_SIZE_ARCH 2
  17 #else
  18 # define AT_VECTOR_SIZE_ARCH 1
  19 #endif
  20
  21 struct task_struct; /* one of the stranger aspects of C forward declarations */
  22 struct task_struct *__switch_to(struct task_struct *prev,
  23                                 struct task_struct *next);
  24 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p);
  25
  26 #ifdef CONFIG_X86_32
  27
  28 #ifdef CONFIG_CC_STACKPROTECTOR
  29 #define __switch_canary                                                 \
  30         "movl %P[task_canary](%[next]), %%ebx\n\t"                      \
  31         "movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
  32 #define __switch_canary_oparam                                          \
  33         , [stack_canary] "=m" (per_cpu_var(stack_canary.canary))
  34 #define __switch_canary_iparam                                          \
  35         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
  36 #else   /* CC_STACKPROTECTOR */
  37 #define __switch_canary
  38 #define __switch_canary_oparam
  39 #define __switch_canary_iparam
  40 #endif  /* CC_STACKPROTECTOR */
  41
  42 /*
  43  * Saving eflags is important. It switches not only IOPL between tasks,
  44  * it also protects other tasks from NT leaking through sysenter etc.
  45  */
  46 #define switch_to(prev, next, last)                                     \
  47 do {                                                                    \
  48         /*                                                              \
  49          * Context-switching clobbers all registers, so we clobber      \
  50          * them explicitly, via unused output variables.                \
  51          * (EAX and EBP is not listed because EBP is saved/restored     \
  52          * explicitly for wchan access and EAX is the return value of   \
  53          * __switch_to())                                               \
  54          */                                                             \
  55         unsigned long ebx, ecx, edx, esi, edi;                          \
  56                                                                         \
  57         asm volatile("pushfl\n\t"               /* save    flags */     \
  58                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  59                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  60                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  61                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  62                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  63                      __switch_canary                                    \
  64                      "jmp __switch_to\n"        /* regparm call  */     \
  65                      "1:\t"                                             \
  66                      "popl %%ebp\n\t"           /* restore EBP   */     \
  67                      "popfl\n"                  /* restore flags */     \
  68                                                                         \
  69                      /* output parameters */                            \
  70                      : [prev_sp] "=m" (prev->thread.sp),                \
  71                        [prev_ip] "=m" (prev->thread.ip),                \
  72                        "=a" (last),                                     \
  73                                                                         \
  74                        /* clobbered output registers: */                \
  75                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  76                        "=S" (esi), "=D" (edi)                           \
  77                                                                         \
  78                        __switch_canary_oparam                           \
  79                                                                         \
  80                        /* input parameters: */                          \
  81                      : [next_sp]  "m" (next->thread.sp),                \
  82                        [next_ip]  "m" (next->thread.ip),                \
  83                                                                         \
  84                        /* regparm parameters for __switch_to(): */      \
  85                        [prev]     "a" (prev),                           \
  86                        [next]     "d" (next)                            \
  87                                                                         \
  88                        __switch_canary_iparam                           \
  89                                                                         \
  90                      : /* reloaded segment registers */                 \
  91                         "memory");                                      \
  92 } while (0)
  93
  94 /*
  95  * disable hlt during certain critical i/o operations
  96  */
  97 #define HAVE_DISABLE_HLT
  98 #else
  99 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
 100 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
 101
 102 /* frame pointer must be last for get_wchan */
 103 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
 104 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
 105
 106 #define __EXTRA_CLOBBER  \
 107         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
 108           "r12", "r13", "r14", "r15"
 109
 110 #ifdef CONFIG_CC_STACKPROTECTOR
 111 #define __switch_canary                                                   \
 112         "movq %P[task_canary](%%rsi),%%r8\n\t"                            \
 113         "movq %%r8,"__percpu_arg([gs_canary])"\n\t"
 114 #define __switch_canary_oparam                                            \
 115         , [gs_canary] "=m" (per_cpu_var(irq_stack_union.stack_canary))
 116 #define __switch_canary_iparam                                            \
 117         , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
 118 #else   /* CC_STACKPROTECTOR */
 119 #define __switch_canary
 120 #define __switch_canary_oparam
 121 #define __switch_canary_iparam
 122 #endif  /* CC_STACKPROTECTOR */
 123
 124 /* Save restore flags to clear handle leaking NT */
 125 #define switch_to(prev, next, last) \
 126         asm volatile(SAVE_CONTEXT                                         \
 127              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
 128              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
 129              "call __switch_to\n\t"                                       \
 130              ".globl thread_return\n"                                     \
 131              "thread_return:\n\t"                                         \
 132              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
 133              __switch_canary                                              \
 134              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
 135              "movq %%rax,%%rdi\n\t"                                       \
 136              "testl  %[_tif_fork],%P[ti_flags](%%r8)\n\t"         \
 137              "jnz   ret_from_fork\n\t"                                    \
 138              RESTORE_CONTEXT                                              \
 139              : "=a" (last)                                                \
 140                __switch_canary_oparam                                     \
 141              : [next] "S" (next), [prev] "D" (prev),                      \
 142                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 143                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 144                [_tif_fork] "i" (_TIF_FORK),                               \
 145                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 146                [current_task] "m" (per_cpu_var(current_task))             \
 147                __switch_canary_iparam                                     \
 148              : "memory", "cc" __EXTRA_CLOBBER)
 149 #endif
 150
 151 #ifdef __KERNEL__
 152
 153 extern void xen_load_gs_index(unsigned);
 154
 155 /*
 156  * Load a segment. Fall back on loading the zero
 157  * segment if something goes wrong..
 158  */
 159 #define loadsegment(seg, value)                 \
 160         asm volatile("\n"                       \
 161                      "1:\t"                     \
 162                      "movl %k0,%%" #seg "\n"    \
 163                      "2:\n"                     \
 164                      ".section .fixup,\"ax\"\n" \
 165                      "3:\t"                     \
 166                      "movl %k1, %%" #seg "\n\t" \
 167                      "jmp 2b\n"                 \
 168                      ".previous\n"              \
 169                      _ASM_EXTABLE(1b,3b)        \
 170                      : :"r" (value), "r" (0) : "memory")
 171
 172
 173 /*
 174  * Save a segment register away
 175  */
 176 #define savesegment(seg, value)                         \
 177         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 178
 179 /*
 180  * x86_32 user gs accessors.
 181  */
 182 #ifdef CONFIG_X86_32
 183 #ifdef CONFIG_X86_32_LAZY_GS
 184 #define get_user_gs(regs)       (u16)({unsigned long v; savesegment(gs, v); v;})
 185 #define set_user_gs(regs, v)    loadsegment(gs, (unsigned long)(v))
 186 #define task_user_gs(tsk)       ((tsk)->thread.gs)
 187 #define lazy_save_gs(v)         savesegment(gs, (v))
 188 #define lazy_load_gs(v)         loadsegment(gs, (v))
 189 #else   /* X86_32_LAZY_GS */
 190 #define get_user_gs(regs)       (u16)((regs)->gs)
 191 #define set_user_gs(regs, v)    do { (regs)->gs = (v); } while (0)
 192 #define task_user_gs(tsk)       (task_pt_regs(tsk)->gs)
 193 #define lazy_save_gs(v)         do { } while (0)
 194 #define lazy_load_gs(v)         do { } while (0)
 195 #endif  /* X86_32_LAZY_GS */
 196 #endif  /* X86_32 */
 197
 198 static inline unsigned long get_limit(unsigned long segment)
 199 {
 200         unsigned long __limit;
 201         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 202         return __limit + 1;
 203 }
 204
 205 static inline void xen_clts(void)
 206 {
 207         HYPERVISOR_fpu_taskswitch(0);
 208 }
 209
 210 static inline void xen_stts(void)
 211 {
 212         HYPERVISOR_fpu_taskswitch(1);
 213 }
 214
 215 /*
 216  * Volatile isn't enough to prevent the compiler from reordering the
 217  * read/write functions for the control registers and messing everything up.
 218  * A memory clobber would solve the problem, but would prevent reordering of
 219  * all loads stores around it, which can hurt performance. Solution is to
 220  * use a variable and mimic reads and writes to it to enforce serialization
 221  */
 222 static unsigned long __force_order;
 223
 224 static inline unsigned long xen_read_cr0(void)
 225 {
 226         unsigned long val;
 227         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 228         return val;
 229 }
 230
 231 static inline void xen_write_cr0(unsigned long val)
 232 {
 233         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 234 }
 235
 236 #define xen_read_cr2() vcpu_info_read(arch.cr2)
 237 #define xen_write_cr2(val) vcpu_info_write(arch.cr2, val)
 238
 239 static inline unsigned long xen_read_cr3(void)
 240 {
 241         unsigned long val;
 242         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 243 #ifdef CONFIG_X86_32
 244         return mfn_to_pfn(xen_cr3_to_pfn(val)) << PAGE_SHIFT;
 245 #else
 246         return machine_to_phys(val);
 247 #endif
 248 }
 249
 250 static inline void xen_write_cr3(unsigned long val)
 251 {
 252 #ifdef CONFIG_X86_32
 253         val = xen_pfn_to_cr3(pfn_to_mfn(val >> PAGE_SHIFT));
 254 #else
 255         val = phys_to_machine(val);
 256 #endif
 257         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 258 }
 259
 260 static inline unsigned long xen_read_cr4(void)
 261 {
 262         unsigned long val;
 263         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 264         return val;
 265 }
 266
 267 #define xen_read_cr4_safe() xen_read_cr4()
 268
 269 static inline void xen_write_cr4(unsigned long val)
 270 {
 271         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 272 }
 273
 274 #ifdef CONFIG_X86_64
 275 static inline unsigned long xen_read_cr8(void)
 276 {
 277         return 0;
 278 }
 279
 280 static inline void xen_write_cr8(unsigned long val)
 281 {
 282         BUG_ON(val);
 283 }
 284 #endif
 285
 286 static inline void xen_wbinvd(void)
 287 {
 288         asm volatile("wbinvd": : :"memory");
 289 }
 290
 291 #define read_cr0()      (xen_read_cr0())
 292 #define write_cr0(x)    (xen_write_cr0(x))
 293 #define read_cr2()      (xen_read_cr2())
 294 #define write_cr2(x)    (xen_write_cr2(x))
 295 #define read_cr3()      (xen_read_cr3())
 296 #define write_cr3(x)    (xen_write_cr3(x))
 297 #define read_cr4()      (xen_read_cr4())
 298 #define read_cr4_safe() (xen_read_cr4_safe())
 299 #define write_cr4(x)    (xen_write_cr4(x))
 300 #define wbinvd()        (xen_wbinvd())
 301 #ifdef CONFIG_X86_64
 302 #define read_cr8()      (xen_read_cr8())
 303 #define write_cr8(x)    (xen_write_cr8(x))
 304 #define load_gs_index   xen_load_gs_index
 305 #endif
 306
 307 /* Clear the 'TS' bit */
 308 #define clts()          (xen_clts())
 309 #define stts()          (xen_stts())
 310
 311 #endif /* __KERNEL__ */
 312
 313 static inline void clflush(volatile void *__p)
 314 {
 315         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 316 }
 317
 318 #define nop() asm volatile ("nop")
 319
 320 void disable_hlt(void);
 321 void enable_hlt(void);
 322
 323 void cpu_idle_wait(void);
 324
 325 extern unsigned long arch_align_stack(unsigned long sp);
 326 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 327
 328 void xen_idle(void);
 329
 330 void stop_this_cpu(void *dummy);
 331
 332 /*
 333  * Force strict CPU ordering.
 334  * And yes, this is required on UP too when we're talking
 335  * to devices.
 336  */
 337 #ifdef CONFIG_X86_32
 338 /*
 339  * Some non-Intel clones support out of order store. wmb() ceases to be a
 340  * nop for these.
 341  */
 342 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 343 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 344 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 345 #else
 346 #define mb()    asm volatile("mfence":::"memory")
 347 #define rmb()   asm volatile("lfence":::"memory")
 348 #define wmb()   asm volatile("sfence" ::: "memory")
 349 #endif
 350
 351 /**
 352  * read_barrier_depends - Flush all pending reads that subsequents reads
 353  * depend on.
 354  *
 355  * No data-dependent reads from memory-like regions are ever reordered
 356  * over this barrier.  All reads preceding this primitive are guaranteed
 357  * to access memory (but not necessarily other CPUs' caches) before any
 358  * reads following this primitive that depend on the data return by
 359  * any of the preceding reads.  This primitive is much lighter weight than
 360  * rmb() on most CPUs, and is never heavier weight than is
 361  * rmb().
 362  *
 363  * These ordering constraints are respected by both the local CPU
 364  * and the compiler.
 365  *
 366  * Ordering is not guaranteed by anything other than these primitives,
 367  * not even by data dependencies.  See the documentation for
 368  * memory_barrier() for examples and URLs to more information.
 369  *
 370  * For example, the following code would force ordering (the initial
 371  * value of "a" is zero, "b" is one, and "p" is "&a"):
 372  *
 373  * <programlisting>
 374  *      CPU 0                           CPU 1
 375  *
 376  *      b = 2;
 377  *      memory_barrier();
 378  *      p = &b;                         q = p;
 379  *                                      read_barrier_depends();
 380  *                                      d = *q;
 381  * </programlisting>
 382  *
 383  * because the read of "*q" depends on the read of "p" and these
 384  * two reads are separated by a read_barrier_depends().  However,
 385  * the following code, with the same initial values for "a" and "b":
 386  *
 387  * <programlisting>
 388  *      CPU 0                           CPU 1
 389  *
 390  *      a = 2;
 391  *      memory_barrier();
 392  *      b = 3;                          y = b;
 393  *                                      read_barrier_depends();
 394  *                                      x = a;
 395  * </programlisting>
 396  *
 397  * does not enforce ordering, since there is no data dependency between
 398  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 399  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 400  * in cases like this where there are no data dependencies.
 401  **/
 402
 403 #define read_barrier_depends()  do { } while (0)
 404
 405 #ifdef CONFIG_SMP
 406 #define smp_mb()        mb()
 407 #ifdef CONFIG_X86_PPRO_FENCE
 408 # define smp_rmb()      rmb()
 409 #else
 410 # define smp_rmb()      barrier()
 411 #endif
 412 #ifdef CONFIG_X86_OOSTORE
 413 # define smp_wmb()      wmb()
 414 #else
 415 # define smp_wmb()      barrier()
 416 #endif
 417 #define smp_read_barrier_depends()      read_barrier_depends()
 418 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 419 #else
 420 #define smp_mb()        barrier()
 421 #define smp_rmb()       barrier()
 422 #define smp_wmb()       barrier()
 423 #define smp_read_barrier_depends()      do { } while (0)
 424 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 425 #endif
 426
 427 /*
 428  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 429  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 430  * code region.
 431  *
 432  * (Could use an alternative three way for this if there was one.)
 433  */
 434 static inline void rdtsc_barrier(void)
 435 {
 436         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 437         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 438 }
 439
 440 #endif /* _ASM_X86_SYSTEM_H */