drivers/staging/rtl8192u/r819xU_cmdpkt.h

   1 #ifndef R819XUSB_CMDPKT_H
   2 #define R819XUSB_CMDPKT_H
   3 /* Different command packet have dedicated message length and definition. */
   4 #define         CMPK_RX_TX_FB_SIZE                                      sizeof(cmpk_txfb_t)             //20
   5 #define         CMPK_TX_SET_CONFIG_SIZE                         sizeof(cmpk_set_cfg_t)  //16
   6 #define         CMPK_BOTH_QUERY_CONFIG_SIZE                     sizeof(cmpk_set_cfg_t)  //16
   7 #define         CMPK_RX_TX_STS_SIZE                                     sizeof(cmpk_tx_status_t)//
   8 #define         CMPK_RX_DBG_MSG_SIZE                    sizeof(cmpk_rx_dbginfo_t)//
   9 #define         CMPK_TX_RAHIS_SIZE                      sizeof(cmpk_tx_rahis_t)
  10
  11 /* 2008/05/08 amy For USB constant. */
  12 #define ISR_TxBcnOk                                     BIT27                   // Transmit Beacon OK
  13 #define ISR_TxBcnErr                            BIT26                   // Transmit Beacon Error
  14 #define ISR_BcnTimerIntr                        BIT13                   // Beacon Timer Interrupt
  15
  16
  17 /* Define element ID of command packet. */
  18
  19 /*------------------------------Define structure----------------------------*/
  20 /* Define different command packet structure. */
  21 /* 1. RX side: TX feedback packet. */
  22 typedef struct tag_cmd_pkt_tx_feedback
  23 {
  24         // DWORD 0
  25         u8      element_id;                     /* Command packet type. */
  26         u8      length;                         /* Command packet length. */
  27         /* 2007/07/05 MH Change tx feedback info field. */
  28         /*------TX Feedback Info Field */
  29         u8      TID:4;                          /* */
  30         u8      fail_reason:3;          /* */
  31         u8      tok:1;                          /* Transmit ok. */
  32         u8      reserve1:4;                     /* */
  33         u8      pkt_type:2;             /* */
  34         u8      bandwidth:1;            /* */
  35         u8      qos_pkt:1;                      /* */
  36
  37         // DWORD 1
  38         u8      reserve2;                       /* */
  39         /*------TX Feedback Info Field */
  40         u8      retry_cnt;                      /* */
  41         u16     pkt_id;                         /* */
  42
  43         // DWORD 3
  44         u16     seq_num;                        /* */
  45         u8      s_rate;                         /* Start rate. */
  46         u8      f_rate;                         /* Final rate. */
  47
  48         // DWORD 4
  49         u8      s_rts_rate;                     /* */
  50         u8      f_rts_rate;                     /* */
  51         u16     pkt_length;                     /* */
  52
  53         // DWORD 5
  54         u16     reserve3;                       /* */
  55         u16     duration;                       /* */
  56 }cmpk_txfb_t;
  57
  58 /* 2. RX side: Interrupt status packet. It includes Beacon State,
  59           Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  60 typedef struct tag_cmd_pkt_interrupt_status
  61 {
  62         u8      element_id;                     /* Command packet type. */
  63         u8      length;                         /* Command packet length. */
  64         u16     reserve;
  65         u32     interrupt_status;                               /* Interrupt Status. */
  66 }cmpk_intr_sta_t;
  67
  68
  69 /* 3. TX side: Set configuration packet. */
  70 typedef struct tag_cmd_pkt_set_configuration
  71 {
  72         u8      element_id;                     /* Command packet type. */
  73         u8      length;                         /* Command packet length. */
  74         u16     reserve1;                       /* */
  75         u8      cfg_reserve1:3;
  76         u8      cfg_size:2;                     /* Configuration info. */
  77         u8      cfg_type:2;                     /* Configuration info. */
  78         u8      cfg_action:1;           /* Configuration info. */
  79         u8      cfg_reserve2;           /* Configuration info. */
  80         u8      cfg_page:4;                     /* Configuration info. */
  81         u8      cfg_reserve3:4;         /* Configuration info. */
  82         u8      cfg_offset;                     /* Configuration info. */
  83         u32     value;                          /* */
  84         u32     mask;                           /* */
  85 }cmpk_set_cfg_t;
  86
  87 /* 4. Both side : TX/RX query configuraton packet. The query structure is the
  88       same as set configuration. */
  89 #define         cmpk_query_cfg_t        cmpk_set_cfg_t
  90
  91 /* 5. Multi packet feedback status. */
  92 typedef struct tag_tx_stats_feedback // PJ quick rxcmd 09042007
  93 {
  94         // For endian transfer --> Driver will not the same as firmware structure.
  95         // DW 0
  96         u16     reserve1;
  97         u8      length;                         // Command packet length
  98         u8      element_id;                     // Command packet type
  99
 100         // DW 1
 101         u16     txfail;                         // Tx Fail count
 102         u16     txok;                           // Tx ok count
 103
 104         // DW 2
 105         u16     txmcok;                         // tx multicast
 106         u16     txretry;                        // Tx Retry count
 107
 108         // DW 3
 109         u16  txucok;                            // tx unicast
 110         u16     txbcok;                         // tx broadcast
 111
 112         // DW 4
 113         u16     txbcfail;                       //
 114         u16     txmcfail;                       //
 115
 116         // DW 5
 117         u16     reserve2;                       //
 118         u16     txucfail;                       //
 119
 120         // DW 6-8
 121         u32     txmclength;
 122         u32     txbclength;
 123         u32     txuclength;
 124
 125         // DW 9
 126         u16     reserve3_23;
 127         u8      reserve3_1;
 128         u8      rate;
 129 }__attribute__((packed)) cmpk_tx_status_t;
 130
 131 /* 6. Debug feedback message. */
 132 /* 2007/10/23 MH Define RX debug message  */
 133 typedef struct tag_rx_debug_message_feedback
 134 {
 135         // For endian transfer --> for driver
 136         // DW 0
 137         u16     reserve1;
 138         u8      length;                         // Command packet length
 139         u8      element_id;                     // Command packet type
 140
 141         // DW 1-??
 142         // Variable debug message.
 143
 144 }cmpk_rx_dbginfo_t;
 145
 146 /* 2008/03/20 MH Define transmit rate history. For big endian format. */
 147 typedef struct tag_tx_rate_history
 148 {
 149         // For endian transfer --> for driver
 150         // DW 0
 151         u8      element_id;                     // Command packet type
 152         u8      length;                         // Command packet length
 153         u16     reserved1;
 154
 155         // DW 1-2       CCK rate counter
 156         u16     cck[4];
 157
 158         // DW 3-6
 159         u16     ofdm[8];
 160
 161         // DW 7-14
 162         //UINT16        MCS_BW0_SG0[16];
 163
 164         // DW 15-22
 165         //UINT16        MCS_BW1_SG0[16];
 166
 167         // DW 23-30
 168         //UINT16        MCS_BW0_SG1[16];
 169
 170         // DW 31-38
 171         //UINT16        MCS_BW1_SG1[16];
 172
 173         // DW 7-14      BW=0 SG=0
 174         // DW 15-22     BW=1 SG=0
 175         // DW 23-30     BW=0 SG=1
 176         // DW 31-38     BW=1 SG=1
 177         u16     ht_mcs[4][16];
 178
 179 }__attribute__((packed)) cmpk_tx_rahis_t;
 180
 181 typedef enum tag_command_packet_directories
 182 {
 183     RX_TX_FEEDBACK = 0,
 184     RX_INTERRUPT_STATUS         = 1,
 185     TX_SET_CONFIG                               = 2,
 186     BOTH_QUERY_CONFIG                   = 3,
 187     RX_TX_STATUS                                = 4,
 188     RX_DBGINFO_FEEDBACK         = 5,
 189     RX_TX_PER_PKT_FEEDBACK              = 6,
 190     RX_TX_RATE_HISTORY          = 7,
 191     RX_CMD_ELE_MAX
 192 }cmpk_element_e;
 193
 194 typedef enum _rt_status{
 195         RT_STATUS_SUCCESS,
 196         RT_STATUS_FAILURE,
 197         RT_STATUS_PENDING,
 198         RT_STATUS_RESOURCE
 199 }rt_status,*prt_status;
 200
 201 extern rt_status cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
 202
 203 extern  u32 cmpk_message_handle_rx(struct net_device *dev, struct ieee80211_rx_stats * pstats);
 204 extern rt_status SendTxCommandPacket( struct net_device *dev, void* pData, u32 DataLen);
 205
 206
 207 #endif