drivers/net/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5   Copyright (C) 2007-2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/kernel.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/crc32.h>
  44 #include <linux/mii.h>
  45 #include <linux/phy.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/stm/soc.h>
  49 #include "stmmac.h"
  50
  51 #define STMMAC_RESOURCE_NAME    "stmmaceth"
  52 #define PHY_RESOURCE_NAME       "stmmacphy"
  53
  54 #undef STMMAC_DEBUG
  55 /*#define STMMAC_DEBUG*/
  56 #ifdef STMMAC_DEBUG
  57 #define DBG(nlevel, klevel, fmt, args...) \
  58                 ((void)(netif_msg_##nlevel(priv) && \
  59                 printk(KERN_##klevel fmt, ## args)))
  60 #else
  61 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  62 #endif
  63
  64 #undef STMMAC_RX_DEBUG
  65 /*#define STMMAC_RX_DEBUG*/
  66 #ifdef STMMAC_RX_DEBUG
  67 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  68 #else
  69 #define RX_DBG(fmt, args...)  do { } while (0)
  70 #endif
  71
  72 #undef STMMAC_XMIT_DEBUG
  73 /*#define STMMAC_XMIT_DEBUG*/
  74 #ifdef STMMAC_TX_DEBUG
  75 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  76 #else
  77 #define TX_DBG(fmt, args...)  do { } while (0)
  78 #endif
  79
  80 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  81 #define JUMBO_LEN       9000
  82
  83 /* Module parameters */
  84 #define TX_TIMEO 5000 /* default 5 seconds */
  85 static int watchdog = TX_TIMEO;
  86 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  87 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  88
  89 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  90 module_param(debug, int, S_IRUGO | S_IWUSR);
  91 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  92
  93 static int phyaddr = -1;
  94 module_param(phyaddr, int, S_IRUGO);
  95 MODULE_PARM_DESC(phyaddr, "Physical device address");
  96
  97 #define DMA_TX_SIZE 256
  98 static int dma_txsize = DMA_TX_SIZE;
  99 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
 100 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 101
 102 #define DMA_RX_SIZE 256
 103 static int dma_rxsize = DMA_RX_SIZE;
 104 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 105 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 106
 107 static int flow_ctrl = FLOW_OFF;
 108 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 109 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 110
 111 static int pause = PAUSE_TIME;
 112 module_param(pause, int, S_IRUGO | S_IWUSR);
 113 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 114
 115 #define TC_DEFAULT 64
 116 static int tc = TC_DEFAULT;
 117 module_param(tc, int, S_IRUGO | S_IWUSR);
 118 MODULE_PARM_DESC(tc, "DMA threshold control value");
 119
 120 #define RX_NO_COALESCE  1       /* Always interrupt on completion */
 121 #define TX_NO_COALESCE  -1      /* No moderation by default */
 122
 123 /* Pay attention to tune this parameter; take care of both
 124  * hardware capability and network stabitily/performance impact.
 125  * Many tests showed that ~4ms latency seems to be good enough. */
 126 #ifdef CONFIG_STMMAC_TIMER
 127 #define DEFAULT_PERIODIC_RATE   256
 128 static int tmrate = DEFAULT_PERIODIC_RATE;
 129 module_param(tmrate, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
 131 #endif
 132
 133 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 134 static int buf_sz = DMA_BUFFER_SIZE;
 135 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 136 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 137
 138 /* In case of Giga ETH, we can enable/disable the COE for the
 139  * transmit HW checksum computation.
 140  * Note that, if tx csum is off in HW, SG will be still supported. */
 141 static int tx_coe = HW_CSUM;
 142 module_param(tx_coe, int, S_IRUGO | S_IWUSR);
 143 MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
 144
 145 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 146                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 147                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 148
 149 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 150 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
 151
 152 /**
 153  * stmmac_verify_args - verify the driver parameters.
 154  * Description: it verifies if some wrong parameter is passed to the driver.
 155  * Note that wrong parameters are replaced with the default values.
 156  */
 157 static void stmmac_verify_args(void)
 158 {
 159         if (unlikely(watchdog < 0))
 160                 watchdog = TX_TIMEO;
 161         if (unlikely(dma_rxsize < 0))
 162                 dma_rxsize = DMA_RX_SIZE;
 163         if (unlikely(dma_txsize < 0))
 164                 dma_txsize = DMA_TX_SIZE;
 165         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 166                 buf_sz = DMA_BUFFER_SIZE;
 167         if (unlikely(flow_ctrl > 1))
 168                 flow_ctrl = FLOW_AUTO;
 169         else if (likely(flow_ctrl < 0))
 170                 flow_ctrl = FLOW_OFF;
 171         if (unlikely((pause < 0) || (pause > 0xffff)))
 172                 pause = PAUSE_TIME;
 173
 174         return;
 175 }
 176
 177 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 178 static void print_pkt(unsigned char *buf, int len)
 179 {
 180         int j;
 181         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 182         for (j = 0; j < len; j++) {
 183                 if ((j % 16) == 0)
 184                         pr_info("\n %03x:", j);
 185                 pr_info(" %02x", buf[j]);
 186         }
 187         pr_info("\n");
 188         return;
 189 }
 190 #endif
 191
 192 /* minimum number of free TX descriptors required to wake up TX process */
 193 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 194
 195 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 196 {
 197         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 198 }
 199
 200 /**
 201  * stmmac_adjust_link
 202  * @dev: net device structure
 203  * Description: it adjusts the link parameters.
 204  */
 205 static void stmmac_adjust_link(struct net_device *dev)
 206 {
 207         struct stmmac_priv *priv = netdev_priv(dev);
 208         struct phy_device *phydev = priv->phydev;
 209         unsigned long ioaddr = dev->base_addr;
 210         unsigned long flags;
 211         int new_state = 0;
 212         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 213
 214         if (phydev == NULL)
 215                 return;
 216
 217         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 218             phydev->addr, phydev->link);
 219
 220         spin_lock_irqsave(&priv->lock, flags);
 221         if (phydev->link) {
 222                 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
 223
 224                 /* Now we make sure that we can be in full duplex mode.
 225                  * If not, we operate in half-duplex mode. */
 226                 if (phydev->duplex != priv->oldduplex) {
 227                         new_state = 1;
 228                         if (!(phydev->duplex))
 229                                 ctrl &= ~priv->mac_type->hw.link.duplex;
 230                         else
 231                                 ctrl |= priv->mac_type->hw.link.duplex;
 232                         priv->oldduplex = phydev->duplex;
 233                 }
 234                 /* Flow Control operation */
 235                 if (phydev->pause)
 236                         priv->mac_type->ops->flow_ctrl(ioaddr, phydev->duplex,
 237                                                        fc, pause_time);
 238
 239                 if (phydev->speed != priv->speed) {
 240                         new_state = 1;
 241                         switch (phydev->speed) {
 242                         case 1000:
 243                                 if (likely(priv->is_gmac))
 244                                         ctrl &= ~priv->mac_type->hw.link.port;
 245                                 break;
 246                         case 100:
 247                         case 10:
 248                                 if (priv->is_gmac) {
 249                                         ctrl |= priv->mac_type->hw.link.port;
 250                                         if (phydev->speed == SPEED_100) {
 251                                                 ctrl |=
 252                                                     priv->mac_type->hw.link.
 253                                                     speed;
 254                                         } else {
 255                                                 ctrl &=
 256                                                     ~(priv->mac_type->hw.
 257                                                       link.speed);
 258                                         }
 259                                 } else {
 260                                         ctrl &= ~priv->mac_type->hw.link.port;
 261                                 }
 262                                 priv->fix_mac_speed(priv->bsp_priv,
 263                                                     phydev->speed);
 264                                 break;
 265                         default:
 266                                 if (netif_msg_link(priv))
 267                                         pr_warning("%s: Speed (%d) is not 10"
 268                                        " or 100!\n", dev->name, phydev->speed);
 269                                 break;
 270                         }
 271
 272                         priv->speed = phydev->speed;
 273                 }
 274
 275                 writel(ctrl, ioaddr + MAC_CTRL_REG);
 276
 277                 if (!priv->oldlink) {
 278                         new_state = 1;
 279                         priv->oldlink = 1;
 280                 }
 281         } else if (priv->oldlink) {
 282                 new_state = 1;
 283                 priv->oldlink = 0;
 284                 priv->speed = 0;
 285                 priv->oldduplex = -1;
 286         }
 287
 288         if (new_state && netif_msg_link(priv))
 289                 phy_print_status(phydev);
 290
 291         spin_unlock_irqrestore(&priv->lock, flags);
 292
 293         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 294 }
 295
 296 /**
 297  * stmmac_init_phy - PHY initialization
 298  * @dev: net device structure
 299  * Description: it initializes the driver's PHY state, and attaches the PHY
 300  * to the mac driver.
 301  *  Return value:
 302  *  0 on success
 303  */
 304 static int stmmac_init_phy(struct net_device *dev)
 305 {
 306         struct stmmac_priv *priv = netdev_priv(dev);
 307         struct phy_device *phydev;
 308         char phy_id[BUS_ID_SIZE];       /* PHY to connect */
 309         char bus_id[BUS_ID_SIZE];
 310
 311         priv->oldlink = 0;
 312         priv->speed = 0;
 313         priv->oldduplex = -1;
 314
 315         if (priv->phy_addr == -1) {
 316                 /* We don't have a PHY, so do nothing */
 317                 return 0;
 318         }
 319
 320         snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
 321         snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, bus_id, priv->phy_addr);
 322         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
 323
 324         phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
 325                         priv->phy_interface);
 326
 327         if (IS_ERR(phydev)) {
 328                 pr_err("%s: Could not attach to PHY\n", dev->name);
 329                 return PTR_ERR(phydev);
 330         }
 331
 332         /*
 333          * Broken HW is sometimes missing the pull-up resistor on the
 334          * MDIO line, which results in reads to non-existent devices returning
 335          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 336          * device as well.
 337          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 338          */
 339         if (phydev->phy_id == 0) {
 340                 phy_disconnect(phydev);
 341                 return -ENODEV;
 342         }
 343         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 344                " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 345
 346         priv->phydev = phydev;
 347
 348         return 0;
 349 }
 350
 351 static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
 352 {
 353         u32 value = readl(ioaddr + MAC_CTRL_REG);
 354         value |= MAC_RNABLE_RX;
 355         /* Set the RE (receive enable bit into the MAC CTRL register).  */
 356         writel(value, ioaddr + MAC_CTRL_REG);
 357 }
 358
 359 static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
 360 {
 361         u32 value = readl(ioaddr + MAC_CTRL_REG);
 362         value |= MAC_ENABLE_TX;
 363         /* Set the TE (transmit enable bit into the MAC CTRL register).  */
 364         writel(value, ioaddr + MAC_CTRL_REG);
 365 }
 366
 367 static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
 368 {
 369         u32 value = readl(ioaddr + MAC_CTRL_REG);
 370         value &= ~MAC_RNABLE_RX;
 371         writel(value, ioaddr + MAC_CTRL_REG);
 372 }
 373
 374 static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
 375 {
 376         u32 value = readl(ioaddr + MAC_CTRL_REG);
 377         value &= ~MAC_ENABLE_TX;
 378         writel(value, ioaddr + MAC_CTRL_REG);
 379 }
 380
 381 /**
 382  * display_ring
 383  * @p: pointer to the ring.
 384  * @size: size of the ring.
 385  * Description: display all the descriptors within the ring.
 386  */
 387 static void display_ring(struct dma_desc *p, int size)
 388 {
 389         struct tmp_s {
 390                 u64 a;
 391                 unsigned int b;
 392                 unsigned int c;
 393         };
 394         int i;
 395         for (i = 0; i < size; i++) {
 396                 struct tmp_s *x = (struct tmp_s *)(p + i);
 397                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 398                        i, (unsigned int)virt_to_phys(&p[i]),
 399                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 400                        x->b, x->c);
 401                 pr_info("\n");
 402         }
 403 }
 404
 405 /**
 406  * init_dma_desc_rings - init the RX/TX descriptor rings
 407  * @dev: net device structure
 408  * Description:  this function initializes the DMA RX/TX descriptors
 409  * and allocates the socket buffers.
 410  */
 411 static void init_dma_desc_rings(struct net_device *dev)
 412 {
 413         int i;
 414         struct stmmac_priv *priv = netdev_priv(dev);
 415         struct sk_buff *skb;
 416         unsigned int txsize = priv->dma_tx_size;
 417         unsigned int rxsize = priv->dma_rx_size;
 418         unsigned int bfsize = priv->dma_buf_sz;
 419         int buff2_needed = 0, dis_ic = 0;
 420
 421         /* Set the Buffer size according to the MTU;
 422          * indeed, in case of jumbo we need to bump-up the buffer sizes.
 423          */
 424         if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
 425                 bfsize = BUF_SIZE_16KiB;
 426         else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
 427                 bfsize = BUF_SIZE_8KiB;
 428         else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
 429                 bfsize = BUF_SIZE_4KiB;
 430         else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
 431                 bfsize = BUF_SIZE_2KiB;
 432         else
 433                 bfsize = DMA_BUFFER_SIZE;
 434
 435 #ifdef CONFIG_STMMAC_TIMER
 436         /* Disable interrupts on completion for the reception if timer is on */
 437         if (likely(priv->tm->enable))
 438                 dis_ic = 1;
 439 #endif
 440         /* If the MTU exceeds 8k so use the second buffer in the chain */
 441         if (bfsize >= BUF_SIZE_8KiB)
 442                 buff2_needed = 1;
 443
 444         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 445             txsize, rxsize, bfsize);
 446
 447         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
 448         priv->rx_skbuff =
 449             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
 450         priv->dma_rx =
 451             (struct dma_desc *)dma_alloc_coherent(priv->device,
 452                                                   rxsize *
 453                                                   sizeof(struct dma_desc),
 454                                                   &priv->dma_rx_phy,
 455                                                   GFP_KERNEL);
 456         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
 457                                        GFP_KERNEL);
 458         priv->dma_tx =
 459             (struct dma_desc *)dma_alloc_coherent(priv->device,
 460                                                   txsize *
 461                                                   sizeof(struct dma_desc),
 462                                                   &priv->dma_tx_phy,
 463                                                   GFP_KERNEL);
 464
 465         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
 466                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
 467                 return;
 468         }
 469
 470         DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
 471             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 472             dev->name, priv->dma_rx, priv->dma_tx,
 473             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 474
 475         /* RX INITIALIZATION */
 476         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 477                          "skb\t\tskb data\tdma data\n");
 478
 479         for (i = 0; i < rxsize; i++) {
 480                 struct dma_desc *p = priv->dma_rx + i;
 481
 482                 skb = netdev_alloc_skb_ip_align(dev, bfsize);
 483                 if (unlikely(skb == NULL)) {
 484                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 485                         break;
 486                 }
 487                 priv->rx_skbuff[i] = skb;
 488                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 489                                                 bfsize, DMA_FROM_DEVICE);
 490
 491                 p->des2 = priv->rx_skbuff_dma[i];
 492                 if (unlikely(buff2_needed))
 493                         p->des3 = p->des2 + BUF_SIZE_8KiB;
 494                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 495                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 496         }
 497         priv->cur_rx = 0;
 498         priv->dirty_rx = (unsigned int)(i - rxsize);
 499         priv->dma_buf_sz = bfsize;
 500         buf_sz = bfsize;
 501
 502         /* TX INITIALIZATION */
 503         for (i = 0; i < txsize; i++) {
 504                 priv->tx_skbuff[i] = NULL;
 505                 priv->dma_tx[i].des2 = 0;
 506         }
 507         priv->dirty_tx = 0;
 508         priv->cur_tx = 0;
 509
 510         /* Clear the Rx/Tx descriptors */
 511         priv->mac_type->ops->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 512         priv->mac_type->ops->init_tx_desc(priv->dma_tx, txsize);
 513
 514         if (netif_msg_hw(priv)) {
 515                 pr_info("RX descriptor ring:\n");
 516                 display_ring(priv->dma_rx, rxsize);
 517                 pr_info("TX descriptor ring:\n");
 518                 display_ring(priv->dma_tx, txsize);
 519         }
 520         return;
 521 }
 522
 523 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 524 {
 525         int i;
 526
 527         for (i = 0; i < priv->dma_rx_size; i++) {
 528                 if (priv->rx_skbuff[i]) {
 529                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 530                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 531                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 532                 }
 533                 priv->rx_skbuff[i] = NULL;
 534         }
 535         return;
 536 }
 537
 538 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 539 {
 540         int i;
 541
 542         for (i = 0; i < priv->dma_tx_size; i++) {
 543                 if (priv->tx_skbuff[i] != NULL) {
 544                         struct dma_desc *p = priv->dma_tx + i;
 545                         if (p->des2)
 546                                 dma_unmap_single(priv->device, p->des2,
 547                                  priv->mac_type->ops->get_tx_len(p),
 548                                  DMA_TO_DEVICE);
 549                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 550                         priv->tx_skbuff[i] = NULL;
 551                 }
 552         }
 553         return;
 554 }
 555
 556 static void free_dma_desc_resources(struct stmmac_priv *priv)
 557 {
 558         /* Release the DMA TX/RX socket buffers */
 559         dma_free_rx_skbufs(priv);
 560         dma_free_tx_skbufs(priv);
 561
 562         /* Free the region of consistent memory previously allocated for
 563          * the DMA */
 564         dma_free_coherent(priv->device,
 565                           priv->dma_tx_size * sizeof(struct dma_desc),
 566                           priv->dma_tx, priv->dma_tx_phy);
 567         dma_free_coherent(priv->device,
 568                           priv->dma_rx_size * sizeof(struct dma_desc),
 569                           priv->dma_rx, priv->dma_rx_phy);
 570         kfree(priv->rx_skbuff_dma);
 571         kfree(priv->rx_skbuff);
 572         kfree(priv->tx_skbuff);
 573
 574         return;
 575 }
 576
 577 /**
 578  * stmmac_dma_start_tx
 579  * @ioaddr: device I/O address
 580  * Description:  this function starts the DMA tx process.
 581  */
 582 static void stmmac_dma_start_tx(unsigned long ioaddr)
 583 {
 584         u32 value = readl(ioaddr + DMA_CONTROL);
 585         value |= DMA_CONTROL_ST;
 586         writel(value, ioaddr + DMA_CONTROL);
 587         return;
 588 }
 589
 590 static void stmmac_dma_stop_tx(unsigned long ioaddr)
 591 {
 592         u32 value = readl(ioaddr + DMA_CONTROL);
 593         value &= ~DMA_CONTROL_ST;
 594         writel(value, ioaddr + DMA_CONTROL);
 595         return;
 596 }
 597
 598 /**
 599  * stmmac_dma_start_rx
 600  * @ioaddr: device I/O address
 601  * Description:  this function starts the DMA rx process.
 602  */
 603 static void stmmac_dma_start_rx(unsigned long ioaddr)
 604 {
 605         u32 value = readl(ioaddr + DMA_CONTROL);
 606         value |= DMA_CONTROL_SR;
 607         writel(value, ioaddr + DMA_CONTROL);
 608
 609         return;
 610 }
 611
 612 static void stmmac_dma_stop_rx(unsigned long ioaddr)
 613 {
 614         u32 value = readl(ioaddr + DMA_CONTROL);
 615         value &= ~DMA_CONTROL_SR;
 616         writel(value, ioaddr + DMA_CONTROL);
 617
 618         return;
 619 }
 620
 621 /**
 622  *  stmmac_dma_operation_mode - HW DMA operation mode
 623  *  @priv : pointer to the private device structure.
 624  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 625  *  or Store-And-Forward capability. It also verifies the COE for the
 626  *  transmission in case of Giga ETH.
 627  */
 628 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 629 {
 630         if (!priv->is_gmac) {
 631                 /* MAC 10/100 */
 632                 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc, 0);
 633                 priv->tx_coe = NO_HW_CSUM;
 634         } else {
 635                 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
 636                         priv->mac_type->ops->dma_mode(priv->dev->base_addr,
 637                                                       SF_DMA_MODE, SF_DMA_MODE);
 638                         tc = SF_DMA_MODE;
 639                         priv->tx_coe = HW_CSUM;
 640                 } else {
 641                         /* Checksum computation is performed in software. */
 642                         priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc,
 643                                                       SF_DMA_MODE);
 644                         priv->tx_coe = NO_HW_CSUM;
 645                 }
 646         }
 647         tx_coe = priv->tx_coe;
 648
 649         return;
 650 }
 651
 652 #ifdef STMMAC_DEBUG
 653 /**
 654  * show_tx_process_state
 655  * @status: tx descriptor status field
 656  * Description: it shows the Transmit Process State for CSR5[22:20]
 657  */
 658 static void show_tx_process_state(unsigned int status)
 659 {
 660         unsigned int state;
 661         state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
 662
 663         switch (state) {
 664         case 0:
 665                 pr_info("- TX (Stopped): Reset or Stop command\n");
 666                 break;
 667         case 1:
 668                 pr_info("- TX (Running):Fetching the Tx desc\n");
 669                 break;
 670         case 2:
 671                 pr_info("- TX (Running): Waiting for end of tx\n");
 672                 break;
 673         case 3:
 674                 pr_info("- TX (Running): Reading the data "
 675                        "and queuing the data into the Tx buf\n");
 676                 break;
 677         case 6:
 678                 pr_info("- TX (Suspended): Tx Buff Underflow "
 679                        "or an unavailable Transmit descriptor\n");
 680                 break;
 681         case 7:
 682                 pr_info("- TX (Running): Closing Tx descriptor\n");
 683                 break;
 684         default:
 685                 break;
 686         }
 687         return;
 688 }
 689
 690 /**
 691  * show_rx_process_state
 692  * @status: rx descriptor status field
 693  * Description: it shows the  Receive Process State for CSR5[19:17]
 694  */
 695 static void show_rx_process_state(unsigned int status)
 696 {
 697         unsigned int state;
 698         state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
 699
 700         switch (state) {
 701         case 0:
 702                 pr_info("- RX (Stopped): Reset or Stop command\n");
 703                 break;
 704         case 1:
 705                 pr_info("- RX (Running): Fetching the Rx desc\n");
 706                 break;
 707         case 2:
 708                 pr_info("- RX (Running):Checking for end of pkt\n");
 709                 break;
 710         case 3:
 711                 pr_info("- RX (Running): Waiting for Rx pkt\n");
 712                 break;
 713         case 4:
 714                 pr_info("- RX (Suspended): Unavailable Rx buf\n");
 715                 break;
 716         case 5:
 717                 pr_info("- RX (Running): Closing Rx descriptor\n");
 718                 break;
 719         case 6:
 720                 pr_info("- RX(Running): Flushing the current frame"
 721                        " from the Rx buf\n");
 722                 break;
 723         case 7:
 724                 pr_info("- RX (Running): Queuing the Rx frame"
 725                        " from the Rx buf into memory\n");
 726                 break;
 727         default:
 728                 break;
 729         }
 730         return;
 731 }
 732 #endif
 733
 734 /**
 735  * stmmac_tx:
 736  * @priv: private driver structure
 737  * Description: it reclaims resources after transmission completes.
 738  */
 739 static void stmmac_tx(struct stmmac_priv *priv)
 740 {
 741         unsigned int txsize = priv->dma_tx_size;
 742         unsigned long ioaddr = priv->dev->base_addr;
 743
 744         while (priv->dirty_tx != priv->cur_tx) {
 745                 int last;
 746                 unsigned int entry = priv->dirty_tx % txsize;
 747                 struct sk_buff *skb = priv->tx_skbuff[entry];
 748                 struct dma_desc *p = priv->dma_tx + entry;
 749
 750                 /* Check if the descriptor is owned by the DMA. */
 751                 if (priv->mac_type->ops->get_tx_owner(p))
 752                         break;
 753
 754                 /* Verify tx error by looking at the last segment */
 755                 last = priv->mac_type->ops->get_tx_ls(p);
 756                 if (likely(last)) {
 757                         int tx_error =
 758                             priv->mac_type->ops->tx_status(&priv->dev->stats,
 759                                                            &priv->xstats,
 760                                                            p, ioaddr);
 761                         if (likely(tx_error == 0)) {
 762                                 priv->dev->stats.tx_packets++;
 763                                 priv->xstats.tx_pkt_n++;
 764                         } else
 765                                 priv->dev->stats.tx_errors++;
 766                 }
 767                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 768                         priv->cur_tx, priv->dirty_tx);
 769
 770                 if (likely(p->des2))
 771                         dma_unmap_single(priv->device, p->des2,
 772                                          priv->mac_type->ops->get_tx_len(p),
 773                                          DMA_TO_DEVICE);
 774                 if (unlikely(p->des3))
 775                         p->des3 = 0;
 776
 777                 if (likely(skb != NULL)) {
 778                         /*
 779                          * If there's room in the queue (limit it to size)
 780                          * we add this skb back into the pool,
 781                          * if it's the right size.
 782                          */
 783                         if ((skb_queue_len(&priv->rx_recycle) <
 784                                 priv->dma_rx_size) &&
 785                                 skb_recycle_check(skb, priv->dma_buf_sz))
 786                                 __skb_queue_head(&priv->rx_recycle, skb);
 787                         else
 788                                 dev_kfree_skb(skb);
 789
 790                         priv->tx_skbuff[entry] = NULL;
 791                 }
 792
 793                 priv->mac_type->ops->release_tx_desc(p);
 794
 795                 entry = (++priv->dirty_tx) % txsize;
 796         }
 797         if (unlikely(netif_queue_stopped(priv->dev) &&
 798                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 799                 netif_tx_lock(priv->dev);
 800                 if (netif_queue_stopped(priv->dev) &&
 801                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 802                         TX_DBG("%s: restart transmit\n", __func__);
 803                         netif_wake_queue(priv->dev);
 804                 }
 805                 netif_tx_unlock(priv->dev);
 806         }
 807         return;
 808 }
 809
 810 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
 811 {
 812 #ifdef CONFIG_STMMAC_TIMER
 813         if (likely(priv->tm->enable))
 814                 priv->tm->timer_start(tmrate);
 815         else
 816 #endif
 817         writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
 818 }
 819
 820 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
 821 {
 822 #ifdef CONFIG_STMMAC_TIMER
 823         if (likely(priv->tm->enable))
 824                 priv->tm->timer_stop();
 825         else
 826 #endif
 827         writel(0, priv->dev->base_addr + DMA_INTR_ENA);
 828 }
 829
 830 static int stmmac_has_work(struct stmmac_priv *priv)
 831 {
 832         unsigned int has_work = 0;
 833         int rxret, tx_work = 0;
 834
 835         rxret = priv->mac_type->ops->get_rx_owner(priv->dma_rx +
 836                 (priv->cur_rx % priv->dma_rx_size));
 837
 838         if (priv->dirty_tx != priv->cur_tx)
 839                 tx_work = 1;
 840
 841         if (likely(!rxret || tx_work))
 842                 has_work = 1;
 843
 844         return has_work;
 845 }
 846
 847 static inline void _stmmac_schedule(struct stmmac_priv *priv)
 848 {
 849         if (likely(stmmac_has_work(priv))) {
 850                 stmmac_disable_irq(priv);
 851                 napi_schedule(&priv->napi);
 852         }
 853 }
 854
 855 #ifdef CONFIG_STMMAC_TIMER
 856 void stmmac_schedule(struct net_device *dev)
 857 {
 858         struct stmmac_priv *priv = netdev_priv(dev);
 859
 860         priv->xstats.sched_timer_n++;
 861
 862         _stmmac_schedule(priv);
 863
 864         return;
 865 }
 866
 867 static void stmmac_no_timer_started(unsigned int x)
 868 {;
 869 };
 870
 871 static void stmmac_no_timer_stopped(void)
 872 {;
 873 };
 874 #endif
 875
 876 /**
 877  * stmmac_tx_err:
 878  * @priv: pointer to the private device structure
 879  * Description: it cleans the descriptors and restarts the transmission
 880  * in case of errors.
 881  */
 882 static void stmmac_tx_err(struct stmmac_priv *priv)
 883 {
 884         netif_stop_queue(priv->dev);
 885
 886         stmmac_dma_stop_tx(priv->dev->base_addr);
 887         dma_free_tx_skbufs(priv);
 888         priv->mac_type->ops->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 889         priv->dirty_tx = 0;
 890         priv->cur_tx = 0;
 891         stmmac_dma_start_tx(priv->dev->base_addr);
 892
 893         priv->dev->stats.tx_errors++;
 894         netif_wake_queue(priv->dev);
 895
 896         return;
 897 }
 898
 899 /**
 900  * stmmac_dma_interrupt - Interrupt handler for the driver
 901  * @dev: net device structure
 902  * Description: Interrupt handler for the driver (DMA).
 903  */
 904 static void stmmac_dma_interrupt(struct net_device *dev)
 905 {
 906         unsigned long ioaddr = dev->base_addr;
 907         struct stmmac_priv *priv = netdev_priv(dev);
 908         /* read the status register (CSR5) */
 909         u32 intr_status = readl(ioaddr + DMA_STATUS);
 910
 911         DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 912
 913 #ifdef STMMAC_DEBUG
 914         /* It displays the DMA transmit process state (CSR5 register) */
 915         if (netif_msg_tx_done(priv))
 916                 show_tx_process_state(intr_status);
 917         if (netif_msg_rx_status(priv))
 918                 show_rx_process_state(intr_status);
 919 #endif
 920         /* ABNORMAL interrupts */
 921         if (unlikely(intr_status & DMA_STATUS_AIS)) {
 922                 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
 923                 if (unlikely(intr_status & DMA_STATUS_UNF)) {
 924                         DBG(intr, INFO, "transmit underflow\n");
 925                         if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 926                                 /* Try to bump up the threshold */
 927                                 tc += 64;
 928                                 priv->mac_type->ops->dma_mode(ioaddr, tc,
 929                                               SF_DMA_MODE);
 930                                 priv->xstats.threshold = tc;
 931                         }
 932                         stmmac_tx_err(priv);
 933                         priv->xstats.tx_undeflow_irq++;
 934                 }
 935                 if (unlikely(intr_status & DMA_STATUS_TJT)) {
 936                         DBG(intr, INFO, "transmit jabber\n");
 937                         priv->xstats.tx_jabber_irq++;
 938                 }
 939                 if (unlikely(intr_status & DMA_STATUS_OVF)) {
 940                         DBG(intr, INFO, "recv overflow\n");
 941                         priv->xstats.rx_overflow_irq++;
 942                 }
 943                 if (unlikely(intr_status & DMA_STATUS_RU)) {
 944                         DBG(intr, INFO, "receive buffer unavailable\n");
 945                         priv->xstats.rx_buf_unav_irq++;
 946                 }
 947                 if (unlikely(intr_status & DMA_STATUS_RPS)) {
 948                         DBG(intr, INFO, "receive process stopped\n");
 949                         priv->xstats.rx_process_stopped_irq++;
 950                 }
 951                 if (unlikely(intr_status & DMA_STATUS_RWT)) {
 952                         DBG(intr, INFO, "receive watchdog\n");
 953                         priv->xstats.rx_watchdog_irq++;
 954                 }
 955                 if (unlikely(intr_status & DMA_STATUS_ETI)) {
 956                         DBG(intr, INFO, "transmit early interrupt\n");
 957                         priv->xstats.tx_early_irq++;
 958                 }
 959                 if (unlikely(intr_status & DMA_STATUS_TPS)) {
 960                         DBG(intr, INFO, "transmit process stopped\n");
 961                         priv->xstats.tx_process_stopped_irq++;
 962                         stmmac_tx_err(priv);
 963                 }
 964                 if (unlikely(intr_status & DMA_STATUS_FBI)) {
 965                         DBG(intr, INFO, "fatal bus error\n");
 966                         priv->xstats.fatal_bus_error_irq++;
 967                         stmmac_tx_err(priv);
 968                 }
 969         }
 970
 971         /* TX/RX NORMAL interrupts */
 972         if (intr_status & DMA_STATUS_NIS) {
 973                 priv->xstats.normal_irq_n++;
 974                 if (likely((intr_status & DMA_STATUS_RI) ||
 975                          (intr_status & (DMA_STATUS_TI))))
 976                                 _stmmac_schedule(priv);
 977         }
 978
 979         /* Optional hardware blocks, interrupts should be disabled */
 980         if (unlikely(intr_status &
 981                      (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
 982                 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
 983
 984         /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
 985         writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
 986
 987         DBG(intr, INFO, "\n\n");
 988
 989         return;
 990 }
 991
 992 /**
 993  *  stmmac_open - open entry point of the driver
 994  *  @dev : pointer to the device structure.
 995  *  Description:
 996  *  This function is the open entry point of the driver.
 997  *  Return value:
 998  *  0 on success and an appropriate (-)ve integer as defined in errno.h
 999  *  file on failure.
1000  */
1001 static int stmmac_open(struct net_device *dev)
1002 {
1003         struct stmmac_priv *priv = netdev_priv(dev);
1004         unsigned long ioaddr = dev->base_addr;
1005         int ret;
1006
1007         /* Check that the MAC address is valid.  If its not, refuse
1008          * to bring the device up. The user must specify an
1009          * address using the following linux command:
1010          *      ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx  */
1011         if (!is_valid_ether_addr(dev->dev_addr)) {
1012                 random_ether_addr(dev->dev_addr);
1013                 pr_warning("%s: generated random MAC address %pM\n", dev->name,
1014                         dev->dev_addr);
1015         }
1016
1017         stmmac_verify_args();
1018
1019         ret = stmmac_init_phy(dev);
1020         if (unlikely(ret)) {
1021                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1022                 return ret;
1023         }
1024
1025         /* Request the IRQ lines */
1026         ret = request_irq(dev->irq, stmmac_interrupt,
1027                           IRQF_SHARED, dev->name, dev);
1028         if (unlikely(ret < 0)) {
1029                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1030                        __func__, dev->irq, ret);
1031                 return ret;
1032         }
1033
1034 #ifdef CONFIG_STMMAC_TIMER
1035         priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
1036         if (unlikely(priv->tm == NULL)) {
1037                 pr_err("%s: ERROR: timer memory alloc failed \n", __func__);
1038                 return -ENOMEM;
1039         }
1040         priv->tm->freq = tmrate;
1041
1042         /* Test if the external timer can be actually used.
1043          * In case of failure continue without timer. */
1044         if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
1045                 pr_warning("stmmaceth: cannot attach the external timer.\n");
1046                 tmrate = 0;
1047                 priv->tm->freq = 0;
1048                 priv->tm->timer_start = stmmac_no_timer_started;
1049                 priv->tm->timer_stop = stmmac_no_timer_stopped;
1050         } else
1051                 priv->tm->enable = 1;
1052 #endif
1053
1054         /* Create and initialize the TX/RX descriptors chains. */
1055         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1056         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1057         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1058         init_dma_desc_rings(dev);
1059
1060         /* DMA initialization and SW reset */
1061         if (unlikely(priv->mac_type->ops->dma_init(ioaddr,
1062                 priv->pbl, priv->dma_tx_phy, priv->dma_rx_phy) < 0)) {
1063
1064                 pr_err("%s: DMA initialization failed\n", __func__);
1065                 return -1;
1066         }
1067
1068         /* Copy the MAC addr into the HW  */
1069         priv->mac_type->ops->set_umac_addr(ioaddr, dev->dev_addr, 0);
1070         /* Initialize the MAC Core */
1071         priv->mac_type->ops->core_init(ioaddr);
1072
1073         priv->shutdown = 0;
1074
1075         /* Initialise the MMC (if present) to disable all interrupts. */
1076         writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
1077         writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
1078
1079         /* Enable the MAC Rx/Tx */
1080         stmmac_mac_enable_rx(ioaddr);
1081         stmmac_mac_enable_tx(ioaddr);
1082
1083         /* Set the HW DMA mode and the COE */
1084         stmmac_dma_operation_mode(priv);
1085
1086         /* Extra statistics */
1087         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1088         priv->xstats.threshold = tc;
1089
1090         /* Start the ball rolling... */
1091         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1092         stmmac_dma_start_tx(ioaddr);
1093         stmmac_dma_start_rx(ioaddr);
1094
1095 #ifdef CONFIG_STMMAC_TIMER
1096         priv->tm->timer_start(tmrate);
1097 #endif
1098         /* Dump DMA/MAC registers */
1099         if (netif_msg_hw(priv)) {
1100                 priv->mac_type->ops->dump_mac_regs(ioaddr);
1101                 priv->mac_type->ops->dump_dma_regs(ioaddr);
1102         }
1103
1104         if (priv->phydev)
1105                 phy_start(priv->phydev);
1106
1107         napi_enable(&priv->napi);
1108         skb_queue_head_init(&priv->rx_recycle);
1109         netif_start_queue(dev);
1110         return 0;
1111 }
1112
1113 /**
1114  *  stmmac_release - close entry point of the driver
1115  *  @dev : device pointer.
1116  *  Description:
1117  *  This is the stop entry point of the driver.
1118  */
1119 static int stmmac_release(struct net_device *dev)
1120 {
1121         struct stmmac_priv *priv = netdev_priv(dev);
1122
1123         /* Stop and disconnect the PHY */
1124         if (priv->phydev) {
1125                 phy_stop(priv->phydev);
1126                 phy_disconnect(priv->phydev);
1127                 priv->phydev = NULL;
1128         }
1129
1130         netif_stop_queue(dev);
1131
1132 #ifdef CONFIG_STMMAC_TIMER
1133         /* Stop and release the timer */
1134         stmmac_close_ext_timer();
1135         if (priv->tm != NULL)
1136                 kfree(priv->tm);
1137 #endif
1138         napi_disable(&priv->napi);
1139         skb_queue_purge(&priv->rx_recycle);
1140
1141         /* Free the IRQ lines */
1142         free_irq(dev->irq, dev);
1143
1144         /* Stop TX/RX DMA and clear the descriptors */
1145         stmmac_dma_stop_tx(dev->base_addr);
1146         stmmac_dma_stop_rx(dev->base_addr);
1147
1148         /* Release and free the Rx/Tx resources */
1149         free_dma_desc_resources(priv);
1150
1151         /* Disable the MAC core */
1152         stmmac_mac_disable_tx(dev->base_addr);
1153         stmmac_mac_disable_rx(dev->base_addr);
1154
1155         netif_carrier_off(dev);
1156
1157         return 0;
1158 }
1159
1160 /*
1161  * To perform emulated hardware segmentation on skb.
1162  */
1163 static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
1164 {
1165         struct sk_buff *segs, *curr_skb;
1166         int gso_segs = skb_shinfo(skb)->gso_segs;
1167
1168         /* Estimate the number of fragments in the worst case */
1169         if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
1170                 netif_stop_queue(priv->dev);
1171                 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
1172                        __func__);
1173                 if (stmmac_tx_avail(priv) < gso_segs)
1174                         return NETDEV_TX_BUSY;
1175
1176                 netif_wake_queue(priv->dev);
1177         }
1178         TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
1179                skb, skb->len);
1180
1181         segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
1182         if (unlikely(IS_ERR(segs)))
1183                 goto sw_tso_end;
1184
1185         do {
1186                 curr_skb = segs;
1187                 segs = segs->next;
1188                 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
1189                        "*next %p\n", curr_skb->len, curr_skb, segs);
1190                 curr_skb->next = NULL;
1191                 stmmac_xmit(curr_skb, priv->dev);
1192         } while (segs);
1193
1194 sw_tso_end:
1195         dev_kfree_skb(skb);
1196
1197         return NETDEV_TX_OK;
1198 }
1199
1200 static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1201                                                struct net_device *dev,
1202                                                int csum_insertion)
1203 {
1204         struct stmmac_priv *priv = netdev_priv(dev);
1205         unsigned int nopaged_len = skb_headlen(skb);
1206         unsigned int txsize = priv->dma_tx_size;
1207         unsigned int entry = priv->cur_tx % txsize;
1208         struct dma_desc *desc = priv->dma_tx + entry;
1209
1210         if (nopaged_len > BUF_SIZE_8KiB) {
1211
1212                 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1213
1214                 desc->des2 = dma_map_single(priv->device, skb->data,
1215                                             BUF_SIZE_8KiB, DMA_TO_DEVICE);
1216                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1217                 priv->mac_type->ops->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1218                                                      csum_insertion);
1219
1220                 entry = (++priv->cur_tx) % txsize;
1221                 desc = priv->dma_tx + entry;
1222
1223                 desc->des2 = dma_map_single(priv->device,
1224                                         skb->data + BUF_SIZE_8KiB,
1225                                         buf2_size, DMA_TO_DEVICE);
1226                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1227                 priv->mac_type->ops->prepare_tx_desc(desc, 0,
1228                                                      buf2_size, csum_insertion);
1229                 priv->mac_type->ops->set_tx_owner(desc);
1230                 priv->tx_skbuff[entry] = NULL;
1231         } else {
1232                 desc->des2 = dma_map_single(priv->device, skb->data,
1233                                         nopaged_len, DMA_TO_DEVICE);
1234                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1235                 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1236                                                      csum_insertion);
1237         }
1238         return entry;
1239 }
1240
1241 /**
1242  *  stmmac_xmit:
1243  *  @skb : the socket buffer
1244  *  @dev : device pointer
1245  *  Description : Tx entry point of the driver.
1246  */
1247 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1248 {
1249         struct stmmac_priv *priv = netdev_priv(dev);
1250         unsigned int txsize = priv->dma_tx_size;
1251         unsigned int entry;
1252         int i, csum_insertion = 0;
1253         int nfrags = skb_shinfo(skb)->nr_frags;
1254         struct dma_desc *desc, *first;
1255
1256         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1257                 if (!netif_queue_stopped(dev)) {
1258                         netif_stop_queue(dev);
1259                         /* This is a hard error, log it. */
1260                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1261                                 __func__);
1262                 }
1263                 return NETDEV_TX_BUSY;
1264         }
1265
1266         entry = priv->cur_tx % txsize;
1267
1268 #ifdef STMMAC_XMIT_DEBUG
1269         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1270                 pr_info("stmmac xmit:\n"
1271                        "\tskb addr %p - len: %d - nopaged_len: %d\n"
1272                        "\tn_frags: %d - ip_summed: %d - %s gso\n",
1273                        skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1274                        !skb_is_gso(skb) ? "isn't" : "is");
1275 #endif
1276
1277         if (unlikely(skb_is_gso(skb)))
1278                 return stmmac_sw_tso(priv, skb);
1279
1280         if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1281                 if (likely(priv->tx_coe == NO_HW_CSUM))
1282                         skb_checksum_help(skb);
1283                 else
1284                         csum_insertion = 1;
1285         }
1286
1287         desc = priv->dma_tx + entry;
1288         first = desc;
1289
1290 #ifdef STMMAC_XMIT_DEBUG
1291         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1292                 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1293                        "\t\tn_frags: %d, ip_summed: %d\n",
1294                        skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1295 #endif
1296         priv->tx_skbuff[entry] = skb;
1297         if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1298                 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1299                 desc = priv->dma_tx + entry;
1300         } else {
1301                 unsigned int nopaged_len = skb_headlen(skb);
1302                 desc->des2 = dma_map_single(priv->device, skb->data,
1303                                         nopaged_len, DMA_TO_DEVICE);
1304                 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len,
1305                                                      csum_insertion);
1306         }
1307
1308         for (i = 0; i < nfrags; i++) {
1309                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1310                 int len = frag->size;
1311
1312                 entry = (++priv->cur_tx) % txsize;
1313                 desc = priv->dma_tx + entry;
1314
1315                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1316                 desc->des2 = dma_map_page(priv->device, frag->page,
1317                                           frag->page_offset,
1318                                           len, DMA_TO_DEVICE);
1319                 priv->tx_skbuff[entry] = NULL;
1320                 priv->mac_type->ops->prepare_tx_desc(desc, 0, len,
1321                                                      csum_insertion);
1322                 priv->mac_type->ops->set_tx_owner(desc);
1323         }
1324
1325         /* Interrupt on completition only for the latest segment */
1326         priv->mac_type->ops->close_tx_desc(desc);
1327
1328 #ifdef CONFIG_STMMAC_TIMER
1329         /* Clean IC while using timer */
1330         if (likely(priv->tm->enable))
1331                 priv->mac_type->ops->clear_tx_ic(desc);
1332 #endif
1333         /* To avoid raise condition */
1334         priv->mac_type->ops->set_tx_owner(first);
1335
1336         priv->cur_tx++;
1337
1338 #ifdef STMMAC_XMIT_DEBUG
1339         if (netif_msg_pktdata(priv)) {
1340                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1341                        "first=%p, nfrags=%d\n",
1342                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1343                        entry, first, nfrags);
1344                 display_ring(priv->dma_tx, txsize);
1345                 pr_info(">>> frame to be transmitted: ");
1346                 print_pkt(skb->data, skb->len);
1347         }
1348 #endif
1349         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1350                 TX_DBG("%s: stop transmitted packets\n", __func__);
1351                 netif_stop_queue(dev);
1352         }
1353
1354         dev->stats.tx_bytes += skb->len;
1355
1356         /* CSR1 enables the transmit DMA to check for new descriptor */
1357         writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1358
1359         return NETDEV_TX_OK;
1360 }
1361
1362 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1363 {
1364         unsigned int rxsize = priv->dma_rx_size;
1365         int bfsize = priv->dma_buf_sz;
1366         struct dma_desc *p = priv->dma_rx;
1367
1368         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1369                 unsigned int entry = priv->dirty_rx % rxsize;
1370                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1371                         struct sk_buff *skb;
1372
1373                         skb = __skb_dequeue(&priv->rx_recycle);
1374                         if (skb == NULL)
1375                                 skb = netdev_alloc_skb_ip_align(priv->dev,
1376                                                                 bfsize);
1377
1378                         if (unlikely(skb == NULL))
1379                                 break;
1380
1381                         priv->rx_skbuff[entry] = skb;
1382                         priv->rx_skbuff_dma[entry] =
1383                             dma_map_single(priv->device, skb->data, bfsize,
1384                                            DMA_FROM_DEVICE);
1385
1386                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1387                         if (unlikely(priv->is_gmac)) {
1388                                 if (bfsize >= BUF_SIZE_8KiB)
1389                                         (p + entry)->des3 =
1390                                             (p + entry)->des2 + BUF_SIZE_8KiB;
1391                         }
1392                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1393                 }
1394                 priv->mac_type->ops->set_rx_owner(p + entry);
1395         }
1396         return;
1397 }
1398
1399 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1400 {
1401         unsigned int rxsize = priv->dma_rx_size;
1402         unsigned int entry = priv->cur_rx % rxsize;
1403         unsigned int next_entry;
1404         unsigned int count = 0;
1405         struct dma_desc *p = priv->dma_rx + entry;
1406         struct dma_desc *p_next;
1407
1408 #ifdef STMMAC_RX_DEBUG
1409         if (netif_msg_hw(priv)) {
1410                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1411                 display_ring(priv->dma_rx, rxsize);
1412         }
1413 #endif
1414         count = 0;
1415         while (!priv->mac_type->ops->get_rx_owner(p)) {
1416                 int status;
1417
1418                 if (count >= limit)
1419                         break;
1420
1421                 count++;
1422
1423                 next_entry = (++priv->cur_rx) % rxsize;
1424                 p_next = priv->dma_rx + next_entry;
1425                 prefetch(p_next);
1426
1427                 /* read the status of the incoming frame */
1428                 status = (priv->mac_type->ops->rx_status(&priv->dev->stats,
1429                                                          &priv->xstats, p));
1430                 if (unlikely(status == discard_frame))
1431                         priv->dev->stats.rx_errors++;
1432                 else {
1433                         struct sk_buff *skb;
1434                         /* Length should omit the CRC */
1435                         int frame_len =
1436                             priv->mac_type->ops->get_rx_frame_len(p) - 4;
1437
1438 #ifdef STMMAC_RX_DEBUG
1439                         if (frame_len > ETH_FRAME_LEN)
1440                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1441                                         frame_len, status);
1442
1443                         if (netif_msg_hw(priv))
1444                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1445                                         p, entry, p->des2);
1446 #endif
1447                         skb = priv->rx_skbuff[entry];
1448                         if (unlikely(!skb)) {
1449                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1450                                         priv->dev->name);
1451                                 priv->dev->stats.rx_dropped++;
1452                                 break;
1453                         }
1454                         prefetch(skb->data - NET_IP_ALIGN);
1455                         priv->rx_skbuff[entry] = NULL;
1456
1457                         skb_put(skb, frame_len);
1458                         dma_unmap_single(priv->device,
1459                                          priv->rx_skbuff_dma[entry],
1460                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1461 #ifdef STMMAC_RX_DEBUG
1462                         if (netif_msg_pktdata(priv)) {
1463                                 pr_info(" frame received (%dbytes)", frame_len);
1464                                 print_pkt(skb->data, frame_len);
1465                         }
1466 #endif
1467                         skb->protocol = eth_type_trans(skb, priv->dev);
1468
1469                         if (unlikely(status == csum_none)) {
1470                                 /* always for the old mac 10/100 */
1471                                 skb->ip_summed = CHECKSUM_NONE;
1472                                 netif_receive_skb(skb);
1473                         } else {
1474                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1475                                 napi_gro_receive(&priv->napi, skb);
1476                         }
1477
1478                         priv->dev->stats.rx_packets++;
1479                         priv->dev->stats.rx_bytes += frame_len;
1480                         priv->dev->last_rx = jiffies;
1481                 }
1482                 entry = next_entry;
1483                 p = p_next;     /* use prefetched values */
1484         }
1485
1486         stmmac_rx_refill(priv);
1487
1488         priv->xstats.rx_pkt_n += count;
1489
1490         return count;
1491 }
1492
1493 /**
1494  *  stmmac_poll - stmmac poll method (NAPI)
1495  *  @napi : pointer to the napi structure.
1496  *  @budget : maximum number of packets that the current CPU can receive from
1497  *            all interfaces.
1498  *  Description :
1499  *   This function implements the the reception process.
1500  *   Also it runs the TX completion thread
1501  */
1502 static int stmmac_poll(struct napi_struct *napi, int budget)
1503 {
1504         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1505         int work_done = 0;
1506
1507         priv->xstats.poll_n++;
1508         stmmac_tx(priv);
1509         work_done = stmmac_rx(priv, budget);
1510
1511         if (work_done < budget) {
1512                 napi_complete(napi);
1513                 stmmac_enable_irq(priv);
1514         }
1515         return work_done;
1516 }
1517
1518 /**
1519  *  stmmac_tx_timeout
1520  *  @dev : Pointer to net device structure
1521  *  Description: this function is called when a packet transmission fails to
1522  *   complete within a reasonable tmrate. The driver will mark the error in the
1523  *   netdev structure and arrange for the device to be reset to a sane state
1524  *   in order to transmit a new packet.
1525  */
1526 static void stmmac_tx_timeout(struct net_device *dev)
1527 {
1528         struct stmmac_priv *priv = netdev_priv(dev);
1529
1530         /* Clear Tx resources and restart transmitting again */
1531         stmmac_tx_err(priv);
1532         return;
1533 }
1534
1535 /* Configuration changes (passed on by ifconfig) */
1536 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1537 {
1538         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1539                 return -EBUSY;
1540
1541         /* Don't allow changing the I/O address */
1542         if (map->base_addr != dev->base_addr) {
1543                 pr_warning("%s: can't change I/O address\n", dev->name);
1544                 return -EOPNOTSUPP;
1545         }
1546
1547         /* Don't allow changing the IRQ */
1548         if (map->irq != dev->irq) {
1549                 pr_warning("%s: can't change IRQ number %d\n",
1550                        dev->name, dev->irq);
1551                 return -EOPNOTSUPP;
1552         }
1553
1554         /* ignore other fields */
1555         return 0;
1556 }
1557
1558 /**
1559  *  stmmac_multicast_list - entry point for multicast addressing
1560  *  @dev : pointer to the device structure
1561  *  Description:
1562  *  This function is a driver entry point which gets called by the kernel
1563  *  whenever multicast addresses must be enabled/disabled.
1564  *  Return value:
1565  *  void.
1566  */
1567 static void stmmac_multicast_list(struct net_device *dev)
1568 {
1569         struct stmmac_priv *priv = netdev_priv(dev);
1570
1571         spin_lock(&priv->lock);
1572         priv->mac_type->ops->set_filter(dev);
1573         spin_unlock(&priv->lock);
1574         return;
1575 }
1576
1577 /**
1578  *  stmmac_change_mtu - entry point to change MTU size for the device.
1579  *  @dev : device pointer.
1580  *  @new_mtu : the new MTU size for the device.
1581  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1582  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1583  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1584  *  Return value:
1585  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1586  *  file on failure.
1587  */
1588 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1589 {
1590         struct stmmac_priv *priv = netdev_priv(dev);
1591         int max_mtu;
1592
1593         if (netif_running(dev)) {
1594                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1595                 return -EBUSY;
1596         }
1597
1598         if (priv->is_gmac)
1599                 max_mtu = JUMBO_LEN;
1600         else
1601                 max_mtu = ETH_DATA_LEN;
1602
1603         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1604                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1605                 return -EINVAL;
1606         }
1607
1608         dev->mtu = new_mtu;
1609
1610         return 0;
1611 }
1612
1613 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1614 {
1615         struct net_device *dev = (struct net_device *)dev_id;
1616         struct stmmac_priv *priv = netdev_priv(dev);
1617
1618         if (unlikely(!dev)) {
1619                 pr_err("%s: invalid dev pointer\n", __func__);
1620                 return IRQ_NONE;
1621         }
1622
1623         if (priv->is_gmac) {
1624                 unsigned long ioaddr = dev->base_addr;
1625                 /* To handle GMAC own interrupts */
1626                 priv->mac_type->ops->host_irq_status(ioaddr);
1627         }
1628         stmmac_dma_interrupt(dev);
1629
1630         return IRQ_HANDLED;
1631 }
1632
1633 #ifdef CONFIG_NET_POLL_CONTROLLER
1634 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1635  * to allow network I/O with interrupts disabled. */
1636 static void stmmac_poll_controller(struct net_device *dev)
1637 {
1638         disable_irq(dev->irq);
1639         stmmac_interrupt(dev->irq, dev);
1640         enable_irq(dev->irq);
1641 }
1642 #endif
1643
1644 /**
1645  *  stmmac_ioctl - Entry point for the Ioctl
1646  *  @dev: Device pointer.
1647  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1648  *  a proprietary structure used to pass information to the driver.
1649  *  @cmd: IOCTL command
1650  *  Description:
1651  *  Currently there are no special functionality supported in IOCTL, just the
1652  *  phy_mii_ioctl(...) can be invoked.
1653  */
1654 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1655 {
1656         struct stmmac_priv *priv = netdev_priv(dev);
1657         int ret = -EOPNOTSUPP;
1658
1659         if (!netif_running(dev))
1660                 return -EINVAL;
1661
1662         switch (cmd) {
1663         case SIOCGMIIPHY:
1664         case SIOCGMIIREG:
1665         case SIOCSMIIREG:
1666                 if (!priv->phydev)
1667                         return -EINVAL;
1668
1669                 spin_lock(&priv->lock);
1670                 ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1671                 spin_unlock(&priv->lock);
1672         default:
1673                 break;
1674         }
1675         return ret;
1676 }
1677
1678 #ifdef STMMAC_VLAN_TAG_USED
1679 static void stmmac_vlan_rx_register(struct net_device *dev,
1680                                     struct vlan_group *grp)
1681 {
1682         struct stmmac_priv *priv = netdev_priv(dev);
1683
1684         DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1685
1686         spin_lock(&priv->lock);
1687         priv->vlgrp = grp;
1688         spin_unlock(&priv->lock);
1689
1690         return;
1691 }
1692 #endif
1693
1694 static const struct net_device_ops stmmac_netdev_ops = {
1695         .ndo_open = stmmac_open,
1696         .ndo_start_xmit = stmmac_xmit,
1697         .ndo_stop = stmmac_release,
1698         .ndo_change_mtu = stmmac_change_mtu,
1699         .ndo_set_multicast_list = stmmac_multicast_list,
1700         .ndo_tx_timeout = stmmac_tx_timeout,
1701         .ndo_do_ioctl = stmmac_ioctl,
1702         .ndo_set_config = stmmac_config,
1703 #ifdef STMMAC_VLAN_TAG_USED
1704         .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1705 #endif
1706 #ifdef CONFIG_NET_POLL_CONTROLLER
1707         .ndo_poll_controller = stmmac_poll_controller,
1708 #endif
1709         .ndo_set_mac_address = eth_mac_addr,
1710 };
1711
1712 /**
1713  * stmmac_probe - Initialization of the adapter .
1714  * @dev : device pointer
1715  * Description: The function initializes the network device structure for
1716  * the STMMAC driver. It also calls the low level routines
1717  * in order to init the HW (i.e. the DMA engine)
1718  */
1719 static int stmmac_probe(struct net_device *dev)
1720 {
1721         int ret = 0;
1722         struct stmmac_priv *priv = netdev_priv(dev);
1723
1724         ether_setup(dev);
1725
1726         dev->netdev_ops = &stmmac_netdev_ops;
1727         stmmac_set_ethtool_ops(dev);
1728
1729         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1730         dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1731 #ifdef STMMAC_VLAN_TAG_USED
1732         /* Both mac100 and gmac support receive VLAN tag detection */
1733         dev->features |= NETIF_F_HW_VLAN_RX;
1734 #endif
1735         priv->msg_enable = netif_msg_init(debug, default_msg_level);
1736
1737         if (priv->is_gmac)
1738                 priv->rx_csum = 1;
1739
1740         if (flow_ctrl)
1741                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
1742
1743         priv->pause = pause;
1744         netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1745
1746         /* Get the MAC address */
1747         priv->mac_type->ops->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
1748
1749         if (!is_valid_ether_addr(dev->dev_addr))
1750                 pr_warning("\tno valid MAC address;"
1751                         "please, use ifconfig or nwhwconfig!\n");
1752
1753         ret = register_netdev(dev);
1754         if (ret) {
1755                 pr_err("%s: ERROR %i registering the device\n",
1756                        __func__, ret);
1757                 return -ENODEV;
1758         }
1759
1760         DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1761             dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1762             (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1763
1764         spin_lock_init(&priv->lock);
1765
1766         return ret;
1767 }
1768
1769 /**
1770  * stmmac_mac_device_setup
1771  * @dev : device pointer
1772  * Description: select and initialise the mac device (mac100 or Gmac).
1773  */
1774 static int stmmac_mac_device_setup(struct net_device *dev)
1775 {
1776         struct stmmac_priv *priv = netdev_priv(dev);
1777         unsigned long ioaddr = dev->base_addr;
1778
1779         struct mac_device_info *device;
1780
1781         if (priv->is_gmac)
1782                 device = gmac_setup(ioaddr);
1783         else
1784                 device = mac100_setup(ioaddr);
1785
1786         if (!device)
1787                 return -ENOMEM;
1788
1789         priv->mac_type = device;
1790
1791         priv->wolenabled = priv->mac_type->hw.pmt;      /* PMT supported */
1792         if (priv->wolenabled == PMT_SUPPORTED)
1793                 priv->wolopts = WAKE_MAGIC;             /* Magic Frame */
1794
1795         return 0;
1796 }
1797
1798 static int stmmacphy_dvr_probe(struct platform_device *pdev)
1799 {
1800         struct plat_stmmacphy_data *plat_dat;
1801         plat_dat = (struct plat_stmmacphy_data *)((pdev->dev).platform_data);
1802
1803         pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1804                plat_dat->bus_id);
1805
1806         return 0;
1807 }
1808
1809 static int stmmacphy_dvr_remove(struct platform_device *pdev)
1810 {
1811         return 0;
1812 }
1813
1814 static struct platform_driver stmmacphy_driver = {
1815         .driver = {
1816                    .name = PHY_RESOURCE_NAME,
1817                    },
1818         .probe = stmmacphy_dvr_probe,
1819         .remove = stmmacphy_dvr_remove,
1820 };
1821
1822 /**
1823  * stmmac_associate_phy
1824  * @dev: pointer to device structure
1825  * @data: points to the private structure.
1826  * Description: Scans through all the PHYs we have registered and checks if
1827  * any are associated with our MAC.  If so, then just fill in
1828  * the blanks in our local context structure
1829  */
1830 static int stmmac_associate_phy(struct device *dev, void *data)
1831 {
1832         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1833         struct plat_stmmacphy_data *plat_dat;
1834
1835         plat_dat = (struct plat_stmmacphy_data *)(dev->platform_data);
1836
1837         DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1838                 plat_dat->bus_id);
1839
1840         /* Check that this phy is for the MAC being initialised */
1841         if (priv->bus_id != plat_dat->bus_id)
1842                 return 0;
1843
1844         /* OK, this PHY is connected to the MAC.
1845            Go ahead and get the parameters */
1846         DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1847         priv->phy_irq =
1848             platform_get_irq_byname(to_platform_device(dev), "phyirq");
1849         DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1850             plat_dat->bus_id, priv->phy_irq);
1851
1852         /* Override with kernel parameters if supplied XXX CRS XXX
1853          * this needs to have multiple instances */
1854         if ((phyaddr >= 0) && (phyaddr <= 31))
1855                 plat_dat->phy_addr = phyaddr;
1856
1857         priv->phy_addr = plat_dat->phy_addr;
1858         priv->phy_mask = plat_dat->phy_mask;
1859         priv->phy_interface = plat_dat->interface;
1860         priv->phy_reset = plat_dat->phy_reset;
1861
1862         DBG(probe, DEBUG, "%s: exiting\n", __func__);
1863         return 1;       /* forces exit of driver_for_each_device() */
1864 }
1865
1866 /**
1867  * stmmac_dvr_probe
1868  * @pdev: platform device pointer
1869  * Description: the driver is initialized through platform_device.
1870  */
1871 static int stmmac_dvr_probe(struct platform_device *pdev)
1872 {
1873         int ret = 0;
1874         struct resource *res;
1875         unsigned int *addr = NULL;
1876         struct net_device *ndev = NULL;
1877         struct stmmac_priv *priv;
1878         struct plat_stmmacenet_data *plat_dat;
1879
1880         pr_info("STMMAC driver:\n\tplatform registration... ");
1881         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882         if (!res) {
1883                 ret = -ENODEV;
1884                 goto out;
1885         }
1886         pr_info("done!\n");
1887
1888         if (!request_mem_region(res->start, (res->end - res->start),
1889                                 pdev->name)) {
1890                 pr_err("%s: ERROR: memory allocation failed"
1891                        "cannot get the I/O addr 0x%x\n",
1892                        __func__, (unsigned int)res->start);
1893                 ret = -EBUSY;
1894                 goto out;
1895         }
1896
1897         addr = ioremap(res->start, (res->end - res->start));
1898         if (!addr) {
1899                 pr_err("%s: ERROR: memory mapping failed \n", __func__);
1900                 ret = -ENOMEM;
1901                 goto out;
1902         }
1903
1904         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1905         if (!ndev) {
1906                 pr_err("%s: ERROR: allocating the device\n", __func__);
1907                 ret = -ENOMEM;
1908                 goto out;
1909         }
1910
1911         SET_NETDEV_DEV(ndev, &pdev->dev);
1912
1913         /* Get the MAC information */
1914         ndev->irq = platform_get_irq_byname(pdev, "macirq");
1915         if (ndev->irq == -ENXIO) {
1916                 pr_err("%s: ERROR: MAC IRQ configuration "
1917                        "information not found\n", __func__);
1918                 ret = -ENODEV;
1919                 goto out;
1920         }
1921
1922         priv = netdev_priv(ndev);
1923         priv->device = &(pdev->dev);
1924         priv->dev = ndev;
1925         plat_dat = (struct plat_stmmacenet_data *)((pdev->dev).platform_data);
1926         priv->bus_id = plat_dat->bus_id;
1927         priv->pbl = plat_dat->pbl;      /* TLI */
1928         priv->is_gmac = plat_dat->has_gmac;     /* GMAC is on board */
1929
1930         platform_set_drvdata(pdev, ndev);
1931
1932         /* Set the I/O base addr */
1933         ndev->base_addr = (unsigned long)addr;
1934
1935         /* MAC HW revice detection */
1936         ret = stmmac_mac_device_setup(ndev);
1937         if (ret < 0)
1938                 goto out;
1939
1940         /* Network Device Registration */
1941         ret = stmmac_probe(ndev);
1942         if (ret < 0)
1943                 goto out;
1944
1945         /* associate a PHY - it is provided by another platform bus */
1946         if (!driver_for_each_device
1947             (&(stmmacphy_driver.driver), NULL, (void *)priv,
1948              stmmac_associate_phy)) {
1949                 pr_err("No PHY device is associated with this MAC!\n");
1950                 ret = -ENODEV;
1951                 goto out;
1952         }
1953
1954         priv->fix_mac_speed = plat_dat->fix_mac_speed;
1955         priv->bsp_priv = plat_dat->bsp_priv;
1956
1957         pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1958                "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1959                pdev->id, ndev->irq, (unsigned int)addr);
1960
1961         /* MDIO bus Registration */
1962         pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1963         ret = stmmac_mdio_register(ndev);
1964         if (ret < 0)
1965                 goto out;
1966         pr_debug("registered!\n");
1967
1968 out:
1969         if (ret < 0) {
1970                 platform_set_drvdata(pdev, NULL);
1971                 release_mem_region(res->start, (res->end - res->start));
1972                 if (addr != NULL)
1973                         iounmap(addr);
1974         }
1975
1976         return ret;
1977 }
1978
1979 /**
1980  * stmmac_dvr_remove
1981  * @pdev: platform device pointer
1982  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1983  * changes the link status, releases the DMA descriptor rings,
1984  * unregisters the MDIO bus and unmaps the allocated memory.
1985  */
1986 static int stmmac_dvr_remove(struct platform_device *pdev)
1987 {
1988         struct net_device *ndev = platform_get_drvdata(pdev);
1989         struct resource *res;
1990
1991         pr_info("%s:\n\tremoving driver", __func__);
1992
1993         stmmac_dma_stop_rx(ndev->base_addr);
1994         stmmac_dma_stop_tx(ndev->base_addr);
1995
1996         stmmac_mac_disable_rx(ndev->base_addr);
1997         stmmac_mac_disable_tx(ndev->base_addr);
1998
1999         netif_carrier_off(ndev);
2000
2001         stmmac_mdio_unregister(ndev);
2002
2003         platform_set_drvdata(pdev, NULL);
2004         unregister_netdev(ndev);
2005
2006         iounmap((void *)ndev->base_addr);
2007         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2008         release_mem_region(res->start, (res->end - res->start));
2009
2010         free_netdev(ndev);
2011
2012         return 0;
2013 }
2014
2015 #ifdef CONFIG_PM
2016 static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2017 {
2018         struct net_device *dev = platform_get_drvdata(pdev);
2019         struct stmmac_priv *priv = netdev_priv(dev);
2020         int dis_ic = 0;
2021
2022         if (!dev || !netif_running(dev))
2023                 return 0;
2024
2025         spin_lock(&priv->lock);
2026
2027         if (state.event == PM_EVENT_SUSPEND) {
2028                 netif_device_detach(dev);
2029                 netif_stop_queue(dev);
2030                 if (priv->phydev)
2031                         phy_stop(priv->phydev);
2032
2033 #ifdef CONFIG_STMMAC_TIMER
2034                 priv->tm->timer_stop();
2035                 if (likely(priv->tm->enable))
2036                         dis_ic = 1;
2037 #endif
2038                 napi_disable(&priv->napi);
2039
2040                 /* Stop TX/RX DMA */
2041                 stmmac_dma_stop_tx(dev->base_addr);
2042                 stmmac_dma_stop_rx(dev->base_addr);
2043                 /* Clear the Rx/Tx descriptors */
2044                 priv->mac_type->ops->init_rx_desc(priv->dma_rx,
2045                                                   priv->dma_rx_size, dis_ic);
2046                 priv->mac_type->ops->init_tx_desc(priv->dma_tx,
2047                                                   priv->dma_tx_size);
2048
2049                 stmmac_mac_disable_tx(dev->base_addr);
2050
2051                 if (device_may_wakeup(&(pdev->dev))) {
2052                         /* Enable Power down mode by programming the PMT regs */
2053                         if (priv->wolenabled == PMT_SUPPORTED)
2054                                 priv->mac_type->ops->pmt(dev->base_addr,
2055                                                          priv->wolopts);
2056                 } else {
2057                         stmmac_mac_disable_rx(dev->base_addr);
2058                 }
2059         } else {
2060                 priv->shutdown = 1;
2061                 /* Although this can appear slightly redundant it actually
2062                  * makes fast the standby operation and guarantees the driver
2063                  * working if hibernation is on media. */
2064                 stmmac_release(dev);
2065         }
2066
2067         spin_unlock(&priv->lock);
2068         return 0;
2069 }
2070
2071 static int stmmac_resume(struct platform_device *pdev)
2072 {
2073         struct net_device *dev = platform_get_drvdata(pdev);
2074         struct stmmac_priv *priv = netdev_priv(dev);
2075         unsigned long ioaddr = dev->base_addr;
2076
2077         if (!netif_running(dev))
2078                 return 0;
2079
2080         spin_lock(&priv->lock);
2081
2082         if (priv->shutdown) {
2083                 /* Re-open the interface and re-init the MAC/DMA
2084                    and the rings. */
2085                 stmmac_open(dev);
2086                 goto out_resume;
2087         }
2088
2089         /* Power Down bit, into the PM register, is cleared
2090          * automatically as soon as a magic packet or a Wake-up frame
2091          * is received. Anyway, it's better to manually clear
2092          * this bit because it can generate problems while resuming
2093          * from another devices (e.g. serial console). */
2094         if (device_may_wakeup(&(pdev->dev)))
2095                 if (priv->wolenabled == PMT_SUPPORTED)
2096                         priv->mac_type->ops->pmt(dev->base_addr, 0);
2097
2098         netif_device_attach(dev);
2099
2100         /* Enable the MAC and DMA */
2101         stmmac_mac_enable_rx(ioaddr);
2102         stmmac_mac_enable_tx(ioaddr);
2103         stmmac_dma_start_tx(ioaddr);
2104         stmmac_dma_start_rx(ioaddr);
2105
2106 #ifdef CONFIG_STMMAC_TIMER
2107         priv->tm->timer_start(tmrate);
2108 #endif
2109         napi_enable(&priv->napi);
2110
2111         if (priv->phydev)
2112                 phy_start(priv->phydev);
2113
2114         netif_start_queue(dev);
2115
2116 out_resume:
2117         spin_unlock(&priv->lock);
2118         return 0;
2119 }
2120 #endif
2121
2122 static struct platform_driver stmmac_driver = {
2123         .driver = {
2124                    .name = STMMAC_RESOURCE_NAME,
2125                    },
2126         .probe = stmmac_dvr_probe,
2127         .remove = stmmac_dvr_remove,
2128 #ifdef CONFIG_PM
2129         .suspend = stmmac_suspend,
2130         .resume = stmmac_resume,
2131 #endif
2132
2133 };
2134
2135 /**
2136  * stmmac_init_module - Entry point for the driver
2137  * Description: This function is the entry point for the driver.
2138  */
2139 static int __init stmmac_init_module(void)
2140 {
2141         int ret;
2142
2143         if (platform_driver_register(&stmmacphy_driver)) {
2144                 pr_err("No PHY devices registered!\n");
2145                 return -ENODEV;
2146         }
2147
2148         ret = platform_driver_register(&stmmac_driver);
2149         return ret;
2150 }
2151
2152 /**
2153  * stmmac_cleanup_module - Cleanup routine for the driver
2154  * Description: This function is the cleanup routine for the driver.
2155  */
2156 static void __exit stmmac_cleanup_module(void)
2157 {
2158         platform_driver_unregister(&stmmacphy_driver);
2159         platform_driver_unregister(&stmmac_driver);
2160 }
2161
2162 #ifndef MODULE
2163 static int __init stmmac_cmdline_opt(char *str)
2164 {
2165         char *opt;
2166
2167         if (!str || !*str)
2168                 return -EINVAL;
2169         while ((opt = strsep(&str, ",")) != NULL) {
2170                 if (!strncmp(opt, "debug:", 6))
2171                         strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
2172                 else if (!strncmp(opt, "phyaddr:", 8))
2173                         strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
2174                 else if (!strncmp(opt, "dma_txsize:", 11))
2175                         strict_strtoul(opt + 11, 0,
2176                                        (unsigned long *)&dma_txsize);
2177                 else if (!strncmp(opt, "dma_rxsize:", 11))
2178                         strict_strtoul(opt + 11, 0,
2179                                        (unsigned long *)&dma_rxsize);
2180                 else if (!strncmp(opt, "buf_sz:", 7))
2181                         strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
2182                 else if (!strncmp(opt, "tc:", 3))
2183                         strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
2184                 else if (!strncmp(opt, "tx_coe:", 7))
2185                         strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
2186                 else if (!strncmp(opt, "watchdog:", 9))
2187                         strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
2188                 else if (!strncmp(opt, "flow_ctrl:", 10))
2189                         strict_strtoul(opt + 10, 0,
2190                                        (unsigned long *)&flow_ctrl);
2191                 else if (!strncmp(opt, "pause:", 6))
2192                         strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
2193 #ifdef CONFIG_STMMAC_TIMER
2194                 else if (!strncmp(opt, "tmrate:", 7))
2195                         strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
2196 #endif
2197         }
2198         return 0;
2199 }
2200
2201 __setup("stmmaceth=", stmmac_cmdline_opt);
2202 #endif
2203
2204 module_init(stmmac_init_module);
2205 module_exit(stmmac_cleanup_module);
2206
2207 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2208 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2209 MODULE_LICENSE("GPL");