2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
23 #include <asm/asmmacro.h>
25 #include <asm/kregs.h>
26 #include <asm/mmu_context.h>
27 #include <asm/asm-offsets.h>
29 #include <asm/paravirt.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/system.h>
34 #include <asm/mca_asm.h>
35 #include <linux/init.h>
36 #include <linux/linkage.h>
38 #ifdef CONFIG_HOTPLUG_CPU
39 #define SAL_PSR_BITS_TO_SET \
40 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
42 #define SAVE_FROM_REG(src, ptr, dest) \
46 #define RESTORE_REG(reg, ptr, _tmp) \
47 ld8 _tmp=[ptr],0x08;; \
50 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
51 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
54 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
58 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
59 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
61 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
63 br.cloop.sptk.many _lbl
65 #define SAVE_ONE_RR(num, _reg, _tmp) \
66 movl _tmp=(num<<61);; \
69 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
70 SAVE_ONE_RR(0,_r0, _tmp);; \
71 SAVE_ONE_RR(1,_r1, _tmp);; \
72 SAVE_ONE_RR(2,_r2, _tmp);; \
73 SAVE_ONE_RR(3,_r3, _tmp);; \
74 SAVE_ONE_RR(4,_r4, _tmp);; \
75 SAVE_ONE_RR(5,_r5, _tmp);; \
76 SAVE_ONE_RR(6,_r6, _tmp);; \
77 SAVE_ONE_RR(7,_r7, _tmp);;
79 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
89 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
93 dep.z _idx2=_idx1,61,3;; \
95 mov rr[_idx2]=_tmp;; \
98 br.cloop.sptk.few RestRR
100 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
101 movl reg1=sal_state_for_booting_cpu;; \
105 * Adjust region registers saved before starting to save
106 * break regs and rest of the states that need to be preserved.
108 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
109 SAVE_FROM_REG(b0,_reg1,_reg2);; \
110 SAVE_FROM_REG(b1,_reg1,_reg2);; \
111 SAVE_FROM_REG(b2,_reg1,_reg2);; \
112 SAVE_FROM_REG(b3,_reg1,_reg2);; \
113 SAVE_FROM_REG(b4,_reg1,_reg2);; \
114 SAVE_FROM_REG(b5,_reg1,_reg2);; \
115 st8 [_reg1]=r1,0x08;; \
116 st8 [_reg1]=r12,0x08;; \
117 st8 [_reg1]=r13,0x08;; \
118 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
121 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
122 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
129 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
130 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
131 st8 [_reg1]=r4,0x08;; \
132 st8 [_reg1]=r5,0x08;; \
133 st8 [_reg1]=r6,0x08;; \
134 st8 [_reg1]=r7,0x08;; \
135 st8 [_reg1]=_pred,0x08;; \
136 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
137 stf.spill.nta [_reg1]=f2,16;; \
138 stf.spill.nta [_reg1]=f3,16;; \
139 stf.spill.nta [_reg1]=f4,16;; \
140 stf.spill.nta [_reg1]=f5,16;; \
141 stf.spill.nta [_reg1]=f16,16;; \
142 stf.spill.nta [_reg1]=f17,16;; \
143 stf.spill.nta [_reg1]=f18,16;; \
144 stf.spill.nta [_reg1]=f19,16;; \
145 stf.spill.nta [_reg1]=f20,16;; \
146 stf.spill.nta [_reg1]=f21,16;; \
147 stf.spill.nta [_reg1]=f22,16;; \
148 stf.spill.nta [_reg1]=f23,16;; \
149 stf.spill.nta [_reg1]=f24,16;; \
150 stf.spill.nta [_reg1]=f25,16;; \
151 stf.spill.nta [_reg1]=f26,16;; \
152 stf.spill.nta [_reg1]=f27,16;; \
153 stf.spill.nta [_reg1]=f28,16;; \
154 stf.spill.nta [_reg1]=f29,16;; \
155 stf.spill.nta [_reg1]=f30,16;; \
156 stf.spill.nta [_reg1]=f31,16;;
159 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
160 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
161 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
162 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
165 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
166 movl _tmp1=(num << 61);; \
167 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
172 .global empty_zero_page
176 .global swapper_pg_dir
182 stringz "Halting kernel\n"
189 * Start the kernel. When the bootloader passes control to _start(), r28
190 * points to the address of the boot parameter area. Execution reaches
191 * here in physical mode.
196 .save rp, r0 // terminate unwind chain with a NULL rp
204 flushrs // must be first insn in group
209 * Save the region registers, predicate before they get clobbered
211 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
215 * Initialize kernel region registers:
216 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
217 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
218 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
219 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
220 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
221 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
222 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
223 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
224 * We initialize all of them to prevent inadvertently assuming
225 * something about the state of address translation early in boot.
227 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
228 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
229 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
230 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
231 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
232 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
233 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
234 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
236 * Now pin mappings into the TLB for kernel text and data
238 mov r18=KERNEL_TR_PAGE_SHIFT<<2
239 movl r17=KERNEL_START
243 mov r16=IA64_TR_KERNEL
247 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
260 * Switch into virtual mode:
262 #ifdef CONFIG_KDB_HARDWARE_BREAKPOINTS
263 #define IA64_PSR_KDB_FLAGS IA64_PSR_DB
265 #define IA64_PSR_KDB_FLAGS 0
267 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
268 |IA64_PSR_DI|IA64_PSR_AC|IA64_PSR_KDB_FLAGS)
278 1: // now we are in virtual mode
280 SET_AREA_FOR_BOOTING_CPU(r2, r16);
282 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
283 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
286 // set IVT entry point---can't access I/O ports without it
298 #define isAP p2 // are we an Application Processor?
299 #define isBP p3 // are we the Bootstrap Processor?
303 * Find the init_task for the currently booting CPU. At poweron, and in
304 * UP mode, task_for_booting_cpu is NULL.
306 movl r3=task_for_booting_cpu
311 cmp.eq isBP,isAP=r3,r0
316 cmp.eq isBP,isAP=r0,r0
319 tpa r3=r2 // r3 == phys addr of task struct
321 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
323 // load mapping for stack (virtaddr in r2, physaddr in r3)
331 dep r2=-1,r3,61,3 // IMVA of task
334 shr.u r16=r3,IA64_GRANULE_SHIFT
341 mov r19=IA64_TR_CURRENT_STACK
350 // load the "current" pointer (r13) and ar.k6 with the current task
351 mov IA64_KR(CURRENT)=r2 // virtual address
352 mov IA64_KR(CURRENT_STACK)=r16
355 * Reserve space at the top of the stack for "struct pt_regs". Kernel
356 * threads don't store interesting values in that structure, but the space
357 * still needs to be there because time-critical stuff such as the context
358 * switching can be implemented more efficiently (for example, __switch_to()
359 * always sets the psr.dfh bit of the task it is switching to).
362 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
363 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
364 mov ar.rsc=0 // place RSE in enforced lazy mode
366 loadrs // clear the dirty partition
367 movl r19=__phys_per_cpu_start
368 mov r18=PERCPU_PAGE_SIZE
375 movl r20=__cpu0_per_cpu
383 (p7) br.cond.dptk.few 1b
390 .pred.rel.mutex isBP,isAP
391 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
392 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
394 mov ar.bspstore=r2 // establish the new RSE stack
396 mov ar.rsc=0x3 // place RSE in eager mode
398 (isBP) dep r28=-1,r28,61,3 // make address virtual
399 (isBP) movl r2=ia64_boot_param
401 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
403 #ifdef CONFIG_PARAVIRT
405 movl r14=hypervisor_setup_hooks
406 movl r15=hypervisor_type
407 mov r16=num_hypervisor_hooks
411 cmp.ltu p7,p0=r2,r16 // array size check
417 (p7) cmp.ne.unc p7,p0=r9,r0 // no actual branch to NULL
419 (p7) br.call.sptk.many rp=b1
423 default_setup_hook = 0 // Currently nothing needs to be done.
427 .global hypervisor_type
429 data8 PARAVIRT_HYPERVISOR_TYPE_DEFAULT
431 // must have the same order with PARAVIRT_HYPERVISOR_TYPE_xxx
433 hypervisor_setup_hooks:
434 data8 default_setup_hook
436 num_hypervisor_hooks = (. - hypervisor_setup_hooks) / 8
442 (isAP) br.call.sptk.many rp=start_secondary
444 (isAP) br.cond.sptk self
447 // This is executed by the bootstrap processor (bsp) only:
449 #ifdef CONFIG_IA64_FW_EMU
450 // initialize PAL & SAL emulator:
451 br.call.sptk.many rp=sys_fw_init
454 br.call.sptk.many rp=start_kernel
455 .ret2: addl r3=@ltoff(halt_msg),gp
457 alloc r2=ar.pfs,8,0,2,0
460 br.call.sptk.many b0=console_print
463 br.sptk.many self // endless loop
468 GLOBAL_ENTRY(ia64_save_debug_regs)
469 alloc r16=ar.pfs,1,0,0,0
470 mov r20=ar.lc // preserve ar.lc
471 mov ar.lc=IA64_NUM_DBG_REGS-1
473 add r19=IA64_NUM_DBG_REGS*8,in0
476 #ifdef CONFIG_ITANIUM
485 br.cloop.sptk.many 1b
487 mov ar.lc=r20 // restore ar.lc
489 END(ia64_save_debug_regs)
491 GLOBAL_ENTRY(ia64_load_debug_regs)
492 alloc r16=ar.pfs,1,0,0,0
494 mov r20=ar.lc // preserve ar.lc
495 add r19=IA64_NUM_DBG_REGS*8,in0
496 mov ar.lc=IA64_NUM_DBG_REGS-1
499 1: ld8.nta r16=[in0],8
504 #ifdef CONFIG_ITANIUM
506 srlz.d // Errata 132 (NoFix status)
509 br.cloop.sptk.many 1b
511 mov ar.lc=r20 // restore ar.lc
513 END(ia64_load_debug_regs)
515 GLOBAL_ENTRY(__ia64_save_fpu)
516 alloc r2=ar.pfs,1,4,0,0
517 adds loc0=96*16-16,in0
518 adds loc1=96*16-16-128,in0
520 stf.spill.nta [loc0]=f127,-256
521 stf.spill.nta [loc1]=f119,-256
523 stf.spill.nta [loc0]=f111,-256
524 stf.spill.nta [loc1]=f103,-256
526 stf.spill.nta [loc0]=f95,-256
527 stf.spill.nta [loc1]=f87,-256
529 stf.spill.nta [loc0]=f79,-256
530 stf.spill.nta [loc1]=f71,-256
532 stf.spill.nta [loc0]=f63,-256
533 stf.spill.nta [loc1]=f55,-256
534 adds loc2=96*16-32,in0
536 stf.spill.nta [loc0]=f47,-256
537 stf.spill.nta [loc1]=f39,-256
538 adds loc3=96*16-32-128,in0
540 stf.spill.nta [loc2]=f126,-256
541 stf.spill.nta [loc3]=f118,-256
543 stf.spill.nta [loc2]=f110,-256
544 stf.spill.nta [loc3]=f102,-256
546 stf.spill.nta [loc2]=f94,-256
547 stf.spill.nta [loc3]=f86,-256
549 stf.spill.nta [loc2]=f78,-256
550 stf.spill.nta [loc3]=f70,-256
552 stf.spill.nta [loc2]=f62,-256
553 stf.spill.nta [loc3]=f54,-256
554 adds loc0=96*16-48,in0
556 stf.spill.nta [loc2]=f46,-256
557 stf.spill.nta [loc3]=f38,-256
558 adds loc1=96*16-48-128,in0
560 stf.spill.nta [loc0]=f125,-256
561 stf.spill.nta [loc1]=f117,-256
563 stf.spill.nta [loc0]=f109,-256
564 stf.spill.nta [loc1]=f101,-256
566 stf.spill.nta [loc0]=f93,-256
567 stf.spill.nta [loc1]=f85,-256
569 stf.spill.nta [loc0]=f77,-256
570 stf.spill.nta [loc1]=f69,-256
572 stf.spill.nta [loc0]=f61,-256
573 stf.spill.nta [loc1]=f53,-256
574 adds loc2=96*16-64,in0
576 stf.spill.nta [loc0]=f45,-256
577 stf.spill.nta [loc1]=f37,-256
578 adds loc3=96*16-64-128,in0
580 stf.spill.nta [loc2]=f124,-256
581 stf.spill.nta [loc3]=f116,-256
583 stf.spill.nta [loc2]=f108,-256
584 stf.spill.nta [loc3]=f100,-256
586 stf.spill.nta [loc2]=f92,-256
587 stf.spill.nta [loc3]=f84,-256
589 stf.spill.nta [loc2]=f76,-256
590 stf.spill.nta [loc3]=f68,-256
592 stf.spill.nta [loc2]=f60,-256
593 stf.spill.nta [loc3]=f52,-256
594 adds loc0=96*16-80,in0
596 stf.spill.nta [loc2]=f44,-256
597 stf.spill.nta [loc3]=f36,-256
598 adds loc1=96*16-80-128,in0
600 stf.spill.nta [loc0]=f123,-256
601 stf.spill.nta [loc1]=f115,-256
603 stf.spill.nta [loc0]=f107,-256
604 stf.spill.nta [loc1]=f99,-256
606 stf.spill.nta [loc0]=f91,-256
607 stf.spill.nta [loc1]=f83,-256
609 stf.spill.nta [loc0]=f75,-256
610 stf.spill.nta [loc1]=f67,-256
612 stf.spill.nta [loc0]=f59,-256
613 stf.spill.nta [loc1]=f51,-256
614 adds loc2=96*16-96,in0
616 stf.spill.nta [loc0]=f43,-256
617 stf.spill.nta [loc1]=f35,-256
618 adds loc3=96*16-96-128,in0
620 stf.spill.nta [loc2]=f122,-256
621 stf.spill.nta [loc3]=f114,-256
623 stf.spill.nta [loc2]=f106,-256
624 stf.spill.nta [loc3]=f98,-256
626 stf.spill.nta [loc2]=f90,-256
627 stf.spill.nta [loc3]=f82,-256
629 stf.spill.nta [loc2]=f74,-256
630 stf.spill.nta [loc3]=f66,-256
632 stf.spill.nta [loc2]=f58,-256
633 stf.spill.nta [loc3]=f50,-256
634 adds loc0=96*16-112,in0
636 stf.spill.nta [loc2]=f42,-256
637 stf.spill.nta [loc3]=f34,-256
638 adds loc1=96*16-112-128,in0
640 stf.spill.nta [loc0]=f121,-256
641 stf.spill.nta [loc1]=f113,-256
643 stf.spill.nta [loc0]=f105,-256
644 stf.spill.nta [loc1]=f97,-256
646 stf.spill.nta [loc0]=f89,-256
647 stf.spill.nta [loc1]=f81,-256
649 stf.spill.nta [loc0]=f73,-256
650 stf.spill.nta [loc1]=f65,-256
652 stf.spill.nta [loc0]=f57,-256
653 stf.spill.nta [loc1]=f49,-256
654 adds loc2=96*16-128,in0
656 stf.spill.nta [loc0]=f41,-256
657 stf.spill.nta [loc1]=f33,-256
658 adds loc3=96*16-128-128,in0
660 stf.spill.nta [loc2]=f120,-256
661 stf.spill.nta [loc3]=f112,-256
663 stf.spill.nta [loc2]=f104,-256
664 stf.spill.nta [loc3]=f96,-256
666 stf.spill.nta [loc2]=f88,-256
667 stf.spill.nta [loc3]=f80,-256
669 stf.spill.nta [loc2]=f72,-256
670 stf.spill.nta [loc3]=f64,-256
672 stf.spill.nta [loc2]=f56,-256
673 stf.spill.nta [loc3]=f48,-256
675 stf.spill.nta [loc2]=f40
676 stf.spill.nta [loc3]=f32
680 GLOBAL_ENTRY(__ia64_load_fpu)
681 alloc r2=ar.pfs,1,2,0,0
688 ldf.fill.nta f32=[in0],loc0
689 ldf.fill.nta f40=[ r3],loc0
690 ldf.fill.nta f48=[r14],loc0
691 ldf.fill.nta f56=[r15],loc0
693 ldf.fill.nta f64=[in0],loc0
694 ldf.fill.nta f72=[ r3],loc0
695 ldf.fill.nta f80=[r14],loc0
696 ldf.fill.nta f88=[r15],loc0
698 ldf.fill.nta f96=[in0],loc1
699 ldf.fill.nta f104=[ r3],loc1
700 ldf.fill.nta f112=[r14],loc1
701 ldf.fill.nta f120=[r15],loc1
703 ldf.fill.nta f33=[in0],loc0
704 ldf.fill.nta f41=[ r3],loc0
705 ldf.fill.nta f49=[r14],loc0
706 ldf.fill.nta f57=[r15],loc0
708 ldf.fill.nta f65=[in0],loc0
709 ldf.fill.nta f73=[ r3],loc0
710 ldf.fill.nta f81=[r14],loc0
711 ldf.fill.nta f89=[r15],loc0
713 ldf.fill.nta f97=[in0],loc1
714 ldf.fill.nta f105=[ r3],loc1
715 ldf.fill.nta f113=[r14],loc1
716 ldf.fill.nta f121=[r15],loc1
718 ldf.fill.nta f34=[in0],loc0
719 ldf.fill.nta f42=[ r3],loc0
720 ldf.fill.nta f50=[r14],loc0
721 ldf.fill.nta f58=[r15],loc0
723 ldf.fill.nta f66=[in0],loc0
724 ldf.fill.nta f74=[ r3],loc0
725 ldf.fill.nta f82=[r14],loc0
726 ldf.fill.nta f90=[r15],loc0
728 ldf.fill.nta f98=[in0],loc1
729 ldf.fill.nta f106=[ r3],loc1
730 ldf.fill.nta f114=[r14],loc1
731 ldf.fill.nta f122=[r15],loc1
733 ldf.fill.nta f35=[in0],loc0
734 ldf.fill.nta f43=[ r3],loc0
735 ldf.fill.nta f51=[r14],loc0
736 ldf.fill.nta f59=[r15],loc0
738 ldf.fill.nta f67=[in0],loc0
739 ldf.fill.nta f75=[ r3],loc0
740 ldf.fill.nta f83=[r14],loc0
741 ldf.fill.nta f91=[r15],loc0
743 ldf.fill.nta f99=[in0],loc1
744 ldf.fill.nta f107=[ r3],loc1
745 ldf.fill.nta f115=[r14],loc1
746 ldf.fill.nta f123=[r15],loc1
748 ldf.fill.nta f36=[in0],loc0
749 ldf.fill.nta f44=[ r3],loc0
750 ldf.fill.nta f52=[r14],loc0
751 ldf.fill.nta f60=[r15],loc0
753 ldf.fill.nta f68=[in0],loc0
754 ldf.fill.nta f76=[ r3],loc0
755 ldf.fill.nta f84=[r14],loc0
756 ldf.fill.nta f92=[r15],loc0
758 ldf.fill.nta f100=[in0],loc1
759 ldf.fill.nta f108=[ r3],loc1
760 ldf.fill.nta f116=[r14],loc1
761 ldf.fill.nta f124=[r15],loc1
763 ldf.fill.nta f37=[in0],loc0
764 ldf.fill.nta f45=[ r3],loc0
765 ldf.fill.nta f53=[r14],loc0
766 ldf.fill.nta f61=[r15],loc0
768 ldf.fill.nta f69=[in0],loc0
769 ldf.fill.nta f77=[ r3],loc0
770 ldf.fill.nta f85=[r14],loc0
771 ldf.fill.nta f93=[r15],loc0
773 ldf.fill.nta f101=[in0],loc1
774 ldf.fill.nta f109=[ r3],loc1
775 ldf.fill.nta f117=[r14],loc1
776 ldf.fill.nta f125=[r15],loc1
778 ldf.fill.nta f38 =[in0],loc0
779 ldf.fill.nta f46 =[ r3],loc0
780 ldf.fill.nta f54 =[r14],loc0
781 ldf.fill.nta f62 =[r15],loc0
783 ldf.fill.nta f70 =[in0],loc0
784 ldf.fill.nta f78 =[ r3],loc0
785 ldf.fill.nta f86 =[r14],loc0
786 ldf.fill.nta f94 =[r15],loc0
788 ldf.fill.nta f102=[in0],loc1
789 ldf.fill.nta f110=[ r3],loc1
790 ldf.fill.nta f118=[r14],loc1
791 ldf.fill.nta f126=[r15],loc1
793 ldf.fill.nta f39 =[in0],loc0
794 ldf.fill.nta f47 =[ r3],loc0
795 ldf.fill.nta f55 =[r14],loc0
796 ldf.fill.nta f63 =[r15],loc0
798 ldf.fill.nta f71 =[in0],loc0
799 ldf.fill.nta f79 =[ r3],loc0
800 ldf.fill.nta f87 =[r14],loc0
801 ldf.fill.nta f95 =[r15],loc0
803 ldf.fill.nta f103=[in0]
804 ldf.fill.nta f111=[ r3]
805 ldf.fill.nta f119=[r14]
806 ldf.fill.nta f127=[r15]
810 GLOBAL_ENTRY(__ia64_init_fpu)
811 stf.spill [sp]=f0 // M3
815 ldfps f33,f34=[sp] // M0
816 ldfps f35,f36=[sp] // M1
824 ldfps f41,f42=[sp] // M0
825 ldfps f43,f44=[sp] // M1
832 ldfps f49,f50=[sp] // M0
833 ldfps f51,f52=[sp] // M1
840 ldfps f57,f58=[sp] // M0
841 ldfps f59,f60=[sp] // M1
848 ldfps f65,f66=[sp] // M0
849 ldfps f67,f68=[sp] // M1
856 ldfps f73,f74=[sp] // M0
857 ldfps f75,f76=[sp] // M1
864 ldfps f81,f82=[sp] // M0
865 ldfps f83,f84=[sp] // M1
873 * When the instructions are cached, it would be faster to initialize
874 * the remaining registers with simply mov instructions (F-unit).
875 * This gets the time down to ~29 cycles. However, this would use up
876 * 33 bundles, whereas continuing with the above pattern yields
877 * 10 bundles and ~30 cycles.
880 ldfps f89,f90=[sp] // M0
881 ldfps f91,f92=[sp] // M1
888 ldfps f97,f98=[sp] // M0
889 ldfps f99,f100=[sp] // M1
896 ldfps f105,f106=[sp] // M0
897 ldfps f107,f108=[sp] // M1
904 ldfps f113,f114=[sp] // M0
905 ldfps f115,f116=[sp] // M1
912 ldfps f121,f122=[sp] // M0
913 ldfps f123,f124=[sp] // M1
918 br.ret.sptk.many rp // F
922 * Switch execution mode from virtual to physical
925 * r16 = new psr to establish
927 * r19 = old virtual address of ar.bsp
928 * r20 = old virtual address of sp
930 * Note: RSE must already be in enforced lazy mode
932 GLOBAL_ENTRY(ia64_switch_mode_phys)
934 rsm psr.i | psr.ic // disable interrupts and interrupt collection
939 flushrs // must be first insn in group
943 mov cr.ipsr=r16 // set new PSR
944 add r3=1f-ia64_switch_mode_phys,r15
948 mov r14=rp // get return address into a general register
951 // going to physical mode, use tpa to translate virt->phys
958 mov r18=ar.rnat // save ar.rnat
959 mov ar.bspstore=r17 // this steps on ar.rnat
963 mov ar.rnat=r18 // restore ar.rnat
964 rfi // must be last insn in group
968 END(ia64_switch_mode_phys)
971 * Switch execution mode from physical to virtual
974 * r16 = new psr to establish
975 * r19 = new bspstore to establish
976 * r20 = new sp to establish
978 * Note: RSE must already be in enforced lazy mode
980 GLOBAL_ENTRY(ia64_switch_mode_virt)
982 rsm psr.i | psr.ic // disable interrupts and interrupt collection
987 flushrs // must be first insn in group
991 mov cr.ipsr=r16 // set new PSR
992 add r3=1f-ia64_switch_mode_virt,r15
994 mov r14=rp // get return address into a general register
998 // - for code addresses, set upper bits of addr to KERNEL_START
999 // - for stack addresses, copy from input argument
1000 movl r18=KERNEL_START
1001 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
1002 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
1009 mov r18=ar.rnat // save ar.rnat
1010 mov ar.bspstore=r19 // this steps on ar.rnat
1014 mov ar.rnat=r18 // restore ar.rnat
1015 rfi // must be last insn in group
1019 END(ia64_switch_mode_virt)
1021 GLOBAL_ENTRY(ia64_delay_loop)
1023 { nop 0 // work around GAS unwind info generation bug...
1031 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
1032 // inside function body without corrupting unwind info).
1034 1: br.cloop.sptk.few 1b
1038 END(ia64_delay_loop)
1041 * Return a CPU-local timestamp in nano-seconds. This timestamp is
1042 * NOT synchronized across CPUs its return value must never be
1043 * compared against the values returned on another CPU. The usage in
1044 * kernel/sched.c ensures that.
1046 * The return-value of sched_clock() is NOT supposed to wrap-around.
1047 * If it did, it would cause some scheduling hiccups (at the worst).
1048 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1049 * that would happen only once every 5+ years.
1051 * The code below basically calculates:
1053 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1055 * except that the multiplication and the shift are done with 128-bit
1056 * intermediate precision so that we can produce a full 64-bit result.
1058 GLOBAL_ENTRY(ia64_native_sched_clock)
1059 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1060 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1064 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1066 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1067 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1069 getf.sig r8=f10 // (5 cyc)
1072 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1074 END(ia64_native_sched_clock)
1075 #ifndef CONFIG_PARAVIRT
1076 //unsigned long long
1077 //sched_clock(void) __attribute__((alias("ia64_native_sched_clock")));
1079 sched_clock = ia64_native_sched_clock
1082 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
1083 GLOBAL_ENTRY(cycle_to_cputime)
1084 alloc r16=ar.pfs,1,0,0,0
1085 addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1091 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1092 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1094 getf.sig r8=f10 // (5 cyc)
1097 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1099 END(cycle_to_cputime)
1100 #endif /* CONFIG_VIRT_CPU_ACCOUNTING */
1102 GLOBAL_ENTRY(start_kernel_thread)
1104 .save rp, r0 // this is the end of the call-chain
1106 alloc r2 = ar.pfs, 0, 0, 2, 0
1109 br.call.sptk.many rp = kernel_thread_helper;;
1111 br.call.sptk.many rp = sys_exit;;
1112 1: br.sptk.few 1b // not reached
1113 END(start_kernel_thread)
1115 #ifdef CONFIG_IA64_BRL_EMU
1118 * Assembly routines used by brl_emu.c to set preserved register state.
1121 #define SET_REG(reg) \
1122 GLOBAL_ENTRY(ia64_set_##reg); \
1123 alloc r16=ar.pfs,1,0,0,0; \
1126 br.ret.sptk.many rp; \
1135 #endif /* CONFIG_IA64_BRL_EMU */
1139 #ifdef CONFIG_HOTPLUG_CPU
1140 GLOBAL_ENTRY(ia64_jump_to_sal)
1141 alloc r16=ar.pfs,1,0,0,0;;
1148 movl r18=tlb_purge_done;;
1149 DATA_VA_TO_PA(r18);;
1150 mov b1=r18 // Return location
1151 movl r18=ia64_do_tlb_purge;;
1152 DATA_VA_TO_PA(r18);;
1153 mov b2=r18 // doing tlb_flush work
1154 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1156 DATA_VA_TO_PA(r17);;
1158 movl r16=SAL_PSR_BITS_TO_SET;;
1161 rfi;; // note: this unmask MCA/INIT (psr.mc)
1164 * Invalidate all TLB data/inst
1166 br.sptk.many b2;; // jump to tlb purge code
1169 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1170 RESTORE_REG(b0, r25, r17);;
1171 RESTORE_REG(b1, r25, r17);;
1172 RESTORE_REG(b2, r25, r17);;
1173 RESTORE_REG(b3, r25, r17);;
1174 RESTORE_REG(b4, r25, r17);;
1175 RESTORE_REG(b5, r25, r17);;
1177 ld8 r12=[r25],0x08;;
1178 ld8 r13=[r25],0x08;;
1179 RESTORE_REG(ar.fpsr, r25, r17);;
1180 RESTORE_REG(ar.pfs, r25, r17);;
1181 RESTORE_REG(ar.rnat, r25, r17);;
1182 RESTORE_REG(ar.unat, r25, r17);;
1183 RESTORE_REG(ar.bspstore, r25, r17);;
1184 RESTORE_REG(cr.dcr, r25, r17);;
1185 RESTORE_REG(cr.iva, r25, r17);;
1186 RESTORE_REG(cr.pta, r25, r17);;
1187 srlz.d;; // required not to violate RAW dependency
1188 RESTORE_REG(cr.itv, r25, r17);;
1189 RESTORE_REG(cr.pmv, r25, r17);;
1190 RESTORE_REG(cr.cmcv, r25, r17);;
1191 RESTORE_REG(cr.lrr0, r25, r17);;
1192 RESTORE_REG(cr.lrr1, r25, r17);;
1197 ld8 r17=[r25],0x08;;
1199 RESTORE_REG(ar.lc, r25, r17);;
1201 * Now Restore floating point regs
1203 ldf.fill.nta f2=[r25],16;;
1204 ldf.fill.nta f3=[r25],16;;
1205 ldf.fill.nta f4=[r25],16;;
1206 ldf.fill.nta f5=[r25],16;;
1207 ldf.fill.nta f16=[r25],16;;
1208 ldf.fill.nta f17=[r25],16;;
1209 ldf.fill.nta f18=[r25],16;;
1210 ldf.fill.nta f19=[r25],16;;
1211 ldf.fill.nta f20=[r25],16;;
1212 ldf.fill.nta f21=[r25],16;;
1213 ldf.fill.nta f22=[r25],16;;
1214 ldf.fill.nta f23=[r25],16;;
1215 ldf.fill.nta f24=[r25],16;;
1216 ldf.fill.nta f25=[r25],16;;
1217 ldf.fill.nta f26=[r25],16;;
1218 ldf.fill.nta f27=[r25],16;;
1219 ldf.fill.nta f28=[r25],16;;
1220 ldf.fill.nta f29=[r25],16;;
1221 ldf.fill.nta f30=[r25],16;;
1222 ldf.fill.nta f31=[r25],16;;
1225 * Now that we have done all the register restores
1226 * we are now ready for the big DIVE to SAL Land
1230 br.ret.sptk.many b0;;
1231 END(ia64_jump_to_sal)
1232 #endif /* CONFIG_HOTPLUG_CPU */
1234 #endif /* CONFIG_SMP */