arch/mips64/mm/cerr-sb1.c

   1 /*
   2  * Copyright (C) 2001 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #include <linux/sched.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/sibyte/sb1250.h>
  22
  23 #ifndef CONFIG_SIBYTE_BUS_WATCHER
  24 #include <asm/io.h>
  25 #include <asm/sibyte/sb1250_regs.h>
  26 #include <asm/sibyte/sb1250_scd.h>
  27 #include <asm/sibyte/64bit.h>
  28 #endif
  29
  30 /* SB1 definitions */
  31
  32 /* XXX should come from config1 XXX */
  33 #define SB1_CACHE_INDEX_MASK   0x1fe0
  34
  35 #define CP0_ERRCTL_RECOVERABLE (1 << 31)
  36 #define CP0_ERRCTL_DCACHE      (1 << 30)
  37 #define CP0_ERRCTL_ICACHE      (1 << 29)
  38 #define CP0_ERRCTL_MULTIBUS    (1 << 23)
  39 #define CP0_ERRCTL_MC_TLB      (1 << 15)
  40 #define CP0_ERRCTL_MC_TIMEOUT  (1 << 14)
  41
  42 #define CP0_CERRI_TAG_PARITY   (1 << 29)
  43 #define CP0_CERRI_DATA_PARITY  (1 << 28)
  44 #define CP0_CERRI_EXTERNAL     (1 << 26)
  45
  46 #define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))
  47 #define CP0_CERRI_DATA         (CP0_CERRI_DATA_PARITY)
  48
  49 #define CP0_CERRD_MULTIPLE     (1 << 31)
  50 #define CP0_CERRD_TAG_STATE    (1 << 30)
  51 #define CP0_CERRD_TAG_ADDRESS  (1 << 29)
  52 #define CP0_CERRD_DATA_SBE     (1 << 28)
  53 #define CP0_CERRD_DATA_DBE     (1 << 27)
  54 #define CP0_CERRD_EXTERNAL     (1 << 26)
  55 #define CP0_CERRD_LOAD         (1 << 25)
  56 #define CP0_CERRD_STORE        (1 << 24)
  57 #define CP0_CERRD_FILLWB       (1 << 23)
  58 #define CP0_CERRD_COHERENCY    (1 << 22)
  59 #define CP0_CERRD_DUPTAG       (1 << 21)
  60
  61 #define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL))
  62 #define CP0_CERRD_IDX_VALID(c) \
  63    (((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0)
  64 #define CP0_CERRD_CAUSES \
  65    (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG)
  66 #define CP0_CERRD_TYPES \
  67    (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL)
  68 #define CP0_CERRD_DATA         (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE)
  69
  70 static uint32_t extract_ic(unsigned short addr, int data);
  71 static uint32_t extract_dc(unsigned short addr, int data);
  72
  73 static inline void breakout_errctl(unsigned int val)
  74 {
  75         if (val & CP0_ERRCTL_RECOVERABLE)
  76                 prom_printf(" recoverable");
  77         if (val & CP0_ERRCTL_DCACHE)
  78                 prom_printf(" dcache");
  79         if (val & CP0_ERRCTL_ICACHE)
  80                 prom_printf(" icache");
  81         if (val & CP0_ERRCTL_MULTIBUS)
  82                 prom_printf(" multiple-buserr");
  83         prom_printf("\n");
  84 }
  85
  86 static inline void breakout_cerri(unsigned int val)
  87 {
  88         if (val & CP0_CERRI_TAG_PARITY)
  89                 prom_printf(" tag-parity");
  90         if (val & CP0_CERRI_DATA_PARITY)
  91                 prom_printf(" data-parity");
  92         if (val & CP0_CERRI_EXTERNAL)
  93                 prom_printf(" external");
  94         prom_printf("\n");
  95 }
  96
  97 static inline void breakout_cerrd(unsigned int val)
  98 {
  99         switch (val & CP0_CERRD_CAUSES) {
 100         case CP0_CERRD_LOAD:
 101                 prom_printf(" load,");
 102                 break;
 103         case CP0_CERRD_STORE:
 104                 prom_printf(" store,");
 105                 break;
 106         case CP0_CERRD_FILLWB:
 107                 prom_printf(" fill/wb,");
 108                 break;
 109         case CP0_CERRD_COHERENCY:
 110                 prom_printf(" coherency,");
 111                 break;
 112         case CP0_CERRD_DUPTAG:
 113                 prom_printf(" duptags,");
 114                 break;
 115         default:
 116                 prom_printf(" NO CAUSE,");
 117                 break;
 118         }
 119         if (!(val & CP0_CERRD_TYPES))
 120                 prom_printf(" NO TYPE");
 121         else {
 122                 if (val & CP0_CERRD_MULTIPLE)
 123                         prom_printf(" multi-err");
 124                 if (val & CP0_CERRD_TAG_STATE)
 125                         prom_printf(" tag-state");
 126                 if (val & CP0_CERRD_TAG_ADDRESS)
 127                         prom_printf(" tag-address");
 128                 if (val & CP0_CERRD_DATA_SBE)
 129                         prom_printf(" data-SBE");
 130                 if (val & CP0_CERRD_DATA_DBE)
 131                         prom_printf(" data-DBE");
 132                 if (val & CP0_CERRD_EXTERNAL)
 133                         prom_printf(" external");
 134         }
 135         prom_printf("\n");
 136 }
 137
 138 #ifndef CONFIG_SIBYTE_BUS_WATCHER
 139
 140 static void check_bus_watcher(void)
 141 {
 142         uint32_t status, l2_err, memio_err;
 143
 144         /* Destructive read, clears register and interrupt */
 145         status = csr_in32(IO_SPACE_BASE | A_SCD_BUS_ERR_STATUS);
 146         /* Bit 31 is always on, but there's no #define for that */
 147         if (status & ~(1UL << 31)) {
 148                 l2_err = csr_in32(IO_SPACE_BASE | A_BUS_L2_ERRORS);
 149                 memio_err = csr_in32(IO_SPACE_BASE | A_BUS_MEM_IO_ERRORS);
 150                 prom_printf("Bus watcher error counters: %08x %08x\n", l2_err, memio_err);
 151                 prom_printf("\nLast recorded signature:\n");
 152                 prom_printf("Request %02x from %d, answered by %d with Dcode %d\n",
 153                        (unsigned int)(G_SCD_BERR_TID(status) & 0x3f),
 154                        (int)(G_SCD_BERR_TID(status) >> 6),
 155                        (int)G_SCD_BERR_RID(status),
 156                        (int)G_SCD_BERR_DCODE(status));
 157         } else {
 158                 prom_printf("Bus watcher indicates no error\n");
 159         }
 160 }
 161 #else
 162 extern void check_bus_watcher(void);
 163 #endif
 164
 165 asmlinkage void sb1_cache_error(void)
 166 {
 167         uint64_t cerr_dpa;
 168         uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res;
 169
 170         prom_printf("Cache error exception on CPU %x:\n",
 171                     (read_c0_prid() >> 25) & 0x7);
 172
 173         __asm__ __volatile__ (
 174         "       .set    push\n\t"
 175         "       .set    mips64\n\t"
 176         "       .set    noat\n\t"
 177         "       mfc0    %0, $26\n\t"
 178         "       mfc0    %1, $27\n\t"
 179         "       mfc0    %2, $27, 1\n\t"
 180         "       dmfc0   $1, $27, 3\n\t"
 181         "       dsrl32  %3, $1, 0 \n\t"
 182         "       sll     %4, $1, 0 \n\t"
 183         "       mfc0    %5, $30\n\t"
 184         "       .set    pop"
 185         : "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d),
 186           "=r" (dpahi), "=r" (dpalo), "=r" (eepc));
 187
 188         cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;
 189         prom_printf(" c0_errorepc ==   %08x\n", eepc);
 190         prom_printf(" c0_errctl   ==   %08x", errctl);
 191         breakout_errctl(errctl);
 192         if (errctl & CP0_ERRCTL_ICACHE) {
 193                 prom_printf(" c0_cerr_i   ==   %08x", cerr_i);
 194                 breakout_cerri(cerr_i);
 195                 if (CP0_CERRI_IDX_VALID(cerr_i)) {
 196                         if ((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK))
 197                                 prom_printf(" cerr_i idx doesn't match eepc\n");
 198                         else {
 199                                 res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK,
 200                                                  (cerr_i & CP0_CERRI_DATA) != 0);
 201                                 if (!(res & cerr_i))
 202                                         prom_printf("...didn't see indicated icache problem\n");
 203                         }
 204                 }
 205         }
 206         if (errctl & CP0_ERRCTL_DCACHE) {
 207                 prom_printf(" c0_cerr_d   ==   %08x", cerr_d);
 208                 breakout_cerrd(cerr_d);
 209                 if (CP0_CERRD_DPA_VALID(cerr_d)) {
 210                         prom_printf(" c0_cerr_dpa == %010llx\n", cerr_dpa);
 211                         if (!CP0_CERRD_IDX_VALID(cerr_d)) {
 212                                 res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK,
 213                                                  (cerr_d & CP0_CERRD_DATA) != 0);
 214                                 if (!(res & cerr_d))
 215                                         prom_printf("...didn't see indicated dcache problem\n");
 216                         } else {
 217                                 if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK))
 218                                         prom_printf(" cerr_d idx doesn't match cerr_dpa\n");
 219                                 else {
 220                                         res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK,
 221                                                          (cerr_d & CP0_CERRD_DATA) != 0);
 222                                         if (!(res & cerr_d))
 223                                                 prom_printf("...didn't see indicated problem\n");
 224                                 }
 225                         }
 226                 }
 227         }
 228
 229         check_bus_watcher();
 230
 231         while (1);
 232         /*
 233          * This tends to make things get really ugly; let's just stall instead.
 234          *    panic("Can't handle the cache error!");
 235          */
 236 }
 237
 238
 239 /* Parity lookup table. */
 240 static const uint8_t parity[256] = {
 241         0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
 242         1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
 243         1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
 244         0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
 245         1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,
 246         0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
 247         0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,
 248         1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0
 249 };
 250
 251 /* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
 252 static const uint64_t mask_72_64[8] = {
 253         0x0738C808099264FFL,
 254         0x38C808099264FF07L,
 255         0xC808099264FF0738L,
 256         0x08099264FF0738C8L,
 257         0x099264FF0738C808L,
 258         0x9264FF0738C80809L,
 259         0x64FF0738C8080992L,
 260         0xFF0738C808099264L
 261 };
 262
 263 /* Calculate the parity on a range of bits */
 264 static char range_parity(uint64_t dword, int max, int min)
 265 {
 266         char parity = 0;
 267         int i;
 268         dword >>= min;
 269         for (i=max-min; i>=0; i--) {
 270                 if (dword & 0x1)
 271                         parity = !parity;
 272                 dword >>= 1;
 273         }
 274         return parity;
 275 }
 276
 277 /* Calculate the 4-bit even byte-parity for an instruction */
 278 static unsigned char inst_parity(uint32_t word)
 279 {
 280         int i, j;
 281         char parity = 0;
 282         for (j=0; j<4; j++) {
 283                 char byte_parity = 0;
 284                 for (i=0; i<8; i++) {
 285                         if (word & 0x80000000)
 286                                 byte_parity = !byte_parity;
 287                         word <<= 1;
 288                 }
 289                 parity <<= 1;
 290                 parity |= byte_parity;
 291         }
 292         return parity;
 293 }
 294
 295 static uint32_t extract_ic(unsigned short addr, int data)
 296 {
 297         unsigned short way;
 298         int valid;
 299         uint64_t taglo, va, tlo_tmp;
 300         uint32_t taghi, taglolo, taglohi;
 301         uint8_t lru;
 302         int res = 0;
 303
 304         prom_printf("Icache index 0x%04x  ", addr);
 305         for (way = 0; way < 4; way++) {
 306                 /* Index-load-tag-I */
 307                 __asm__ __volatile__ (
 308                 "       .set    push            \n\t"
 309                 "       .set    noreorder       \n\t"
 310                 "       .set    mips64          \n\t"
 311                 "       .set    noat            \n\t"
 312                 "       cache   4, 0(%3)        \n\t"
 313                 "       mfc0    %0, $29         \n\t"
 314                 "       dmfc0   $1, $28         \n\t"
 315                 "       dsrl32  %1, $1, 0       \n\t"
 316                 "       sll     %2, $1, 0       \n\t"
 317                 "       .set    pop"
 318                 : "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
 319                 : "r" ((way << 13) | addr));
 320
 321                 taglo = ((unsigned long long)taglohi << 32) | taglolo;
 322                 if (way == 0) {
 323                         lru = (taghi >> 14) & 0xff;
 324                         prom_printf("[Bank %d Set 0x%02x]  LRU > %d %d %d %d > MRU\n",
 325                                     ((addr >> 5) & 0x3), /* bank */
 326                                     ((addr >> 7) & 0x3f), /* index */
 327                                     (lru & 0x3),
 328                                     ((lru >> 2) & 0x3),
 329                                     ((lru >> 4) & 0x3),
 330                                     ((lru >> 6) & 0x3));
 331                 }
 332                 va = (taglo & 0xC0000FFFFFFFE000) | addr;
 333                 if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3))
 334                         va |= 0x3FFFF00000000000;
 335                 valid = ((taghi >> 29) & 1);
 336                 if (valid) {
 337                         tlo_tmp = taglo & 0xfff3ff;
 338                         if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) {
 339                                 prom_printf("   ** bad parity in VTag0/G/ASID\n");
 340                                 res |= CP0_CERRI_TAG_PARITY;
 341                         }
 342                         if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) {
 343                                 prom_printf("   ** bad parity in R/VTag1\n");
 344                                 res |= CP0_CERRI_TAG_PARITY;
 345                         }
 346                 }
 347                 if (valid ^ ((taghi >> 27) & 1)) {
 348                         prom_printf("   ** bad parity for valid bit\n");
 349                         res |= CP0_CERRI_TAG_PARITY;
 350                 }
 351                 prom_printf(" %d  [VA %016llx]  [Vld? %d]  raw tags: %08X-%016llX\n",
 352                             way, va, valid, taghi, taglo);
 353
 354                 if (data) {
 355                         uint32_t datahi, insta, instb;
 356                         uint8_t predecode;
 357                         int offset;
 358
 359                         /* (hit all banks and ways) */
 360                         for (offset = 0; offset < 4; offset++) {
 361                                 /* Index-load-data-I */
 362                                 __asm__ __volatile__ (
 363                                 "       .set    push\n\t"
 364                                 "       .set    noreorder\n\t"
 365                                 "       .set    mips64\n\t"
 366                                 "       .set    noat\n\t"
 367                                 "       cache   6, 0(%3)  \n\t"
 368                                 "       mfc0    %0, $29, 1\n\t"
 369                                 "       dmfc0  $1, $28, 1\n\t"
 370                                 "       dsrl32 %1, $1, 0 \n\t"
 371                                 "       sll    %2, $1, 0 \n\t"
 372                                 "       .set    pop         \n"
 373                                 : "=r" (datahi), "=r" (insta), "=r" (instb)
 374                                 : "r" ((way << 13) | addr | (offset << 3)));
 375                                 predecode = (datahi >> 8) & 0xff;
 376                                 if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) {
 377                                         prom_printf("   ** bad parity in predecode\n");
 378                                         res |= CP0_CERRI_DATA_PARITY;
 379                                 }
 380                                 /* XXXKW should/could check predecode bits themselves */
 381                                 if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) {
 382                                         prom_printf("   ** bad parity in instruction a\n");
 383                                         res |= CP0_CERRI_DATA_PARITY;
 384                                 }
 385                                 if ((datahi & 0xf) ^ inst_parity(instb)) {
 386                                         prom_printf("   ** bad parity in instruction b\n");
 387                                         res |= CP0_CERRI_DATA_PARITY;
 388                                 }
 389                                 prom_printf("  %05X-%08X%08X", datahi, insta, instb);
 390                         }
 391                         prom_printf("\n");
 392                 }
 393         }
 394         return res;
 395 }
 396
 397 /* Compute the ECC for a data doubleword */
 398 static uint8_t dc_ecc(uint64_t dword)
 399 {
 400         uint64_t t;
 401         uint32_t w;
 402         uint8_t  p;
 403         int      i;
 404
 405         p = 0;
 406         for (i = 7; i >= 0; i--)
 407         {
 408                 p <<= 1;
 409                 t = dword & mask_72_64[i];
 410                 w = (uint32_t)(t >> 32);
 411                 p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
 412                       ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
 413                 w = (uint32_t)(t & 0xFFFFFFFF);
 414                 p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF]
 415                       ^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]);
 416         }
 417         return p;
 418 }
 419
 420 struct dc_state {
 421         unsigned char val;
 422         char *name;
 423 };
 424
 425 static struct dc_state dc_states[] = {
 426         { 0x00, "INVALID" },
 427         { 0x0f, "COH-SHD" },
 428         { 0x13, "NCO-E-C" },
 429         { 0x19, "NCO-E-D" },
 430         { 0x16, "COH-E-C" },
 431         { 0x1c, "COH-E-D" },
 432         { 0xff, "*ERROR*" }
 433 };
 434
 435 #define DC_TAG_VALID(state) \
 436     (((state) == 0xf) || ((state) == 0x13) || ((state) == 0x19) || ((state == 0x16)) || ((state) == 0x1c))
 437
 438 static char *dc_state_str(unsigned char state)
 439 {
 440         struct dc_state *dsc = dc_states;
 441         while (dsc->val != 0xff) {
 442                 if (dsc->val == state)
 443                         break;
 444                 dsc++;
 445         }
 446         return dsc->name;
 447 }
 448
 449 static uint32_t extract_dc(unsigned short addr, int data)
 450 {
 451         int valid, way;
 452         unsigned char state;
 453         uint64_t taglo, pa;
 454         uint32_t taghi, taglolo, taglohi;
 455         uint8_t ecc, lru;
 456         int res = 0;
 457
 458         prom_printf("Dcache index 0x%04x  ", addr);
 459         for (way = 0; way < 4; way++) {
 460                 __asm__ __volatile__ (
 461                 "       .set    push\n\t"
 462                 "       .set    noreorder\n\t"
 463                 "       .set    mips64\n\t"
 464                 "       .set    noat\n\t"
 465                 "       cache   5, 0(%3)\n\t"   /* Index-load-tag-D */
 466                 "       mfc0    %0, $29, 2\n\t"
 467                 "       dmfc0   $1, $28, 2\n\t"
 468                 "       dsrl32  %1, $1, 0\n\t"
 469                 "       sll     %2, $1, 0\n\t"
 470                 "       .set    pop"
 471                 : "=r" (taghi), "=r" (taglohi), "=r" (taglolo)
 472                 : "r" ((way << 13) | addr));
 473
 474                 taglo = ((unsigned long long)taglohi << 32) | taglolo;
 475                 pa = (taglo & 0xFFFFFFE000) | addr;
 476                 if (way == 0) {
 477                         lru = (taghi >> 14) & 0xff;
 478                         prom_printf("[Bank %d Set 0x%02x]  LRU > %d %d %d %d > MRU\n",
 479                                     ((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */
 480                                     ((addr >> 6) & 0x3f), /* index */
 481                                     (lru & 0x3),
 482                                     ((lru >> 2) & 0x3),
 483                                     ((lru >> 4) & 0x3),
 484                                     ((lru >> 6) & 0x3));
 485                 }
 486                 state = (taghi >> 25) & 0x1f;
 487                 valid = DC_TAG_VALID(state);
 488                 prom_printf(" %d  [PA %010llx]  [state %s (%02x)]  raw tags: %08X-%016llX\n",
 489                             way, pa, dc_state_str(state), state, taghi, taglo);
 490                 if (valid) {
 491                         if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) {
 492                                 prom_printf("   ** bad parity in PTag1\n");
 493                                 res |= CP0_CERRD_TAG_ADDRESS;
 494                         }
 495                         if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) {
 496                                 prom_printf("   ** bad parity in PTag0\n");
 497                                 res |= CP0_CERRD_TAG_ADDRESS;
 498                         }
 499                 } else {
 500                         res |= CP0_CERRD_TAG_STATE;
 501                 }
 502
 503                 if (data) {
 504                         uint64_t datalo;
 505                         uint32_t datalohi, datalolo, datahi;
 506                         int offset;
 507
 508                         for (offset = 0; offset < 4; offset++) {
 509                                 /* Index-load-data-D */
 510                                 __asm__ __volatile__ (
 511                                 "       .set    push\n\t"
 512                                 "       .set    noreorder\n\t"
 513                                 "       .set    mips64\n\t"
 514                                 "       .set    noat\n\t"
 515                                 "       cache   7, 0(%3)\n\t" /* Index-load-data-D */
 516                                 "       mfc0    %0, $29, 3\n\t"
 517                                 "       dmfc0   $1, $28, 3\n\t"
 518                                 "       dsrl32  %1, $1, 0 \n\t"
 519                                 "       sll     %2, $1, 0 \n\t"
 520                                 "       .set    pop"
 521                                 : "=r" (datahi), "=r" (datalohi), "=r" (datalolo)
 522                                 : "r" ((way << 13) | addr | (offset << 3)));
 523                                 datalo = ((unsigned long long)datalohi << 32) | datalolo;
 524                                 ecc = dc_ecc(datalo);
 525                                 if (ecc != datahi) {
 526                                         int bits = 0;
 527                                         prom_printf("  ** bad ECC (%02x %02x) ->",
 528                                                     datahi, ecc);
 529                                         ecc ^= datahi;
 530                                         while (ecc) {
 531                                                 if (ecc & 1) bits++;
 532                                                 ecc >>= 1;
 533                                         }
 534                                         res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE;
 535                                 }
 536                                 prom_printf("  %02X-%016llX", datahi, datalo);
 537                         }
 538                         prom_printf("\n");
 539                 }
 540         }
 541         return res;
 542 }