2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
30 #include "nouveau_gpio.h"
32 #include <linux/io-mapping.h>
34 /* these defines are made up */
35 #define NV_CIO_CRE_44_HEADA 0x0
36 #define NV_CIO_CRE_44_HEADB 0x3
37 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
41 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42 #define LOG_OLD_VALUE(x)
49 static bool nv_cksum(const uint8_t *data, unsigned int length)
52 * There's a few checksums in the BIOS, so here's a generic checking
58 for (i = 0; i < length; i++)
68 score_vbios(struct nvbios *bios, const bool writeable)
70 if (!bios->data || bios->data[0] != 0x55 || bios->data[1] != 0xAA) {
71 NV_TRACEWARN(bios->dev, "... BIOS signature not found\n");
75 if (nv_cksum(bios->data, bios->data[2] * 512)) {
76 NV_TRACEWARN(bios->dev, "... BIOS checksum invalid\n");
77 /* if a ro image is somewhat bad, it's probably all rubbish */
78 return writeable ? 2 : 1;
81 NV_TRACE(bios->dev, "... appears to be valid\n");
86 bios_shadow_prom(struct nvbios *bios)
88 struct drm_device *dev = bios->dev;
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
94 /* enable access to rom */
95 if (dev_priv->card_type >= NV_50)
98 pcireg = NV_PBUS_PCI_NV_20;
99 access = nv_mask(dev, pcireg, 0x00000001, 0x00000000);
101 /* bail if no rom signature, with a workaround for a PROM reading
102 * issue on some chipsets. the first read after a period of
103 * inactivity returns the wrong result, so retry the first header
104 * byte a few times before giving up as a workaround
108 if (nv_rd08(dev, NV_PROM_OFFSET + 0) == 0x55)
112 if (!i || nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
115 /* additional check (see note below) - read PCI record header */
116 pcir = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
117 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
118 if (nv_rd08(dev, NV_PROM_OFFSET + pcir + 0) != 'P' ||
119 nv_rd08(dev, NV_PROM_OFFSET + pcir + 1) != 'C' ||
120 nv_rd08(dev, NV_PROM_OFFSET + pcir + 2) != 'I' ||
121 nv_rd08(dev, NV_PROM_OFFSET + pcir + 3) != 'R')
124 /* read entire bios image to system memory */
125 bios->length = nv_rd08(dev, NV_PROM_OFFSET + 2) * 512;
126 bios->data = kmalloc(bios->length, GFP_KERNEL);
128 for (i = 0; i < bios->length; i++)
129 bios->data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
133 /* disable access to rom */
134 nv_wr32(dev, pcireg, access);
138 bios_shadow_pramin(struct nvbios *bios)
140 struct drm_device *dev = bios->dev;
141 struct drm_nouveau_private *dev_priv = dev->dev_private;
145 if (dev_priv->card_type >= NV_50) {
146 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
148 addr = (u64)nv_rd32(dev, 0x001700) << 16;
152 bar0 = nv_mask(dev, 0x001700, 0xffffffff, addr >> 16);
155 /* bail if no rom signature */
156 if (nv_rd08(dev, NV_PRAMIN_OFFSET + 0) != 0x55 ||
157 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
160 bios->length = nv_rd08(dev, NV_PRAMIN_OFFSET + 2) * 512;
161 bios->data = kmalloc(bios->length, GFP_KERNEL);
163 for (i = 0; i < bios->length; i++)
164 bios->data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
168 if (dev_priv->card_type >= NV_50)
169 nv_wr32(dev, 0x001700, bar0);
173 bios_shadow_pci(struct nvbios *bios)
175 struct pci_dev *pdev = bios->dev->pdev;
178 if (!pci_enable_rom(pdev)) {
179 void __iomem *rom = pci_map_rom(pdev, &length);
181 bios->data = kmalloc(length, GFP_KERNEL);
183 memcpy_fromio(bios->data, rom, length);
184 bios->length = length;
186 pci_unmap_rom(pdev, rom);
189 pci_disable_rom(pdev);
194 bios_shadow_acpi(struct nvbios *bios)
196 struct pci_dev *pdev = bios->dev->pdev;
200 if (!nouveau_acpi_rom_supported(pdev))
203 ret = nouveau_acpi_get_bios_chunk(data, 0, sizeof(data));
204 if (ret != sizeof(data))
207 bios->length = min(data[2] * 512, 65536);
208 bios->data = kmalloc(bios->length, GFP_KERNEL);
215 int size = (len > ROM_BIOS_PAGE) ? ROM_BIOS_PAGE : len;
217 ret = nouveau_acpi_get_bios_chunk(bios->data, ptr, size);
231 void (*shadow)(struct nvbios *);
239 bios_shadow(struct drm_device *dev)
241 struct methods shadow_methods[] = {
242 { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL },
243 { "PROM", bios_shadow_prom, false, 0, 0, NULL },
244 { "ACPI", bios_shadow_acpi, true, 0, 0, NULL },
245 { "PCIROM", bios_shadow_pci, true, 0, 0, NULL },
248 struct drm_nouveau_private *dev_priv = dev->dev_private;
249 struct nvbios *bios = &dev_priv->vbios;
250 struct methods *mthd, *best;
253 mthd = shadow_methods;
255 if (strcasecmp(nouveau_vbios, mthd->desc))
257 NV_INFO(dev, "VBIOS source: %s\n", mthd->desc);
260 mthd->score = score_vbios(bios, mthd->rw);
263 } while ((++mthd)->shadow);
265 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
268 mthd = shadow_methods;
270 NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc);
272 mthd->score = score_vbios(bios, mthd->rw);
273 mthd->size = bios->length;
274 mthd->data = bios->data;
275 } while (mthd->score != 3 && (++mthd)->shadow);
277 mthd = shadow_methods;
280 if (mthd->score > best->score) {
284 } while ((++mthd)->shadow);
287 NV_TRACE(dev, "Using VBIOS from %s\n", best->desc);
288 bios->length = best->size;
289 bios->data = best->data;
293 NV_ERROR(dev, "No valid VBIOS image found\n");
297 struct init_tbl_entry {
301 * > 0: success, length of opcode
302 * 0: success, but abort further parsing of table (INIT_DONE etc)
303 * < 0: failure, table parsing will be aborted
305 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
308 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
310 #define MACRO_INDEX_SIZE 2
312 #define CONDITION_SIZE 12
313 #define IO_FLAG_CONDITION_SIZE 9
314 #define IO_CONDITION_SIZE 5
315 #define MEM_INIT_SIZE 66
317 static void still_alive(void)
326 munge_reg(struct nvbios *bios, uint32_t reg)
328 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
329 struct dcb_entry *dcbent = bios->display.output;
331 if (dev_priv->card_type < NV_50)
334 if (reg & 0x80000000) {
335 BUG_ON(bios->display.crtc < 0);
336 reg += bios->display.crtc * 0x800;
339 if (reg & 0x40000000) {
342 reg += (ffs(dcbent->or) - 1) * 0x800;
343 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
352 valid_reg(struct nvbios *bios, uint32_t reg)
354 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
355 struct drm_device *dev = bios->dev;
357 /* C51 has misaligned regs on purpose. Marvellous */
359 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
360 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
362 /* warn on C51 regs that haven't been verified accessible in tracing */
363 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
364 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
365 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
368 if (reg >= (8*1024*1024)) {
369 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
377 valid_idx_port(struct nvbios *bios, uint16_t port)
379 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
380 struct drm_device *dev = bios->dev;
383 * If adding more ports here, the read/write functions below will need
384 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
385 * used for the port in question
387 if (dev_priv->card_type < NV_50) {
388 if (port == NV_CIO_CRX__COLOR)
390 if (port == NV_VIO_SRX)
393 if (port == NV_CIO_CRX__COLOR)
397 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
404 valid_port(struct nvbios *bios, uint16_t port)
406 struct drm_device *dev = bios->dev;
409 * If adding more ports here, the read/write functions below will need
410 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
411 * used for the port in question
413 if (port == NV_VIO_VSE2)
416 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
422 bios_rd32(struct nvbios *bios, uint32_t reg)
426 reg = munge_reg(bios, reg);
427 if (!valid_reg(bios, reg))
431 * C51 sometimes uses regs with bit0 set in the address. For these
432 * cases there should exist a translation in a BIOS table to an IO
433 * port address which the BIOS uses for accessing the reg
435 * These only seem to appear for the power control regs to a flat panel,
436 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
437 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
438 * suspend-resume mmio trace from a C51 will be required to see if this
439 * is true for the power microcode in 0x14.., or whether the direct IO
440 * port access method is needed
445 data = nv_rd32(bios->dev, reg);
447 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
453 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
455 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
457 reg = munge_reg(bios, reg);
458 if (!valid_reg(bios, reg))
461 /* see note in bios_rd32 */
465 LOG_OLD_VALUE(bios_rd32(bios, reg));
466 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
468 if (dev_priv->vbios.execute) {
470 nv_wr32(bios->dev, reg, data);
475 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
477 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
478 struct drm_device *dev = bios->dev;
481 if (!valid_idx_port(bios, port))
484 if (dev_priv->card_type < NV_50) {
485 if (port == NV_VIO_SRX)
486 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
487 else /* assume NV_CIO_CRX__COLOR */
488 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
492 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
493 data = (data32 >> ((index & 3) << 3)) & 0xff;
496 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
497 "Head: 0x%02X, Data: 0x%02X\n",
498 port, index, bios->state.crtchead, data);
503 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
505 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
506 struct drm_device *dev = bios->dev;
508 if (!valid_idx_port(bios, port))
512 * The current head is maintained in the nvbios member state.crtchead.
513 * We trap changes to CR44 and update the head variable and hence the
514 * register set written.
515 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
516 * of the write, and to head1 after the write
518 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
519 data != NV_CIO_CRE_44_HEADB)
520 bios->state.crtchead = 0;
522 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
523 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
524 "Head: 0x%02X, Data: 0x%02X\n",
525 port, index, bios->state.crtchead, data);
527 if (bios->execute && dev_priv->card_type < NV_50) {
529 if (port == NV_VIO_SRX)
530 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
531 else /* assume NV_CIO_CRX__COLOR */
532 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
535 uint32_t data32, shift = (index & 3) << 3;
539 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
540 data32 &= ~(0xff << shift);
541 data32 |= (data << shift);
542 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
545 if (port == NV_CIO_CRX__COLOR &&
546 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
547 bios->state.crtchead = 1;
551 bios_port_rd(struct nvbios *bios, uint16_t port)
553 uint8_t data, head = bios->state.crtchead;
555 if (!valid_port(bios, port))
558 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
560 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
567 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
569 int head = bios->state.crtchead;
571 if (!valid_port(bios, port))
574 LOG_OLD_VALUE(bios_port_rd(bios, port));
575 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
582 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
586 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
589 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
590 * for the CRTC index; 1 byte for the mask to apply to the value
591 * retrieved from the CRTC; 1 byte for the shift right to apply to the
592 * masked CRTC value; 2 bytes for the offset to the flag array, to
593 * which the shifted value is added; 1 byte for the mask applied to the
594 * value read from the flag array; and 1 byte for the value to compare
595 * against the masked byte from the flag table.
598 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
599 uint16_t crtcport = ROM16(bios->data[condptr]);
600 uint8_t crtcindex = bios->data[condptr + 2];
601 uint8_t mask = bios->data[condptr + 3];
602 uint8_t shift = bios->data[condptr + 4];
603 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
604 uint8_t flagarraymask = bios->data[condptr + 7];
605 uint8_t cmpval = bios->data[condptr + 8];
608 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
609 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
611 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
613 data = bios_idxprt_rd(bios, crtcport, crtcindex);
615 data = bios->data[flagarray + ((data & mask) >> shift)];
616 data &= flagarraymask;
618 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
619 offset, data, cmpval);
621 return (data == cmpval);
625 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
628 * The condition table entry has 4 bytes for the address of the
629 * register to check, 4 bytes for a mask to apply to the register and
630 * 4 for a test comparison value
633 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
634 uint32_t reg = ROM32(bios->data[condptr]);
635 uint32_t mask = ROM32(bios->data[condptr + 4]);
636 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
639 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
640 offset, cond, reg, mask);
642 data = bios_rd32(bios, reg) & mask;
644 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
645 offset, data, cmpval);
647 return (data == cmpval);
651 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
654 * The IO condition entry has 2 bytes for the IO port address; 1 byte
655 * for the index to write to io_port; 1 byte for the mask to apply to
656 * the byte read from io_port+1; and 1 byte for the value to compare
657 * against the masked byte.
660 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
661 uint16_t io_port = ROM16(bios->data[condptr]);
662 uint8_t port_index = bios->data[condptr + 2];
663 uint8_t mask = bios->data[condptr + 3];
664 uint8_t cmpval = bios->data[condptr + 4];
666 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
668 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
669 offset, data, cmpval);
671 return (data == cmpval);
675 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
677 struct drm_nouveau_private *dev_priv = dev->dev_private;
678 struct nouveau_pll_vals pll;
679 struct pll_lims pll_limits;
680 u32 ctrl, mask, coef;
683 ret = get_pll_limits(dev, reg, &pll_limits);
687 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
691 coef = pll.N1 << 8 | pll.M1;
692 ctrl = pll.log2P << 16;
694 if (reg == 0x004008) {
696 ctrl |= (pll_limits.log2p_bias << 19);
697 ctrl |= (pll.log2P << 22);
700 if (!dev_priv->vbios.execute)
703 nv_mask(dev, reg + 0, mask, ctrl);
704 nv_wr32(dev, reg + 4, coef);
709 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
711 struct drm_device *dev = bios->dev;
712 struct drm_nouveau_private *dev_priv = dev->dev_private;
714 struct pll_lims pll_lim;
715 struct nouveau_pll_vals pllvals;
718 if (dev_priv->card_type >= NV_50)
719 return nv50_pll_set(dev, reg, clk);
721 /* high regs (such as in the mac g5 table) are not -= 4 */
722 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
726 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
732 nouveau_hw_setpll(dev, reg, &pllvals);
738 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
740 struct drm_nouveau_private *dev_priv = dev->dev_private;
741 struct nvbios *bios = &dev_priv->vbios;
744 * For the results of this function to be correct, CR44 must have been
745 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
746 * and the DCB table parsed, before the script calling the function is
747 * run. run_digital_op_script is example of how to do such setup
750 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
752 if (dcb_entry > bios->dcb.entries) {
753 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
754 "(%02X)\n", dcb_entry);
755 dcb_entry = 0x7f; /* unused / invalid marker */
761 static struct nouveau_i2c_chan *
762 init_i2c_device_find(struct drm_device *dev, int i2c_index)
764 if (i2c_index == 0xff) {
765 struct drm_nouveau_private *dev_priv = dev->dev_private;
766 struct dcb_table *dcb = &dev_priv->vbios.dcb;
767 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
768 int idx = dcb_entry_idx_from_crtchead(dev);
770 i2c_index = NV_I2C_DEFAULT(0);
771 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
772 i2c_index = NV_I2C_DEFAULT(1);
775 return nouveau_i2c_find(dev, i2c_index);
779 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
782 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
783 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
784 * CR58 for CR57 = 0 to index a table of offsets to the basic
786 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
787 * CR58 for CR57 = 0 to index a table of offsets to the basic
788 * 0x6808b0 address, and then flip the offset by 8.
791 struct drm_nouveau_private *dev_priv = dev->dev_private;
792 struct nvbios *bios = &dev_priv->vbios;
793 const int pramdac_offset[13] = {
794 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
795 const uint32_t pramdac_table[4] = {
796 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
799 int dcb_entry, dacoffset;
801 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
802 dcb_entry = dcb_entry_idx_from_crtchead(dev);
803 if (dcb_entry == 0x7f)
805 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
808 return 0x6808b0 + dacoffset;
810 if (mlv >= ARRAY_SIZE(pramdac_table)) {
811 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
815 return pramdac_table[mlv];
820 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
821 struct init_exec *iexec)
824 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
826 * offset (8 bit): opcode
827 * offset + 1 (16 bit): CRTC port
828 * offset + 3 (8 bit): CRTC index
829 * offset + 4 (8 bit): mask
830 * offset + 5 (8 bit): shift
831 * offset + 6 (8 bit): count
832 * offset + 7 (32 bit): register
833 * offset + 11 (32 bit): configuration 1
836 * Starting at offset + 11 there are "count" 32 bit values.
837 * To find out which value to use read index "CRTC index" on "CRTC
838 * port", AND this value with "mask" and then bit shift right "shift"
839 * bits. Read the appropriate value using this index and write to
843 uint16_t crtcport = ROM16(bios->data[offset + 1]);
844 uint8_t crtcindex = bios->data[offset + 3];
845 uint8_t mask = bios->data[offset + 4];
846 uint8_t shift = bios->data[offset + 5];
847 uint8_t count = bios->data[offset + 6];
848 uint32_t reg = ROM32(bios->data[offset + 7]);
851 int len = 11 + count * 4;
856 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
857 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
858 offset, crtcport, crtcindex, mask, shift, count, reg);
860 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
861 if (config > count) {
863 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
864 offset, config, count);
868 configval = ROM32(bios->data[offset + 11 + config * 4]);
870 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
872 bios_wr32(bios, reg, configval);
878 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
881 * INIT_REPEAT opcode: 0x33 ('3')
883 * offset (8 bit): opcode
884 * offset + 1 (8 bit): count
886 * Execute script following this opcode up to INIT_REPEAT_END
890 uint8_t count = bios->data[offset + 1];
893 /* no iexec->execute check by design */
895 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
898 iexec->repeat = true;
901 * count - 1, as the script block will execute once when we leave this
902 * opcode -- this is compatible with bios behaviour as:
903 * a) the block is always executed at least once, even if count == 0
904 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
907 for (i = 0; i < count - 1; i++)
908 parse_init_table(bios, offset + 2, iexec);
910 iexec->repeat = false;
916 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
917 struct init_exec *iexec)
920 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
922 * offset (8 bit): opcode
923 * offset + 1 (16 bit): CRTC port
924 * offset + 3 (8 bit): CRTC index
925 * offset + 4 (8 bit): mask
926 * offset + 5 (8 bit): shift
927 * offset + 6 (8 bit): IO flag condition index
928 * offset + 7 (8 bit): count
929 * offset + 8 (32 bit): register
930 * offset + 12 (16 bit): frequency 1
933 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
934 * Set PLL register "register" to coefficients for frequency n,
935 * selected by reading index "CRTC index" of "CRTC port" ANDed with
936 * "mask" and shifted right by "shift".
938 * If "IO flag condition index" > 0, and condition met, double
939 * frequency before setting it.
942 uint16_t crtcport = ROM16(bios->data[offset + 1]);
943 uint8_t crtcindex = bios->data[offset + 3];
944 uint8_t mask = bios->data[offset + 4];
945 uint8_t shift = bios->data[offset + 5];
946 int8_t io_flag_condition_idx = bios->data[offset + 6];
947 uint8_t count = bios->data[offset + 7];
948 uint32_t reg = ROM32(bios->data[offset + 8]);
951 int len = 12 + count * 2;
956 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
957 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
958 "Count: 0x%02X, Reg: 0x%08X\n",
959 offset, crtcport, crtcindex, mask, shift,
960 io_flag_condition_idx, count, reg);
962 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
963 if (config > count) {
965 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
966 offset, config, count);
970 freq = ROM16(bios->data[offset + 12 + config * 2]);
972 if (io_flag_condition_idx > 0) {
973 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
974 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
975 "frequency doubled\n", offset);
978 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
979 "frequency unchanged\n", offset);
982 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
983 offset, reg, config, freq);
985 setPLL(bios, reg, freq * 10);
991 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
994 * INIT_END_REPEAT opcode: 0x36 ('6')
996 * offset (8 bit): opcode
998 * Marks the end of the block for INIT_REPEAT to repeat
1001 /* no iexec->execute check by design */
1004 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1005 * we're not in repeat mode
1014 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1017 * INIT_COPY opcode: 0x37 ('7')
1019 * offset (8 bit): opcode
1020 * offset + 1 (32 bit): register
1021 * offset + 5 (8 bit): shift
1022 * offset + 6 (8 bit): srcmask
1023 * offset + 7 (16 bit): CRTC port
1024 * offset + 9 (8 bit): CRTC index
1025 * offset + 10 (8 bit): mask
1027 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1028 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1032 uint32_t reg = ROM32(bios->data[offset + 1]);
1033 uint8_t shift = bios->data[offset + 5];
1034 uint8_t srcmask = bios->data[offset + 6];
1035 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1036 uint8_t crtcindex = bios->data[offset + 9];
1037 uint8_t mask = bios->data[offset + 10];
1041 if (!iexec->execute)
1044 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1045 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1046 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1048 data = bios_rd32(bios, reg);
1053 data <<= (0x100 - shift);
1057 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1058 crtcdata |= (uint8_t)data;
1059 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1065 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1068 * INIT_NOT opcode: 0x38 ('8')
1070 * offset (8 bit): opcode
1072 * Invert the current execute / no-execute condition (i.e. "else")
1075 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1077 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1079 iexec->execute = !iexec->execute;
1084 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1085 struct init_exec *iexec)
1088 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1090 * offset (8 bit): opcode
1091 * offset + 1 (8 bit): condition number
1093 * Check condition "condition number" in the IO flag condition table.
1094 * If condition not met skip subsequent opcodes until condition is
1095 * inverted (INIT_NOT), or we hit INIT_RESUME
1098 uint8_t cond = bios->data[offset + 1];
1100 if (!iexec->execute)
1103 if (io_flag_condition_met(bios, offset, cond))
1104 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1106 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1107 iexec->execute = false;
1114 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1117 * INIT_DP_CONDITION opcode: 0x3A ('')
1119 * offset (8 bit): opcode
1120 * offset + 1 (8 bit): "sub" opcode
1121 * offset + 2 (8 bit): unknown
1125 struct dcb_entry *dcb = bios->display.output;
1126 struct drm_device *dev = bios->dev;
1127 uint8_t cond = bios->data[offset + 1];
1128 uint8_t *table, *entry;
1130 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1132 if (!iexec->execute)
1135 table = nouveau_dp_bios_data(dev, dcb, &entry);
1141 entry = dcb_conn(dev, dcb->connector);
1142 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
1143 iexec->execute = false;
1147 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
1148 (table[0] == 0x40 && !(entry[4] & cond)))
1149 iexec->execute = false;
1153 struct nouveau_i2c_chan *auxch;
1156 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
1158 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1162 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
1164 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1169 iexec->execute = false;
1173 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1178 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1180 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1186 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1189 * INIT_3B opcode: 0x3B ('')
1191 * offset (8 bit): opcode
1192 * offset + 1 (8 bit): crtc index
1196 uint8_t or = ffs(bios->display.output->or) - 1;
1197 uint8_t index = bios->data[offset + 1];
1200 if (!iexec->execute)
1203 data = bios_idxprt_rd(bios, 0x3d4, index);
1204 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1209 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1212 * INIT_3C opcode: 0x3C ('')
1214 * offset (8 bit): opcode
1215 * offset + 1 (8 bit): crtc index
1219 uint8_t or = ffs(bios->display.output->or) - 1;
1220 uint8_t index = bios->data[offset + 1];
1223 if (!iexec->execute)
1226 data = bios_idxprt_rd(bios, 0x3d4, index);
1227 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1232 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1233 struct init_exec *iexec)
1236 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1238 * offset (8 bit): opcode
1239 * offset + 1 (32 bit): control register
1240 * offset + 5 (32 bit): data register
1241 * offset + 9 (32 bit): mask
1242 * offset + 13 (32 bit): data
1243 * offset + 17 (8 bit): count
1244 * offset + 18 (8 bit): address 1
1245 * offset + 19 (8 bit): data 1
1248 * For each of "count" address and data pairs, write "data n" to
1249 * "data register", read the current value of "control register",
1250 * and write it back once ANDed with "mask", ORed with "data",
1251 * and ORed with "address n"
1254 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1255 uint32_t datareg = ROM32(bios->data[offset + 5]);
1256 uint32_t mask = ROM32(bios->data[offset + 9]);
1257 uint32_t data = ROM32(bios->data[offset + 13]);
1258 uint8_t count = bios->data[offset + 17];
1259 int len = 18 + count * 2;
1263 if (!iexec->execute)
1266 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1267 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1268 offset, controlreg, datareg, mask, data, count);
1270 for (i = 0; i < count; i++) {
1271 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1272 uint8_t instdata = bios->data[offset + 19 + i * 2];
1274 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1275 offset, instaddress, instdata);
1277 bios_wr32(bios, datareg, instdata);
1278 value = bios_rd32(bios, controlreg) & mask;
1280 value |= instaddress;
1281 bios_wr32(bios, controlreg, value);
1288 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1289 struct init_exec *iexec)
1292 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1294 * offset (8 bit): opcode
1295 * offset + 1 (16 bit): CRTC port
1296 * offset + 3 (8 bit): CRTC index
1297 * offset + 4 (8 bit): mask
1298 * offset + 5 (8 bit): shift
1299 * offset + 6 (8 bit): count
1300 * offset + 7 (32 bit): register
1301 * offset + 11 (32 bit): frequency 1
1304 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1305 * Set PLL register "register" to coefficients for frequency n,
1306 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1307 * "mask" and shifted right by "shift".
1310 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1311 uint8_t crtcindex = bios->data[offset + 3];
1312 uint8_t mask = bios->data[offset + 4];
1313 uint8_t shift = bios->data[offset + 5];
1314 uint8_t count = bios->data[offset + 6];
1315 uint32_t reg = ROM32(bios->data[offset + 7]);
1316 int len = 11 + count * 4;
1320 if (!iexec->execute)
1323 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1324 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1325 offset, crtcport, crtcindex, mask, shift, count, reg);
1330 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1331 if (config > count) {
1333 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1334 offset, config, count);
1338 freq = ROM32(bios->data[offset + 11 + config * 4]);
1340 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1341 offset, reg, config, freq);
1343 setPLL(bios, reg, freq);
1349 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1352 * INIT_PLL2 opcode: 0x4B ('K')
1354 * offset (8 bit): opcode
1355 * offset + 1 (32 bit): register
1356 * offset + 5 (32 bit): freq
1358 * Set PLL register "register" to coefficients for frequency "freq"
1361 uint32_t reg = ROM32(bios->data[offset + 1]);
1362 uint32_t freq = ROM32(bios->data[offset + 5]);
1364 if (!iexec->execute)
1367 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1370 setPLL(bios, reg, freq);
1375 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1378 * INIT_I2C_BYTE opcode: 0x4C ('L')
1380 * offset (8 bit): opcode
1381 * offset + 1 (8 bit): DCB I2C table entry index
1382 * offset + 2 (8 bit): I2C slave address
1383 * offset + 3 (8 bit): count
1384 * offset + 4 (8 bit): I2C register 1
1385 * offset + 5 (8 bit): mask 1
1386 * offset + 6 (8 bit): data 1
1389 * For each of "count" registers given by "I2C register n" on the device
1390 * addressed by "I2C slave address" on the I2C bus given by
1391 * "DCB I2C table entry index", read the register, AND the result with
1392 * "mask n" and OR it with "data n" before writing it back to the device
1395 struct drm_device *dev = bios->dev;
1396 uint8_t i2c_index = bios->data[offset + 1];
1397 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1398 uint8_t count = bios->data[offset + 3];
1399 struct nouveau_i2c_chan *chan;
1400 int len = 4 + count * 3;
1403 if (!iexec->execute)
1406 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1408 offset, i2c_index, i2c_address, count);
1410 chan = init_i2c_device_find(dev, i2c_index);
1412 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1416 for (i = 0; i < count; i++) {
1417 uint8_t reg = bios->data[offset + 4 + i * 3];
1418 uint8_t mask = bios->data[offset + 5 + i * 3];
1419 uint8_t data = bios->data[offset + 6 + i * 3];
1420 union i2c_smbus_data val;
1422 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1423 I2C_SMBUS_READ, reg,
1424 I2C_SMBUS_BYTE_DATA, &val);
1426 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1430 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1431 "Mask: 0x%02X, Data: 0x%02X\n",
1432 offset, reg, val.byte, mask, data);
1439 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1440 I2C_SMBUS_WRITE, reg,
1441 I2C_SMBUS_BYTE_DATA, &val);
1443 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1452 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1455 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1457 * offset (8 bit): opcode
1458 * offset + 1 (8 bit): DCB I2C table entry index
1459 * offset + 2 (8 bit): I2C slave address
1460 * offset + 3 (8 bit): count
1461 * offset + 4 (8 bit): I2C register 1
1462 * offset + 5 (8 bit): data 1
1465 * For each of "count" registers given by "I2C register n" on the device
1466 * addressed by "I2C slave address" on the I2C bus given by
1467 * "DCB I2C table entry index", set the register to "data n"
1470 struct drm_device *dev = bios->dev;
1471 uint8_t i2c_index = bios->data[offset + 1];
1472 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1473 uint8_t count = bios->data[offset + 3];
1474 struct nouveau_i2c_chan *chan;
1475 int len = 4 + count * 2;
1478 if (!iexec->execute)
1481 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1483 offset, i2c_index, i2c_address, count);
1485 chan = init_i2c_device_find(dev, i2c_index);
1487 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1491 for (i = 0; i < count; i++) {
1492 uint8_t reg = bios->data[offset + 4 + i * 2];
1493 union i2c_smbus_data val;
1495 val.byte = bios->data[offset + 5 + i * 2];
1497 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1498 offset, reg, val.byte);
1503 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1504 I2C_SMBUS_WRITE, reg,
1505 I2C_SMBUS_BYTE_DATA, &val);
1507 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1516 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1519 * INIT_ZM_I2C opcode: 0x4E ('N')
1521 * offset (8 bit): opcode
1522 * offset + 1 (8 bit): DCB I2C table entry index
1523 * offset + 2 (8 bit): I2C slave address
1524 * offset + 3 (8 bit): count
1525 * offset + 4 (8 bit): data 1
1528 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1529 * address" on the I2C bus given by "DCB I2C table entry index"
1532 struct drm_device *dev = bios->dev;
1533 uint8_t i2c_index = bios->data[offset + 1];
1534 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1535 uint8_t count = bios->data[offset + 3];
1536 int len = 4 + count;
1537 struct nouveau_i2c_chan *chan;
1542 if (!iexec->execute)
1545 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1547 offset, i2c_index, i2c_address, count);
1549 chan = init_i2c_device_find(dev, i2c_index);
1551 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1555 for (i = 0; i < count; i++) {
1556 data[i] = bios->data[offset + 4 + i];
1558 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1561 if (bios->execute) {
1562 msg.addr = i2c_address;
1566 ret = i2c_transfer(&chan->adapter, &msg, 1);
1568 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1577 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1580 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1582 * offset (8 bit): opcode
1583 * offset + 1 (8 bit): magic lookup value
1584 * offset + 2 (8 bit): TMDS address
1585 * offset + 3 (8 bit): mask
1586 * offset + 4 (8 bit): data
1588 * Read the data reg for TMDS address "TMDS address", AND it with mask
1589 * and OR it with data, then write it back
1590 * "magic lookup value" determines which TMDS base address register is
1591 * used -- see get_tmds_index_reg()
1594 struct drm_device *dev = bios->dev;
1595 uint8_t mlv = bios->data[offset + 1];
1596 uint32_t tmdsaddr = bios->data[offset + 2];
1597 uint8_t mask = bios->data[offset + 3];
1598 uint8_t data = bios->data[offset + 4];
1599 uint32_t reg, value;
1601 if (!iexec->execute)
1604 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1605 "Mask: 0x%02X, Data: 0x%02X\n",
1606 offset, mlv, tmdsaddr, mask, data);
1608 reg = get_tmds_index_reg(bios->dev, mlv);
1610 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1614 bios_wr32(bios, reg,
1615 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1616 value = (bios_rd32(bios, reg + 4) & mask) | data;
1617 bios_wr32(bios, reg + 4, value);
1618 bios_wr32(bios, reg, tmdsaddr);
1624 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1625 struct init_exec *iexec)
1628 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1630 * offset (8 bit): opcode
1631 * offset + 1 (8 bit): magic lookup value
1632 * offset + 2 (8 bit): count
1633 * offset + 3 (8 bit): addr 1
1634 * offset + 4 (8 bit): data 1
1637 * For each of "count" TMDS address and data pairs write "data n" to
1638 * "addr n". "magic lookup value" determines which TMDS base address
1639 * register is used -- see get_tmds_index_reg()
1642 struct drm_device *dev = bios->dev;
1643 uint8_t mlv = bios->data[offset + 1];
1644 uint8_t count = bios->data[offset + 2];
1645 int len = 3 + count * 2;
1649 if (!iexec->execute)
1652 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1653 offset, mlv, count);
1655 reg = get_tmds_index_reg(bios->dev, mlv);
1657 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1661 for (i = 0; i < count; i++) {
1662 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1663 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1665 bios_wr32(bios, reg + 4, tmdsdata);
1666 bios_wr32(bios, reg, tmdsaddr);
1673 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1674 struct init_exec *iexec)
1677 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1679 * offset (8 bit): opcode
1680 * offset + 1 (8 bit): CRTC index1
1681 * offset + 2 (8 bit): CRTC index2
1682 * offset + 3 (8 bit): baseaddr
1683 * offset + 4 (8 bit): count
1684 * offset + 5 (8 bit): data 1
1687 * For each of "count" address and data pairs, write "baseaddr + n" to
1688 * "CRTC index1" and "data n" to "CRTC index2"
1689 * Once complete, restore initial value read from "CRTC index1"
1691 uint8_t crtcindex1 = bios->data[offset + 1];
1692 uint8_t crtcindex2 = bios->data[offset + 2];
1693 uint8_t baseaddr = bios->data[offset + 3];
1694 uint8_t count = bios->data[offset + 4];
1695 int len = 5 + count;
1696 uint8_t oldaddr, data;
1699 if (!iexec->execute)
1702 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1703 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1704 offset, crtcindex1, crtcindex2, baseaddr, count);
1706 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1708 for (i = 0; i < count; i++) {
1709 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1711 data = bios->data[offset + 5 + i];
1712 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1715 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1721 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1724 * INIT_CR opcode: 0x52 ('R')
1726 * offset (8 bit): opcode
1727 * offset + 1 (8 bit): CRTC index
1728 * offset + 2 (8 bit): mask
1729 * offset + 3 (8 bit): data
1731 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1732 * data back to "CRTC index"
1735 uint8_t crtcindex = bios->data[offset + 1];
1736 uint8_t mask = bios->data[offset + 2];
1737 uint8_t data = bios->data[offset + 3];
1740 if (!iexec->execute)
1743 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1744 offset, crtcindex, mask, data);
1746 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1748 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1754 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1757 * INIT_ZM_CR opcode: 0x53 ('S')
1759 * offset (8 bit): opcode
1760 * offset + 1 (8 bit): CRTC index
1761 * offset + 2 (8 bit): value
1763 * Assign "value" to CRTC register with index "CRTC index".
1766 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1767 uint8_t data = bios->data[offset + 2];
1769 if (!iexec->execute)
1772 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1778 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1781 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1783 * offset (8 bit): opcode
1784 * offset + 1 (8 bit): count
1785 * offset + 2 (8 bit): CRTC index 1
1786 * offset + 3 (8 bit): value 1
1789 * For "count", assign "value n" to CRTC register with index
1793 uint8_t count = bios->data[offset + 1];
1794 int len = 2 + count * 2;
1797 if (!iexec->execute)
1800 for (i = 0; i < count; i++)
1801 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1807 init_condition_time(struct nvbios *bios, uint16_t offset,
1808 struct init_exec *iexec)
1811 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1813 * offset (8 bit): opcode
1814 * offset + 1 (8 bit): condition number
1815 * offset + 2 (8 bit): retries / 50
1817 * Check condition "condition number" in the condition table.
1818 * Bios code then sleeps for 2ms if the condition is not met, and
1819 * repeats up to "retries" times, but on one C51 this has proved
1820 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1821 * this, and bail after "retries" times, or 2s, whichever is less.
1822 * If still not met after retries, clear execution flag for this table.
1825 uint8_t cond = bios->data[offset + 1];
1826 uint16_t retries = bios->data[offset + 2] * 50;
1829 if (!iexec->execute)
1835 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1836 offset, cond, retries);
1838 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1841 for (cnt = 0; cnt < retries; cnt++) {
1842 if (bios_condition_met(bios, offset, cond)) {
1843 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1847 BIOSLOG(bios, "0x%04X: "
1848 "Condition not met, sleeping for 20ms\n",
1854 if (!bios_condition_met(bios, offset, cond)) {
1856 "0x%04X: Condition still not met after %dms, "
1857 "skipping following opcodes\n", offset, 20 * retries);
1858 iexec->execute = false;
1865 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1868 * INIT_LTIME opcode: 0x57 ('V')
1870 * offset (8 bit): opcode
1871 * offset + 1 (16 bit): time
1873 * Sleep for "time" milliseconds.
1876 unsigned time = ROM16(bios->data[offset + 1]);
1878 if (!iexec->execute)
1881 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1890 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1891 struct init_exec *iexec)
1894 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1896 * offset (8 bit): opcode
1897 * offset + 1 (32 bit): base register
1898 * offset + 5 (8 bit): count
1899 * offset + 6 (32 bit): value 1
1902 * Starting at offset + 6 there are "count" 32 bit values.
1903 * For "count" iterations set "base register" + 4 * current_iteration
1904 * to "value current_iteration"
1907 uint32_t basereg = ROM32(bios->data[offset + 1]);
1908 uint32_t count = bios->data[offset + 5];
1909 int len = 6 + count * 4;
1912 if (!iexec->execute)
1915 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1916 offset, basereg, count);
1918 for (i = 0; i < count; i++) {
1919 uint32_t reg = basereg + i * 4;
1920 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1922 bios_wr32(bios, reg, data);
1929 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1932 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1934 * offset (8 bit): opcode
1935 * offset + 1 (16 bit): subroutine offset (in bios)
1937 * Calls a subroutine that will execute commands until INIT_DONE
1941 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1943 if (!iexec->execute)
1946 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1947 offset, sub_offset);
1949 parse_init_table(bios, sub_offset, iexec);
1951 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1957 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1960 * INIT_JUMP opcode: 0x5C ('\')
1962 * offset (8 bit): opcode
1963 * offset + 1 (16 bit): offset (in bios)
1965 * Continue execution of init table from 'offset'
1968 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1970 if (!iexec->execute)
1973 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1974 return jmp_offset - offset;
1978 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1981 * INIT_I2C_IF opcode: 0x5E ('^')
1983 * offset (8 bit): opcode
1984 * offset + 1 (8 bit): DCB I2C table entry index
1985 * offset + 2 (8 bit): I2C slave address
1986 * offset + 3 (8 bit): I2C register
1987 * offset + 4 (8 bit): mask
1988 * offset + 5 (8 bit): data
1990 * Read the register given by "I2C register" on the device addressed
1991 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1992 * entry index". Compare the result AND "mask" to "data".
1993 * If they're not equal, skip subsequent opcodes until condition is
1994 * inverted (INIT_NOT), or we hit INIT_RESUME
1997 uint8_t i2c_index = bios->data[offset + 1];
1998 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1999 uint8_t reg = bios->data[offset + 3];
2000 uint8_t mask = bios->data[offset + 4];
2001 uint8_t data = bios->data[offset + 5];
2002 struct nouveau_i2c_chan *chan;
2003 union i2c_smbus_data val;
2006 /* no execute check by design */
2008 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2009 offset, i2c_index, i2c_address);
2011 chan = init_i2c_device_find(bios->dev, i2c_index);
2015 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2016 I2C_SMBUS_READ, reg,
2017 I2C_SMBUS_BYTE_DATA, &val);
2019 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2020 "Mask: 0x%02X, Data: 0x%02X\n",
2021 offset, reg, mask, data);
2026 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2027 "Mask: 0x%02X, Data: 0x%02X\n",
2028 offset, reg, val.byte, mask, data);
2030 iexec->execute = ((val.byte & mask) == data);
2036 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2039 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2041 * offset (8 bit): opcode
2042 * offset + 1 (32 bit): src reg
2043 * offset + 5 (8 bit): shift
2044 * offset + 6 (32 bit): src mask
2045 * offset + 10 (32 bit): xor
2046 * offset + 14 (32 bit): dst reg
2047 * offset + 18 (32 bit): dst mask
2049 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2050 * "src mask", then XOR with "xor". Write this OR'd with
2051 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2054 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2055 uint8_t shift = bios->data[offset + 5];
2056 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2057 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2058 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2059 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2060 uint32_t srcvalue, dstvalue;
2062 if (!iexec->execute)
2065 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2066 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2067 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2069 srcvalue = bios_rd32(bios, srcreg);
2074 srcvalue <<= (0x100 - shift);
2076 srcvalue = (srcvalue & srcmask) ^ xor;
2078 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2080 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2086 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2089 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2091 * offset (8 bit): opcode
2092 * offset + 1 (16 bit): CRTC port
2093 * offset + 3 (8 bit): CRTC index
2094 * offset + 4 (8 bit): data
2096 * Write "data" to index "CRTC index" of "CRTC port"
2098 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2099 uint8_t crtcindex = bios->data[offset + 3];
2100 uint8_t data = bios->data[offset + 4];
2102 if (!iexec->execute)
2105 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2111 bios_md32(struct nvbios *bios, uint32_t reg,
2112 uint32_t mask, uint32_t val)
2114 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2118 peek_fb(struct drm_device *dev, struct io_mapping *fb,
2123 if (off < pci_resource_len(dev->pdev, 1)) {
2124 uint8_t __iomem *p =
2125 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2127 val = ioread32(p + (off & ~PAGE_MASK));
2129 io_mapping_unmap_atomic(p);
2136 poke_fb(struct drm_device *dev, struct io_mapping *fb,
2137 uint32_t off, uint32_t val)
2139 if (off < pci_resource_len(dev->pdev, 1)) {
2140 uint8_t __iomem *p =
2141 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
2143 iowrite32(val, p + (off & ~PAGE_MASK));
2146 io_mapping_unmap_atomic(p);
2151 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2152 uint32_t off, uint32_t val)
2154 poke_fb(dev, fb, off, val);
2155 return val == peek_fb(dev, fb, off);
2159 nv04_init_compute_mem(struct nvbios *bios)
2161 struct drm_device *dev = bios->dev;
2162 uint32_t patt = 0xdeadbeef;
2163 struct io_mapping *fb;
2166 /* Map the framebuffer aperture */
2167 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2168 pci_resource_len(dev->pdev, 1));
2172 /* Sequencer and refresh off */
2173 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2174 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2176 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2177 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2178 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2179 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2181 for (i = 0; i < 4; i++)
2182 poke_fb(dev, fb, 4 * i, patt);
2184 poke_fb(dev, fb, 0x400000, patt + 1);
2186 if (peek_fb(dev, fb, 0) == patt + 1) {
2187 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2188 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2189 bios_md32(bios, NV04_PFB_DEBUG_0,
2190 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2192 for (i = 0; i < 4; i++)
2193 poke_fb(dev, fb, 4 * i, patt);
2195 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2196 bios_md32(bios, NV04_PFB_BOOT_0,
2197 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2198 NV04_PFB_BOOT_0_RAM_AMOUNT,
2199 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2201 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2202 (patt & 0xffff0000)) {
2203 bios_md32(bios, NV04_PFB_BOOT_0,
2204 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2205 NV04_PFB_BOOT_0_RAM_AMOUNT,
2206 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2208 } else if (peek_fb(dev, fb, 0) != patt) {
2209 if (read_back_fb(dev, fb, 0x800000, patt))
2210 bios_md32(bios, NV04_PFB_BOOT_0,
2211 NV04_PFB_BOOT_0_RAM_AMOUNT,
2212 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2214 bios_md32(bios, NV04_PFB_BOOT_0,
2215 NV04_PFB_BOOT_0_RAM_AMOUNT,
2216 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2218 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2219 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2221 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2222 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2223 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2227 /* Refresh on, sequencer on */
2228 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2229 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2231 io_mapping_free(fb);
2235 static const uint8_t *
2236 nv05_memory_config(struct nvbios *bios)
2238 /* Defaults for BIOSes lacking a memory config table */
2239 static const uint8_t default_config_tab[][2] = {
2249 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2250 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2252 if (bios->legacy.mem_init_tbl_ptr)
2253 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2255 return default_config_tab[i];
2259 nv05_init_compute_mem(struct nvbios *bios)
2261 struct drm_device *dev = bios->dev;
2262 const uint8_t *ramcfg = nv05_memory_config(bios);
2263 uint32_t patt = 0xdeadbeef;
2264 struct io_mapping *fb;
2267 /* Map the framebuffer aperture */
2268 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2269 pci_resource_len(dev->pdev, 1));
2274 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2276 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2279 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2281 /* If present load the hardcoded scrambling table */
2282 if (bios->legacy.mem_init_tbl_ptr) {
2283 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2284 bios->legacy.mem_init_tbl_ptr + 0x10];
2286 for (i = 0; i < 8; i++)
2287 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2288 ROM32(scramble_tab[i]));
2291 /* Set memory type/width/length defaults depending on the straps */
2292 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2294 if (ramcfg[1] & 0x80)
2295 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2297 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2298 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2300 /* Probe memory bus width */
2301 for (i = 0; i < 4; i++)
2302 poke_fb(dev, fb, 4 * i, patt);
2304 if (peek_fb(dev, fb, 0xc) != patt)
2305 bios_md32(bios, NV04_PFB_BOOT_0,
2306 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2308 /* Probe memory length */
2309 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2311 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2312 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2313 !read_back_fb(dev, fb, 0, ++patt)))
2314 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2315 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2317 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2318 !read_back_fb(dev, fb, 0x800000, ++patt))
2319 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2320 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2322 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2323 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2324 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2328 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2330 io_mapping_free(fb);
2335 nv10_init_compute_mem(struct nvbios *bios)
2337 struct drm_device *dev = bios->dev;
2338 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2339 const int mem_width[] = { 0x10, 0x00, 0x20 };
2340 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2341 uint32_t patt = 0xdeadbeef;
2342 struct io_mapping *fb;
2345 /* Map the framebuffer aperture */
2346 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2347 pci_resource_len(dev->pdev, 1));
2351 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2353 /* Probe memory bus width */
2354 for (i = 0; i < mem_width_count; i++) {
2355 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2357 for (j = 0; j < 4; j++) {
2358 for (k = 0; k < 4; k++)
2359 poke_fb(dev, fb, 0x1c, 0);
2361 poke_fb(dev, fb, 0x1c, patt);
2362 poke_fb(dev, fb, 0x3c, 0);
2364 if (peek_fb(dev, fb, 0x1c) == patt)
2365 goto mem_width_found;
2372 /* Probe amount of installed memory */
2373 for (i = 0; i < 4; i++) {
2374 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2376 poke_fb(dev, fb, off, patt);
2377 poke_fb(dev, fb, 0, 0);
2379 peek_fb(dev, fb, 0);
2380 peek_fb(dev, fb, 0);
2381 peek_fb(dev, fb, 0);
2382 peek_fb(dev, fb, 0);
2384 if (peek_fb(dev, fb, off) == patt)
2388 /* IC missing - disable the upper half memory space. */
2389 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2392 io_mapping_free(fb);
2397 nv20_init_compute_mem(struct nvbios *bios)
2399 struct drm_device *dev = bios->dev;
2400 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2401 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2402 uint32_t amount, off;
2403 struct io_mapping *fb;
2405 /* Map the framebuffer aperture */
2406 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2407 pci_resource_len(dev->pdev, 1));
2411 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2413 /* Allow full addressing */
2414 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2416 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2417 for (off = amount; off > 0x2000000; off -= 0x2000000)
2418 poke_fb(dev, fb, off - 4, off);
2420 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2421 if (amount != peek_fb(dev, fb, amount - 4))
2422 /* IC missing - disable the upper half memory space. */
2423 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2425 io_mapping_free(fb);
2430 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2433 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2435 * offset (8 bit): opcode
2437 * This opcode is meant to set the PFB memory config registers
2438 * appropriately so that we can correctly calculate how much VRAM it
2439 * has (on nv10 and better chipsets the amount of installed VRAM is
2440 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2442 * The implementation of this opcode in general consists of several
2445 * 1) Determination of memory type and density. Only necessary for
2446 * really old chipsets, the memory type reported by the strap bits
2447 * (0x101000) is assumed to be accurate on nv05 and newer.
2449 * 2) Determination of the memory bus width. Usually done by a cunning
2450 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2451 * seeing whether the written values are read back correctly.
2453 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2456 * 3) Determination of how many of the card's RAM pads have ICs
2457 * attached, usually done by a cunning combination of writes to an
2458 * offset slightly less than the maximum memory reported by
2459 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2461 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2462 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2463 * card show nothing being done for this opcode. Why is it still listed
2467 /* no iexec->execute check by design */
2469 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2472 if (dev_priv->chipset >= 0x40 ||
2473 dev_priv->chipset == 0x1a ||
2474 dev_priv->chipset == 0x1f)
2476 else if (dev_priv->chipset >= 0x20 &&
2477 dev_priv->chipset != 0x34)
2478 ret = nv20_init_compute_mem(bios);
2479 else if (dev_priv->chipset >= 0x10)
2480 ret = nv10_init_compute_mem(bios);
2481 else if (dev_priv->chipset >= 0x5)
2482 ret = nv05_init_compute_mem(bios);
2484 ret = nv04_init_compute_mem(bios);
2493 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2496 * INIT_RESET opcode: 0x65 ('e')
2498 * offset (8 bit): opcode
2499 * offset + 1 (32 bit): register
2500 * offset + 5 (32 bit): value1
2501 * offset + 9 (32 bit): value2
2503 * Assign "value1" to "register", then assign "value2" to "register"
2506 uint32_t reg = ROM32(bios->data[offset + 1]);
2507 uint32_t value1 = ROM32(bios->data[offset + 5]);
2508 uint32_t value2 = ROM32(bios->data[offset + 9]);
2509 uint32_t pci_nv_19, pci_nv_20;
2511 /* no iexec->execute check by design */
2513 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2514 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2516 bios_wr32(bios, reg, value1);
2520 bios_wr32(bios, reg, value2);
2521 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2523 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2524 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2525 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2531 init_configure_mem(struct nvbios *bios, uint16_t offset,
2532 struct init_exec *iexec)
2535 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2537 * offset (8 bit): opcode
2539 * Equivalent to INIT_DONE on bios version 3 or greater.
2540 * For early bios versions, sets up the memory registers, using values
2541 * taken from the memory init table
2544 /* no iexec->execute check by design */
2546 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2547 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2550 if (bios->major_version > 2)
2553 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2554 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2556 if (bios->data[meminitoffs] & 1)
2557 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2559 for (reg = ROM32(bios->data[seqtbloffs]);
2561 reg = ROM32(bios->data[seqtbloffs += 4])) {
2565 data = NV04_PFB_PRE_CMD_PRECHARGE;
2568 data = NV04_PFB_PAD_CKE_NORMAL;
2571 data = NV04_PFB_REF_CMD_REFRESH;
2574 data = ROM32(bios->data[meminitdata]);
2576 if (data == 0xffffffff)
2580 bios_wr32(bios, reg, data);
2587 init_configure_clk(struct nvbios *bios, uint16_t offset,
2588 struct init_exec *iexec)
2591 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2593 * offset (8 bit): opcode
2595 * Equivalent to INIT_DONE on bios version 3 or greater.
2596 * For early bios versions, sets up the NVClk and MClk PLLs, using
2597 * values taken from the memory init table
2600 /* no iexec->execute check by design */
2602 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2605 if (bios->major_version > 2)
2608 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2609 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2611 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2612 if (bios->data[meminitoffs] & 1) /* DDR */
2614 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2620 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2621 struct init_exec *iexec)
2624 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2626 * offset (8 bit): opcode
2628 * Equivalent to INIT_DONE on bios version 3 or greater.
2629 * For early bios versions, does early init, loading ram and crystal
2630 * configuration from straps into CR3C
2633 /* no iexec->execute check by design */
2635 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2636 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2638 if (bios->major_version > 2)
2641 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2642 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2648 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2651 * INIT_IO opcode: 0x69 ('i')
2653 * offset (8 bit): opcode
2654 * offset + 1 (16 bit): CRTC port
2655 * offset + 3 (8 bit): mask
2656 * offset + 4 (8 bit): data
2658 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2661 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2662 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2663 uint8_t mask = bios->data[offset + 3];
2664 uint8_t data = bios->data[offset + 4];
2666 if (!iexec->execute)
2669 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2670 offset, crtcport, mask, data);
2673 * I have no idea what this does, but NVIDIA do this magic sequence
2674 * in the places where this INIT_IO happens..
2676 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2679 bios_wr32(bios, 0x614100, (bios_rd32(
2680 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2682 bios_wr32(bios, 0x00e18c, bios_rd32(
2683 bios, 0x00e18c) | 0x00020000);
2685 bios_wr32(bios, 0x614900, (bios_rd32(
2686 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2688 bios_wr32(bios, 0x000200, bios_rd32(
2689 bios, 0x000200) & ~0x40000000);
2693 bios_wr32(bios, 0x00e18c, bios_rd32(
2694 bios, 0x00e18c) & ~0x00020000);
2696 bios_wr32(bios, 0x000200, bios_rd32(
2697 bios, 0x000200) | 0x40000000);
2699 bios_wr32(bios, 0x614100, 0x00800018);
2700 bios_wr32(bios, 0x614900, 0x00800018);
2704 bios_wr32(bios, 0x614100, 0x10000018);
2705 bios_wr32(bios, 0x614900, 0x10000018);
2707 for (i = 0; i < 3; i++)
2708 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2709 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2711 for (i = 0; i < 2; i++)
2712 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2713 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2715 for (i = 0; i < 3; i++)
2716 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2717 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2719 for (i = 0; i < 2; i++)
2720 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2721 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2723 for (i = 0; i < 2; i++)
2724 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2725 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2729 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2735 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2738 * INIT_SUB opcode: 0x6B ('k')
2740 * offset (8 bit): opcode
2741 * offset + 1 (8 bit): script number
2743 * Execute script number "script number", as a subroutine
2746 uint8_t sub = bios->data[offset + 1];
2748 if (!iexec->execute)
2751 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2753 parse_init_table(bios,
2754 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2757 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2763 init_ram_condition(struct nvbios *bios, uint16_t offset,
2764 struct init_exec *iexec)
2767 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2769 * offset (8 bit): opcode
2770 * offset + 1 (8 bit): mask
2771 * offset + 2 (8 bit): cmpval
2773 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2774 * If condition not met skip subsequent opcodes until condition is
2775 * inverted (INIT_NOT), or we hit INIT_RESUME
2778 uint8_t mask = bios->data[offset + 1];
2779 uint8_t cmpval = bios->data[offset + 2];
2782 if (!iexec->execute)
2785 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2787 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2788 offset, data, cmpval);
2791 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2793 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2794 iexec->execute = false;
2801 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2804 * INIT_NV_REG opcode: 0x6E ('n')
2806 * offset (8 bit): opcode
2807 * offset + 1 (32 bit): register
2808 * offset + 5 (32 bit): mask
2809 * offset + 9 (32 bit): data
2811 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2814 uint32_t reg = ROM32(bios->data[offset + 1]);
2815 uint32_t mask = ROM32(bios->data[offset + 5]);
2816 uint32_t data = ROM32(bios->data[offset + 9]);
2818 if (!iexec->execute)
2821 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2822 offset, reg, mask, data);
2824 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2830 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2833 * INIT_MACRO opcode: 0x6F ('o')
2835 * offset (8 bit): opcode
2836 * offset + 1 (8 bit): macro number
2838 * Look up macro index "macro number" in the macro index table.
2839 * The macro index table entry has 1 byte for the index in the macro
2840 * table, and 1 byte for the number of times to repeat the macro.
2841 * The macro table entry has 4 bytes for the register address and
2842 * 4 bytes for the value to write to that register
2845 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2846 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2847 uint8_t macro_tbl_idx = bios->data[tmp];
2848 uint8_t count = bios->data[tmp + 1];
2852 if (!iexec->execute)
2855 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2857 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2859 for (i = 0; i < count; i++) {
2860 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2862 reg = ROM32(bios->data[macroentryptr]);
2863 data = ROM32(bios->data[macroentryptr + 4]);
2865 bios_wr32(bios, reg, data);
2872 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2875 * INIT_DONE opcode: 0x71 ('q')
2877 * offset (8 bit): opcode
2879 * End the current script
2882 /* mild retval abuse to stop parsing this table */
2887 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2890 * INIT_RESUME opcode: 0x72 ('r')
2892 * offset (8 bit): opcode
2894 * End the current execute / no-execute condition
2900 iexec->execute = true;
2901 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2907 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2910 * INIT_TIME opcode: 0x74 ('t')
2912 * offset (8 bit): opcode
2913 * offset + 1 (16 bit): time
2915 * Sleep for "time" microseconds.
2918 unsigned time = ROM16(bios->data[offset + 1]);
2920 if (!iexec->execute)
2923 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2929 mdelay((time + 900) / 1000);
2935 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2938 * INIT_CONDITION opcode: 0x75 ('u')
2940 * offset (8 bit): opcode
2941 * offset + 1 (8 bit): condition number
2943 * Check condition "condition number" in the condition table.
2944 * If condition not met skip subsequent opcodes until condition is
2945 * inverted (INIT_NOT), or we hit INIT_RESUME
2948 uint8_t cond = bios->data[offset + 1];
2950 if (!iexec->execute)
2953 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2955 if (bios_condition_met(bios, offset, cond))
2956 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2958 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2959 iexec->execute = false;
2966 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2969 * INIT_IO_CONDITION opcode: 0x76
2971 * offset (8 bit): opcode
2972 * offset + 1 (8 bit): condition number
2974 * Check condition "condition number" in the io condition table.
2975 * If condition not met skip subsequent opcodes until condition is
2976 * inverted (INIT_NOT), or we hit INIT_RESUME
2979 uint8_t cond = bios->data[offset + 1];
2981 if (!iexec->execute)
2984 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2986 if (io_condition_met(bios, offset, cond))
2987 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2989 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2990 iexec->execute = false;
2997 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3000 * INIT_INDEX_IO opcode: 0x78 ('x')
3002 * offset (8 bit): opcode
3003 * offset + 1 (16 bit): CRTC port
3004 * offset + 3 (8 bit): CRTC index
3005 * offset + 4 (8 bit): mask
3006 * offset + 5 (8 bit): data
3008 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3009 * OR with "data", write-back
3012 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3013 uint8_t crtcindex = bios->data[offset + 3];
3014 uint8_t mask = bios->data[offset + 4];
3015 uint8_t data = bios->data[offset + 5];
3018 if (!iexec->execute)
3021 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3023 offset, crtcport, crtcindex, mask, data);
3025 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3026 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3032 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3035 * INIT_PLL opcode: 0x79 ('y')
3037 * offset (8 bit): opcode
3038 * offset + 1 (32 bit): register
3039 * offset + 5 (16 bit): freq
3041 * Set PLL register "register" to coefficients for frequency (10kHz)
3045 uint32_t reg = ROM32(bios->data[offset + 1]);
3046 uint16_t freq = ROM16(bios->data[offset + 5]);
3048 if (!iexec->execute)
3051 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3053 setPLL(bios, reg, freq * 10);
3059 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3062 * INIT_ZM_REG opcode: 0x7A ('z')
3064 * offset (8 bit): opcode
3065 * offset + 1 (32 bit): register
3066 * offset + 5 (32 bit): value
3068 * Assign "value" to "register"
3071 uint32_t reg = ROM32(bios->data[offset + 1]);
3072 uint32_t value = ROM32(bios->data[offset + 5]);
3074 if (!iexec->execute)
3077 if (reg == 0x000200)
3080 bios_wr32(bios, reg, value);
3086 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3087 struct init_exec *iexec)
3090 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3092 * offset (8 bit): opcode
3093 * offset + 1 (8 bit): PLL type
3094 * offset + 2 (32 bit): frequency 0
3096 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3097 * ram_restrict_table_ptr. The value read from there is used to select
3098 * a frequency from the table starting at 'frequency 0' to be
3099 * programmed into the PLL corresponding to 'type'.
3101 * The PLL limits table on cards using this opcode has a mapping of
3102 * 'type' to the relevant registers.
3105 struct drm_device *dev = bios->dev;
3106 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3107 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3108 uint8_t type = bios->data[offset + 1];
3109 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3110 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
3111 int len = 2 + bios->ram_restrict_group_count * 4;
3114 if (!iexec->execute)
3117 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3118 NV_ERROR(dev, "PLL limits table not version 3.x\n");
3119 return len; /* deliberate, allow default clocks to remain */
3122 entry = pll_limits + pll_limits[1];
3123 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3124 if (entry[0] == type) {
3125 uint32_t reg = ROM32(entry[3]);
3127 BIOSLOG(bios, "0x%04X: "
3128 "Type %02x Reg 0x%08x Freq %dKHz\n",
3129 offset, type, reg, freq);
3131 setPLL(bios, reg, freq);
3136 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
3141 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3144 * INIT_8C opcode: 0x8C ('')
3154 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3157 * INIT_8D opcode: 0x8D ('')
3167 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3170 * INIT_GPIO opcode: 0x8E ('')
3172 * offset (8 bit): opcode
3174 * Loop over all entries in the DCB GPIO table, and initialise
3175 * each GPIO according to various values listed in each entry
3178 if (iexec->execute && bios->execute)
3179 nouveau_gpio_reset(bios->dev);
3185 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3186 struct init_exec *iexec)
3189 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3191 * offset (8 bit): opcode
3192 * offset + 1 (32 bit): reg
3193 * offset + 5 (8 bit): regincrement
3194 * offset + 6 (8 bit): count
3195 * offset + 7 (32 bit): value 1,1
3198 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3199 * ram_restrict_table_ptr. The value read from here is 'n', and
3200 * "value 1,n" gets written to "reg". This repeats "count" times and on
3201 * each iteration 'm', "reg" increases by "regincrement" and
3202 * "value m,n" is used. The extent of n is limited by a number read
3203 * from the 'M' BIT table, herein called "blocklen"
3206 uint32_t reg = ROM32(bios->data[offset + 1]);
3207 uint8_t regincrement = bios->data[offset + 5];
3208 uint8_t count = bios->data[offset + 6];
3209 uint32_t strap_ramcfg, data;
3210 /* previously set by 'M' BIT table */
3211 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3212 int len = 7 + count * blocklen;
3216 /* critical! to know the length of the opcode */;
3219 "0x%04X: Zero block length - has the M table "
3220 "been parsed?\n", offset);
3224 if (!iexec->execute)
3227 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3228 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3230 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3231 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3232 offset, reg, regincrement, count, strap_ramcfg, index);
3234 for (i = 0; i < count; i++) {
3235 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3237 bios_wr32(bios, reg, data);
3239 reg += regincrement;
3246 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3249 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3251 * offset (8 bit): opcode
3252 * offset + 1 (32 bit): src reg
3253 * offset + 5 (32 bit): dst reg
3255 * Put contents of "src reg" into "dst reg"
3258 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3259 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3261 if (!iexec->execute)
3264 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3270 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3271 struct init_exec *iexec)
3274 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3276 * offset (8 bit): opcode
3277 * offset + 1 (32 bit): dst reg
3278 * offset + 5 (8 bit): count
3279 * offset + 6 (32 bit): data 1
3282 * For each of "count" values write "data n" to "dst reg"
3285 uint32_t reg = ROM32(bios->data[offset + 1]);
3286 uint8_t count = bios->data[offset + 5];
3287 int len = 6 + count * 4;
3290 if (!iexec->execute)
3293 for (i = 0; i < count; i++) {
3294 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3295 bios_wr32(bios, reg, data);
3302 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3305 * INIT_RESERVED opcode: 0x92 ('')
3307 * offset (8 bit): opcode
3309 * Seemingly does nothing
3316 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3319 * INIT_96 opcode: 0x96 ('')
3321 * offset (8 bit): opcode
3322 * offset + 1 (32 bit): sreg
3323 * offset + 5 (8 bit): sshift
3324 * offset + 6 (8 bit): smask
3325 * offset + 7 (8 bit): index
3326 * offset + 8 (32 bit): reg
3327 * offset + 12 (32 bit): mask
3328 * offset + 16 (8 bit): shift
3332 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3333 uint32_t reg = ROM32(bios->data[offset + 8]);
3334 uint32_t mask = ROM32(bios->data[offset + 12]);
3337 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3338 if (bios->data[offset + 5] < 0x80)
3339 val >>= bios->data[offset + 5];
3341 val <<= (0x100 - bios->data[offset + 5]);
3342 val &= bios->data[offset + 6];
3344 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3345 val <<= bios->data[offset + 16];
3347 if (!iexec->execute)
3350 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3355 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3358 * INIT_97 opcode: 0x97 ('')
3360 * offset (8 bit): opcode
3361 * offset + 1 (32 bit): register
3362 * offset + 5 (32 bit): mask
3363 * offset + 9 (32 bit): value
3365 * Adds "value" to "register" preserving the fields specified
3369 uint32_t reg = ROM32(bios->data[offset + 1]);
3370 uint32_t mask = ROM32(bios->data[offset + 5]);
3371 uint32_t add = ROM32(bios->data[offset + 9]);
3374 val = bios_rd32(bios, reg);
3375 val = (val & mask) | ((val + add) & ~mask);
3377 if (!iexec->execute)
3380 bios_wr32(bios, reg, val);
3385 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3388 * INIT_AUXCH opcode: 0x98 ('')
3390 * offset (8 bit): opcode
3391 * offset + 1 (32 bit): address
3392 * offset + 5 (8 bit): count
3393 * offset + 6 (8 bit): mask 0
3394 * offset + 7 (8 bit): data 0
3399 struct drm_device *dev = bios->dev;
3400 struct nouveau_i2c_chan *auxch;
3401 uint32_t addr = ROM32(bios->data[offset + 1]);
3402 uint8_t count = bios->data[offset + 5];
3403 int len = 6 + count * 2;
3406 if (!bios->display.output) {
3407 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3411 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3413 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3414 bios->display.output->i2c_index);
3418 if (!iexec->execute)
3422 for (i = 0; i < count; i++, offset += 2) {
3425 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3427 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3431 data &= bios->data[offset + 0];
3432 data |= bios->data[offset + 1];
3434 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3436 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3445 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3448 * INIT_ZM_AUXCH opcode: 0x99 ('')
3450 * offset (8 bit): opcode
3451 * offset + 1 (32 bit): address
3452 * offset + 5 (8 bit): count
3453 * offset + 6 (8 bit): data 0
3458 struct drm_device *dev = bios->dev;
3459 struct nouveau_i2c_chan *auxch;
3460 uint32_t addr = ROM32(bios->data[offset + 1]);
3461 uint8_t count = bios->data[offset + 5];
3462 int len = 6 + count;
3465 if (!bios->display.output) {
3466 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3470 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3472 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3473 bios->display.output->i2c_index);
3477 if (!iexec->execute)
3481 for (i = 0; i < count; i++, offset++) {
3482 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3484 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3493 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3496 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3498 * offset (8 bit): opcode
3499 * offset + 1 (8 bit): DCB I2C table entry index
3500 * offset + 2 (8 bit): I2C slave address
3501 * offset + 3 (16 bit): I2C register
3502 * offset + 5 (8 bit): mask
3503 * offset + 6 (8 bit): data
3505 * Read the register given by "I2C register" on the device addressed
3506 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3507 * entry index". Compare the result AND "mask" to "data".
3508 * If they're not equal, skip subsequent opcodes until condition is
3509 * inverted (INIT_NOT), or we hit INIT_RESUME
3512 uint8_t i2c_index = bios->data[offset + 1];
3513 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3514 uint8_t reglo = bios->data[offset + 3];
3515 uint8_t reghi = bios->data[offset + 4];
3516 uint8_t mask = bios->data[offset + 5];
3517 uint8_t data = bios->data[offset + 6];
3518 struct nouveau_i2c_chan *chan;
3519 uint8_t buf0[2] = { reghi, reglo };
3521 struct i2c_msg msg[2] = {
3522 { i2c_address, 0, 1, buf0 },
3523 { i2c_address, I2C_M_RD, 1, buf1 },
3527 /* no execute check by design */
3529 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3530 offset, i2c_index, i2c_address);
3532 chan = init_i2c_device_find(bios->dev, i2c_index);
3537 ret = i2c_transfer(&chan->adapter, msg, 2);
3539 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3540 "Mask: 0x%02X, Data: 0x%02X\n",
3541 offset, reghi, reglo, mask, data);
3546 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3547 "Mask: 0x%02X, Data: 0x%02X\n",
3548 offset, reghi, reglo, buf1[0], mask, data);
3550 iexec->execute = ((buf1[0] & mask) == data);
3555 static struct init_tbl_entry itbl_entry[] = {
3556 /* command name , id , length , offset , mult , command handler */
3557 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3558 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3559 { "INIT_REPEAT" , 0x33, init_repeat },
3560 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3561 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3562 { "INIT_COPY" , 0x37, init_copy },
3563 { "INIT_NOT" , 0x38, init_not },
3564 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3565 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3566 { "INIT_OP_3B" , 0x3B, init_op_3b },
3567 { "INIT_OP_3C" , 0x3C, init_op_3c },
3568 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3569 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3570 { "INIT_PLL2" , 0x4B, init_pll2 },
3571 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3572 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3573 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3574 { "INIT_TMDS" , 0x4F, init_tmds },
3575 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3576 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3577 { "INIT_CR" , 0x52, init_cr },
3578 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3579 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3580 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3581 { "INIT_LTIME" , 0x57, init_ltime },
3582 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3583 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3584 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3585 { "INIT_JUMP" , 0x5C, init_jump },
3586 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3587 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3588 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3589 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3590 { "INIT_RESET" , 0x65, init_reset },
3591 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3592 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3593 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3594 { "INIT_IO" , 0x69, init_io },
3595 { "INIT_SUB" , 0x6B, init_sub },
3596 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3597 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3598 { "INIT_MACRO" , 0x6F, init_macro },
3599 { "INIT_DONE" , 0x71, init_done },
3600 { "INIT_RESUME" , 0x72, init_resume },
3601 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3602 { "INIT_TIME" , 0x74, init_time },
3603 { "INIT_CONDITION" , 0x75, init_condition },
3604 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3605 { "INIT_INDEX_IO" , 0x78, init_index_io },
3606 { "INIT_PLL" , 0x79, init_pll },
3607 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3608 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3609 { "INIT_8C" , 0x8C, init_8c },
3610 { "INIT_8D" , 0x8D, init_8d },
3611 { "INIT_GPIO" , 0x8E, init_gpio },
3612 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3613 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3614 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3615 { "INIT_RESERVED" , 0x92, init_reserved },
3616 { "INIT_96" , 0x96, init_96 },
3617 { "INIT_97" , 0x97, init_97 },
3618 { "INIT_AUXCH" , 0x98, init_auxch },
3619 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3620 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3624 #define MAX_TABLE_OPS 1000
3627 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3630 * Parses all commands in an init table.
3632 * We start out executing all commands found in the init table. Some
3633 * opcodes may change the status of iexec->execute to SKIP, which will
3634 * cause the following opcodes to perform no operation until the value
3635 * is changed back to EXECUTE.
3638 int count = 0, i, ret;
3641 /* catch NULL script pointers */
3646 * Loop until INIT_DONE causes us to break out of the loop
3647 * (or until offset > bios length just in case... )
3648 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3650 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3651 id = bios->data[offset];
3653 /* Find matching id in itbl_entry */
3654 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3657 if (!itbl_entry[i].name) {
3659 "0x%04X: Init table command not found: "
3660 "0x%02X\n", offset, id);
3664 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3665 itbl_entry[i].id, itbl_entry[i].name);
3667 /* execute eventual command handler */
3668 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3670 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3671 "table opcode: %s %d\n", offset,
3672 itbl_entry[i].name, ret);
3679 * Add the offset of the current command including all data
3680 * of that command. The offset will then be pointing on the
3686 if (offset >= bios->length)
3688 "Offset 0x%04X greater than known bios image length. "
3689 "Corrupt image?\n", offset);
3690 if (count >= MAX_TABLE_OPS)
3692 "More than %d opcodes to a table is unlikely, "
3693 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3699 parse_init_tables(struct nvbios *bios)
3701 /* Loops and calls parse_init_table() for each present table. */
3705 struct init_exec iexec = {true, false};
3707 if (bios->old_style_init) {
3708 if (bios->init_script_tbls_ptr)
3709 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3710 if (bios->extra_init_script_tbl_ptr)
3711 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3716 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3718 "Parsing VBIOS init table %d at offset 0x%04X\n",
3720 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3722 parse_init_table(bios, table, &iexec);
3727 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3729 int compare_record_len, i = 0;
3730 uint16_t compareclk, scriptptr = 0;
3732 if (bios->major_version < 5) /* pre BIT */
3733 compare_record_len = 3;
3735 compare_record_len = 4;
3738 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3739 if (pxclk >= compareclk * 10) {
3740 if (bios->major_version < 5) {
3741 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3742 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3744 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3748 } while (compareclk);
3754 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3755 struct dcb_entry *dcbent, int head, bool dl)
3757 struct drm_nouveau_private *dev_priv = dev->dev_private;
3758 struct nvbios *bios = &dev_priv->vbios;
3759 struct init_exec iexec = {true, false};
3761 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3763 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3764 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3765 /* note: if dcb entries have been merged, index may be misleading */
3766 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3767 parse_init_table(bios, scriptptr, &iexec);
3769 nv04_dfp_bind_head(dev, dcbent, head, dl);
3772 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3774 struct drm_nouveau_private *dev_priv = dev->dev_private;
3775 struct nvbios *bios = &dev_priv->vbios;
3776 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3777 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3779 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3782 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3784 if (script == LVDS_PANEL_OFF) {
3785 /* off-on delay in ms */
3786 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3789 /* Powerbook specific quirks */
3790 if (script == LVDS_RESET &&
3791 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3792 dev->pci_device == 0x0329))
3793 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3799 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3802 * The BIT LVDS table's header has the information to setup the
3803 * necessary registers. Following the standard 4 byte header are:
3804 * A bitmask byte and a dual-link transition pxclk value for use in
3805 * selecting the init script when not using straps; 4 script pointers
3806 * for panel power, selected by output and on/off; and 8 table pointers
3807 * for panel init, the needed one determined by output, and bits in the
3808 * conf byte. These tables are similar to the TMDS tables, consisting
3809 * of a list of pxclks and script pointers.
3811 struct drm_nouveau_private *dev_priv = dev->dev_private;
3812 struct nvbios *bios = &dev_priv->vbios;
3813 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3814 uint16_t scriptptr = 0, clktable;
3817 * For now we assume version 3.0 table - g80 support will need some
3824 case LVDS_BACKLIGHT_ON:
3826 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3828 case LVDS_BACKLIGHT_OFF:
3829 case LVDS_PANEL_OFF:
3830 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3833 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3834 if (dcbent->or == 4)
3837 if (dcbent->lvdsconf.use_straps_for_mode) {
3838 if (bios->fp.dual_link)
3840 if (bios->fp.if_is_24bit)
3844 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3846 if (bios->fp.dual_link) {
3851 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3855 clktable = ROM16(bios->data[clktable]);
3857 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3860 scriptptr = clkcmptable(bios, clktable, pxclk);
3864 NV_ERROR(dev, "LVDS output init script not found\n");
3867 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3872 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3875 * LVDS operations are multiplexed in an effort to present a single API
3876 * which works with two vastly differing underlying structures.
3877 * This acts as the demux
3880 struct drm_nouveau_private *dev_priv = dev->dev_private;
3881 struct nvbios *bios = &dev_priv->vbios;
3882 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3883 uint32_t sel_clk_binding, sel_clk;
3886 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3887 (lvds_ver >= 0x30 && script == LVDS_INIT))
3890 if (!bios->fp.lvds_init_run) {
3891 bios->fp.lvds_init_run = true;
3892 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3895 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3896 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3897 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3898 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3900 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3902 /* don't let script change pll->head binding */
3903 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3905 if (lvds_ver < 0x30)
3906 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3908 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3910 bios->fp.last_script_invoc = (script << 1 | head);
3912 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3913 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3914 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3915 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3920 struct lvdstableheader {
3921 uint8_t lvds_ver, headerlen, recordlen;
3924 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3927 * BMP version (0xa) LVDS table has a simple header of version and
3928 * record length. The BIT LVDS table has the typical BIT table header:
3929 * version byte, header length byte, record length byte, and a byte for
3930 * the maximum number of records that can be held in the table.
3933 uint8_t lvds_ver, headerlen, recordlen;
3935 memset(lth, 0, sizeof(struct lvdstableheader));
3937 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3938 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3942 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3945 case 0x0a: /* pre NV40 */
3947 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3949 case 0x30: /* NV4x */
3950 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3951 if (headerlen < 0x1f) {
3952 NV_ERROR(dev, "LVDS table header not understood\n");
3955 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3957 case 0x40: /* G80/G90 */
3958 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3959 if (headerlen < 0x7) {
3960 NV_ERROR(dev, "LVDS table header not understood\n");
3963 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3967 "LVDS table revision %d.%d not currently supported\n",
3968 lvds_ver >> 4, lvds_ver & 0xf);
3972 lth->lvds_ver = lvds_ver;
3973 lth->headerlen = headerlen;
3974 lth->recordlen = recordlen;
3980 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3982 struct drm_nouveau_private *dev_priv = dev->dev_private;
3985 * The fp strap is normally dictated by the "User Strap" in
3986 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3987 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3988 * by the PCI subsystem ID during POST, but not before the previous user
3989 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3990 * read and used instead
3993 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3994 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3996 if (dev_priv->card_type >= NV_50)
3997 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3999 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4002 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4005 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4006 int ret, ofs, fpstrapping;
4007 struct lvdstableheader lth;
4009 if (bios->fp.fptablepointer == 0x0) {
4010 /* Apple cards don't have the fp table; the laptops use DDC */
4011 /* The table is also missing on some x86 IGPs */
4013 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4015 bios->digital_min_front_porch = 0x4b;
4019 fptable = &bios->data[bios->fp.fptablepointer];
4020 fptable_ver = fptable[0];
4022 switch (fptable_ver) {
4024 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4025 * version field, and miss one of the spread spectrum/PWM bytes.
4026 * This could affect early GF2Go parts (not seen any appropriate ROMs
4027 * though). Here we assume that a version of 0x05 matches this case
4028 * (combining with a BMP version check would be better), as the
4029 * common case for the panel type field is 0x0005, and that is in
4030 * fact what we are reading the first byte of.
4032 case 0x05: /* some NV10, 11, 15, 16 */
4036 case 0x10: /* some NV15/16, and NV11+ */
4040 case 0x20: /* NV40+ */
4041 headerlen = fptable[1];
4042 recordlen = fptable[2];
4043 fpentries = fptable[3];
4045 * fptable[4] is the minimum
4046 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4048 bios->digital_min_front_porch = fptable[4];
4053 "FP table revision %d.%d not currently supported\n",
4054 fptable_ver >> 4, fptable_ver & 0xf);
4058 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4061 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4065 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4066 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4068 bios->fp.xlatwidth = lth.recordlen;
4070 if (bios->fp.fpxlatetableptr == 0x0) {
4071 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4075 fpstrapping = get_fp_strap(dev, bios);
4077 fpindex = bios->data[bios->fp.fpxlatetableptr +
4078 fpstrapping * bios->fp.xlatwidth];
4080 if (fpindex > fpentries) {
4081 NV_ERROR(dev, "Bad flat panel table index\n");
4085 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4086 if (lth.lvds_ver > 0x10)
4087 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
4090 * If either the strap or xlated fpindex value are 0xf there is no
4091 * panel using a strap-derived bios mode present. this condition
4092 * includes, but is different from, the DDC panel indicator above
4094 if (fpstrapping == 0xf || fpindex == 0xf)
4097 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4098 recordlen * fpindex + ofs;
4100 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4101 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4102 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4103 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4108 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4110 struct drm_nouveau_private *dev_priv = dev->dev_private;
4111 struct nvbios *bios = &dev_priv->vbios;
4112 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4114 if (!mode) /* just checking whether we can produce a mode */
4115 return bios->fp.mode_ptr;
4117 memset(mode, 0, sizeof(struct drm_display_mode));
4119 * For version 1.0 (version in byte 0):
4120 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4121 * single/dual link, and type (TFT etc.)
4122 * bytes 3-6 are bits per colour in RGBX
4124 mode->clock = ROM16(mode_entry[7]) * 10;
4125 /* bytes 9-10 is HActive */
4126 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4128 * bytes 13-14 is HValid Start
4129 * bytes 15-16 is HValid End
4131 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4132 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4133 mode->htotal = ROM16(mode_entry[21]) + 1;
4134 /* bytes 23-24, 27-30 similarly, but vertical */
4135 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4136 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4137 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4138 mode->vtotal = ROM16(mode_entry[35]) + 1;
4139 mode->flags |= (mode_entry[37] & 0x10) ?
4140 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4141 mode->flags |= (mode_entry[37] & 0x1) ?
4142 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4144 * bytes 38-39 relate to spread spectrum settings
4145 * bytes 40-43 are something to do with PWM
4148 mode->status = MODE_OK;
4149 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4150 drm_mode_set_name(mode);
4151 return bios->fp.mode_ptr;
4154 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4157 * The LVDS table header is (mostly) described in
4158 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4159 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4160 * straps are not being used for the panel, this specifies the frequency
4161 * at which modes should be set up in the dual link style.
4163 * Following the header, the BMP (ver 0xa) table has several records,
4164 * indexed by a separate xlat table, indexed in turn by the fp strap in
4165 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4166 * numbers for use by INIT_SUB which controlled panel init and power,
4167 * and finally a dword of ms to sleep between power off and on
4170 * In the BIT versions, the table following the header serves as an
4171 * integrated config and xlat table: the records in the table are
4172 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4173 * two bytes - the first as a config byte, the second for indexing the
4174 * fp mode table pointed to by the BIT 'D' table
4176 * DDC is not used until after card init, so selecting the correct table
4177 * entry and setting the dual link flag for EDID equipped panels,
4178 * requiring tests against the native-mode pixel clock, cannot be done
4179 * until later, when this function should be called with non-zero pxclk
4181 struct drm_nouveau_private *dev_priv = dev->dev_private;
4182 struct nvbios *bios = &dev_priv->vbios;
4183 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4184 struct lvdstableheader lth;
4186 int ret, chip_version = bios->chip_version;
4188 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
4192 switch (lth.lvds_ver) {
4193 case 0x0a: /* pre NV40 */
4194 lvdsmanufacturerindex = bios->data[
4195 bios->fp.fpxlatemanufacturertableptr +
4198 /* we're done if this isn't the EDID panel case */
4202 if (chip_version < 0x25) {
4205 * It seems the old style lvds script pointer is reused
4206 * to select 18/24 bit colour depth for EDID panels.
4208 lvdsmanufacturerindex =
4209 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4211 if (pxclk >= bios->fp.duallink_transition_clk)
4212 lvdsmanufacturerindex++;
4213 } else if (chip_version < 0x30) {
4214 /* nv28 behaviour (off-chip encoder)
4216 * nv28 does a complex dance of first using byte 121 of
4217 * the EDID to choose the lvdsmanufacturerindex, then
4218 * later attempting to match the EDID manufacturer and
4219 * product IDs in a table (signature 'pidt' (panel id
4220 * table?)), setting an lvdsmanufacturerindex of 0 and
4221 * an fp strap of the match index (or 0xf if none)
4223 lvdsmanufacturerindex = 0;
4225 /* nv31, nv34 behaviour */
4226 lvdsmanufacturerindex = 0;
4227 if (pxclk >= bios->fp.duallink_transition_clk)
4228 lvdsmanufacturerindex = 2;
4229 if (pxclk >= 140000)
4230 lvdsmanufacturerindex = 3;
4234 * nvidia set the high nibble of (cr57=f, cr58) to
4235 * lvdsmanufacturerindex in this case; we don't
4238 case 0x30: /* NV4x */
4239 case 0x40: /* G80/G90 */
4240 lvdsmanufacturerindex = fpstrapping;
4243 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4247 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4248 switch (lth.lvds_ver) {
4250 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4251 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4252 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4253 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4254 *if_is_24bit = bios->data[lvdsofs] & 16;
4259 * No sign of the "power off for reset" or "reset for panel
4260 * on" bits, but it's safer to assume we should
4262 bios->fp.power_off_for_reset = true;
4263 bios->fp.reset_after_pclk_change = true;
4266 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4267 * over-written, and if_is_24bit isn't used
4269 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4270 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4271 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4272 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4276 /* set dual_link flag for EDID case */
4277 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4278 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4280 *dl = bios->fp.dual_link;
4285 /* BIT 'U'/'d' table encoder subtables have hashes matching them to
4286 * a particular set of encoders.
4288 * This function returns true if a particular DCB entry matches.
4291 bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4293 if ((hash & 0x000000f0) != (dcb->location << 4))
4295 if ((hash & 0x0000000f) != dcb->type)
4297 if (!(hash & (dcb->or << 16)))
4300 switch (dcb->type) {
4304 if (hash & 0x00c00000) {
4305 if (!(hash & (dcb->sorconf.link << 22)))
4314 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4315 struct dcb_entry *dcbent, int crtc)
4318 * The display script table is located by the BIT 'U' table.
4320 * It contains an array of pointers to various tables describing
4321 * a particular output type. The first 32-bits of the output
4322 * tables contains similar information to a DCB entry, and is
4323 * used to decide whether that particular table is suitable for
4324 * the output you want to access.
4326 * The "record header length" field here seems to indicate the
4327 * offset of the first configuration entry in the output tables.
4328 * This is 10 on most cards I've seen, but 12 has been witnessed
4329 * on DP cards, and there's another script pointer within the
4332 * offset + 0 ( 8 bits): version
4333 * offset + 1 ( 8 bits): header length
4334 * offset + 2 ( 8 bits): record length
4335 * offset + 3 ( 8 bits): number of records
4336 * offset + 4 ( 8 bits): record header length
4337 * offset + 5 (16 bits): pointer to first output script table
4340 struct drm_nouveau_private *dev_priv = dev->dev_private;
4341 struct nvbios *bios = &dev_priv->vbios;
4342 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4343 uint8_t *otable = NULL;
4347 if (!bios->display.script_table_ptr) {
4348 NV_ERROR(dev, "No pointer to output script table\n");
4353 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4354 * so until they are, we really don't need to care.
4356 if (table[0] < 0x20)
4359 if (table[0] != 0x20 && table[0] != 0x21) {
4360 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4366 * The output script tables describing a particular output type
4369 * offset + 0 (32 bits): output this table matches (hash of DCB)
4370 * offset + 4 ( 8 bits): unknown
4371 * offset + 5 ( 8 bits): number of configurations
4372 * offset + 6 (16 bits): pointer to some script
4373 * offset + 8 (16 bits): pointer to some script
4376 * offset + 10 : configuration 0
4379 * offset + 10 : pointer to some script
4380 * offset + 12 : configuration 0
4382 * Each config entry is as follows:
4384 * offset + 0 (16 bits): unknown, assumed to be a match value
4385 * offset + 2 (16 bits): pointer to script table (clock set?)
4386 * offset + 4 (16 bits): pointer to script table (reset?)
4388 * There doesn't appear to be a count value to say how many
4389 * entries exist in each script table, instead, a 0 value in
4390 * the first 16-bit word seems to indicate both the end of the
4391 * list and the default entry. The second 16-bit word in the
4392 * script tables is a pointer to the script to execute.
4395 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4396 dcbent->type, dcbent->location, dcbent->or);
4397 for (i = 0; i < table[3]; i++) {
4398 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
4399 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4404 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4408 if (pclk < -2 || pclk > 0) {
4409 /* Try to find matching script table entry */
4410 for (i = 0; i < otable[5]; i++) {
4411 if (ROM16(otable[table[4] + i*6]) == type)
4415 if (i == otable[5]) {
4416 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4418 type, dcbent->type, dcbent->or);
4424 script = ROM16(otable[6]);
4426 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4430 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4431 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4434 script = ROM16(otable[8]);
4436 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4440 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4441 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4445 script = ROM16(otable[10]);
4449 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4453 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4454 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4457 script = ROM16(otable[table[4] + i*6 + 2]);
4459 script = clkcmptable(bios, script, pclk);
4461 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4465 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4466 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4469 script = ROM16(otable[table[4] + i*6 + 4]);
4471 script = clkcmptable(bios, script, -pclk);
4473 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4477 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4478 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4485 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4488 * the pxclk parameter is in kHz
4490 * This runs the TMDS regs setting code found on BIT bios cards
4492 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4493 * ffs(or) == 3, use the second.
4496 struct drm_nouveau_private *dev_priv = dev->dev_private;
4497 struct nvbios *bios = &dev_priv->vbios;
4498 int cv = bios->chip_version;
4499 uint16_t clktable = 0, scriptptr;
4500 uint32_t sel_clk_binding, sel_clk;
4502 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4503 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4504 dcbent->location != DCB_LOC_ON_CHIP)
4507 switch (ffs(dcbent->or)) {
4509 clktable = bios->tmds.output0_script_ptr;
4513 clktable = bios->tmds.output1_script_ptr;
4518 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4522 scriptptr = clkcmptable(bios, clktable, pxclk);
4525 NV_ERROR(dev, "TMDS output init script not found\n");
4529 /* don't let script change pll->head binding */
4530 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4531 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4532 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4533 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4538 struct pll_mapping {
4543 static struct pll_mapping nv04_pll_mapping[] = {
4544 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4545 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4546 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4547 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4551 static struct pll_mapping nv40_pll_mapping[] = {
4552 { PLL_CORE , 0x004000 },
4553 { PLL_MEMORY, 0x004020 },
4554 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4555 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4559 static struct pll_mapping nv50_pll_mapping[] = {
4560 { PLL_CORE , 0x004028 },
4561 { PLL_SHADER, 0x004020 },
4562 { PLL_UNK03 , 0x004000 },
4563 { PLL_MEMORY, 0x004008 },
4564 { PLL_UNK40 , 0x00e810 },
4565 { PLL_UNK41 , 0x00e818 },
4566 { PLL_UNK42 , 0x00e824 },
4567 { PLL_VPLL0 , 0x614100 },
4568 { PLL_VPLL1 , 0x614900 },
4572 static struct pll_mapping nv84_pll_mapping[] = {
4573 { PLL_CORE , 0x004028 },
4574 { PLL_SHADER, 0x004020 },
4575 { PLL_MEMORY, 0x004008 },
4576 { PLL_VDEC , 0x004030 },
4577 { PLL_UNK41 , 0x00e818 },
4578 { PLL_VPLL0 , 0x614100 },
4579 { PLL_VPLL1 , 0x614900 },
4584 get_pll_register(struct drm_device *dev, enum pll_types type)
4586 struct drm_nouveau_private *dev_priv = dev->dev_private;
4587 struct nvbios *bios = &dev_priv->vbios;
4588 struct pll_mapping *map;
4591 if (dev_priv->card_type < NV_40)
4592 map = nv04_pll_mapping;
4594 if (dev_priv->card_type < NV_50)
4595 map = nv40_pll_mapping;
4597 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4599 if (plim[0] >= 0x30) {
4600 u8 *entry = plim + plim[1];
4601 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4602 if (entry[0] == type)
4603 return ROM32(entry[3]);
4609 if (dev_priv->chipset == 0x50)
4610 map = nv50_pll_mapping;
4612 map = nv84_pll_mapping;
4616 if (map->type == type)
4624 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4629 * Version 0x10: NV30, NV31
4630 * One byte header (version), one record of 24 bytes
4631 * Version 0x11: NV36 - Not implemented
4632 * Seems to have same record style as 0x10, but 3 records rather than 1
4633 * Version 0x20: Found on Geforce 6 cards
4634 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4635 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4636 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4637 * length in general, some (integrated) have an extra configuration byte
4638 * Version 0x30: Found on Geforce 8, separates the register mapping
4639 * from the limits tables.
4642 struct drm_nouveau_private *dev_priv = dev->dev_private;
4643 struct nvbios *bios = &dev_priv->vbios;
4644 int cv = bios->chip_version, pllindex = 0;
4645 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4646 uint32_t crystal_strap_mask, crystal_straps;
4648 if (!bios->pll_limit_tbl_ptr) {
4649 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4651 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4655 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4657 crystal_strap_mask = 1 << 6;
4658 /* open coded dev->twoHeads test */
4659 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4660 crystal_strap_mask |= 1 << 22;
4661 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4664 switch (pll_lim_ver) {
4666 * We use version 0 to indicate a pre limit table bios (single stage
4667 * pll) and load the hard coded limits instead.
4674 * Strictly v0x11 has 3 entries, but the last two don't seem
4686 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4687 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4688 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4691 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4692 "supported\n", pll_lim_ver);
4696 /* initialize all members to zero */
4697 memset(pll_lim, 0, sizeof(struct pll_lims));
4699 /* if we were passed a type rather than a register, figure
4700 * out the register and store it
4702 if (limit_match > PLL_MAX)
4703 pll_lim->reg = limit_match;
4705 pll_lim->reg = get_pll_register(dev, limit_match);
4710 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4711 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4713 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4714 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4715 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4716 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4717 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4718 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4719 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4721 /* these values taken from nv30/31/36 */
4722 pll_lim->vco1.min_n = 0x1;
4724 pll_lim->vco1.min_n = 0x5;
4725 pll_lim->vco1.max_n = 0xff;
4726 pll_lim->vco1.min_m = 0x1;
4727 pll_lim->vco1.max_m = 0xd;
4728 pll_lim->vco2.min_n = 0x4;
4730 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4731 * table version (apart from nv35)), N2 is compared to
4732 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4735 pll_lim->vco2.max_n = 0x28;
4736 if (cv == 0x30 || cv == 0x35)
4737 /* only 5 bits available for N2 on nv30/35 */
4738 pll_lim->vco2.max_n = 0x1f;
4739 pll_lim->vco2.min_m = 0x1;
4740 pll_lim->vco2.max_m = 0x4;
4741 pll_lim->max_log2p = 0x7;
4742 pll_lim->max_usable_log2p = 0x6;
4743 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4744 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4749 * First entry is default match, if nothing better. warn if
4752 if (ROM32(bios->data[plloffs]))
4753 NV_WARN(dev, "Default PLL limit entry has non-zero "
4754 "register field\n");
4756 for (i = 1; i < entries; i++)
4757 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4762 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4763 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4764 "limits table", pll_lim->reg);
4768 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4770 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4771 pllindex ? pll_lim->reg : 0);
4774 * Frequencies are stored in tables in MHz, kHz are more
4775 * useful, so we convert.
4778 /* What output frequencies can each VCO generate? */
4779 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4780 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4781 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4782 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4784 /* What input frequencies they accept (past the m-divider)? */
4785 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4786 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4787 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4788 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4790 /* What values are accepted as multiplier and divider? */
4791 pll_lim->vco1.min_n = pll_rec[20];
4792 pll_lim->vco1.max_n = pll_rec[21];
4793 pll_lim->vco1.min_m = pll_rec[22];
4794 pll_lim->vco1.max_m = pll_rec[23];
4795 pll_lim->vco2.min_n = pll_rec[24];
4796 pll_lim->vco2.max_n = pll_rec[25];
4797 pll_lim->vco2.min_m = pll_rec[26];
4798 pll_lim->vco2.max_m = pll_rec[27];
4800 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4801 if (pll_lim->max_log2p > 0x7)
4802 /* pll decoding in nv_hw.c assumes never > 7 */
4803 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4804 pll_lim->max_log2p);
4806 pll_lim->max_usable_log2p = 0x6;
4807 pll_lim->log2p_bias = pll_rec[30];
4809 if (recordlen > 0x22)
4810 pll_lim->refclk = ROM32(pll_rec[31]);
4812 if (recordlen > 0x23 && pll_rec[35])
4814 "Bits set in PLL configuration byte (%x)\n",
4817 /* C51 special not seen elsewhere */
4818 if (cv == 0x51 && !pll_lim->refclk) {
4819 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4821 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4822 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4823 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4824 pll_lim->refclk = 200000;
4826 pll_lim->refclk = 25000;
4829 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4830 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4831 uint8_t *record = NULL;
4834 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4837 for (i = 0; i < entries; i++, entry += recordlen) {
4838 if (ROM32(entry[3]) == pll_lim->reg) {
4839 record = &bios->data[ROM16(entry[1])];
4845 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4846 "limits table", pll_lim->reg);
4850 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4851 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4852 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4853 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4854 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4855 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4856 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4857 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4858 pll_lim->vco1.min_n = record[16];
4859 pll_lim->vco1.max_n = record[17];
4860 pll_lim->vco1.min_m = record[18];
4861 pll_lim->vco1.max_m = record[19];
4862 pll_lim->vco2.min_n = record[20];
4863 pll_lim->vco2.max_n = record[21];
4864 pll_lim->vco2.min_m = record[22];
4865 pll_lim->vco2.max_m = record[23];
4866 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4867 pll_lim->log2p_bias = record[27];
4868 pll_lim->refclk = ROM32(record[28]);
4869 } else if (pll_lim_ver) { /* ver 0x40 */
4870 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4871 uint8_t *record = NULL;
4874 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4877 for (i = 0; i < entries; i++, entry += recordlen) {
4878 if (ROM32(entry[3]) == pll_lim->reg) {
4879 record = &bios->data[ROM16(entry[1])];
4885 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4886 "limits table", pll_lim->reg);
4890 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4891 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4892 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4893 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4894 pll_lim->vco1.min_m = record[8];
4895 pll_lim->vco1.max_m = record[9];
4896 pll_lim->vco1.min_n = record[10];
4897 pll_lim->vco1.max_n = record[11];
4898 pll_lim->min_p = record[12];
4899 pll_lim->max_p = record[13];
4900 pll_lim->refclk = ROM16(entry[9]) * 1000;
4904 * By now any valid limit table ought to have set a max frequency for
4905 * vco1, so if it's zero it's either a pre limit table bios, or one
4906 * with an empty limit table (seen on nv18)
4908 if (!pll_lim->vco1.maxfreq) {
4909 pll_lim->vco1.minfreq = bios->fminvco;
4910 pll_lim->vco1.maxfreq = bios->fmaxvco;
4911 pll_lim->vco1.min_inputfreq = 0;
4912 pll_lim->vco1.max_inputfreq = INT_MAX;
4913 pll_lim->vco1.min_n = 0x1;
4914 pll_lim->vco1.max_n = 0xff;
4915 pll_lim->vco1.min_m = 0x1;
4916 if (crystal_straps == 0) {
4917 /* nv05 does this, nv11 doesn't, nv10 unknown */
4919 pll_lim->vco1.min_m = 0x7;
4920 pll_lim->vco1.max_m = 0xd;
4923 pll_lim->vco1.min_m = 0x8;
4924 pll_lim->vco1.max_m = 0xe;
4926 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4927 pll_lim->max_log2p = 4;
4929 pll_lim->max_log2p = 5;
4930 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4933 if (!pll_lim->refclk)
4934 switch (crystal_straps) {
4936 pll_lim->refclk = 13500;
4939 pll_lim->refclk = 14318;
4942 pll_lim->refclk = 27000;
4944 case (1 << 22 | 1 << 6):
4945 pll_lim->refclk = 25000;
4949 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4950 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4951 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4952 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4953 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4954 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4955 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4956 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4957 if (pll_lim->vco2.maxfreq) {
4958 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4959 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4960 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4961 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4962 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4963 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4964 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4965 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4967 if (!pll_lim->max_p) {
4968 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4969 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4971 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4972 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4974 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
4979 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4982 * offset + 0 (8 bits): Micro version
4983 * offset + 1 (8 bits): Minor version
4984 * offset + 2 (8 bits): Chip version
4985 * offset + 3 (8 bits): Major version
4988 bios->major_version = bios->data[offset + 3];
4989 bios->chip_version = bios->data[offset + 2];
4990 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4991 bios->data[offset + 3], bios->data[offset + 2],
4992 bios->data[offset + 1], bios->data[offset]);
4995 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4998 * Parses the init table segment for pointers used in script execution.
5000 * offset + 0 (16 bits): init script tables pointer
5001 * offset + 2 (16 bits): macro index table pointer
5002 * offset + 4 (16 bits): macro table pointer
5003 * offset + 6 (16 bits): condition table pointer
5004 * offset + 8 (16 bits): io condition table pointer
5005 * offset + 10 (16 bits): io flag condition table pointer
5006 * offset + 12 (16 bits): init function table pointer
5009 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5010 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5011 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5012 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5013 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5014 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5015 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5018 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5021 * Parses the load detect values for g80 cards.
5023 * offset + 0 (16 bits): loadval table pointer
5026 uint16_t load_table_ptr;
5027 uint8_t version, headerlen, entrylen, num_entries;
5029 if (bitentry->length != 3) {
5030 NV_ERROR(dev, "Do not understand BIT A table\n");
5034 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5036 if (load_table_ptr == 0x0) {
5037 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
5041 version = bios->data[load_table_ptr];
5043 if (version != 0x10) {
5044 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5045 version >> 4, version & 0xF);
5049 headerlen = bios->data[load_table_ptr + 1];
5050 entrylen = bios->data[load_table_ptr + 2];
5051 num_entries = bios->data[load_table_ptr + 3];
5053 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5054 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5058 /* First entry is normal dac, 2nd tv-out perhaps? */
5059 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
5064 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5067 * offset + 8 (16 bits): PLL limits table pointer
5069 * There's more in here, but that's unknown.
5072 if (bitentry->length < 10) {
5073 NV_ERROR(dev, "Do not understand BIT C table\n");
5077 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5082 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5085 * Parses the flat panel table segment that the bit entry points to.
5086 * Starting at bitentry->offset:
5088 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5089 * records beginning with a freq.
5090 * offset + 2 (16 bits): mode table pointer
5093 if (bitentry->length != 4) {
5094 NV_ERROR(dev, "Do not understand BIT display table\n");
5098 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5103 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5106 * Parses the init table segment that the bit entry points to.
5108 * See parse_script_table_pointers for layout
5111 if (bitentry->length < 14) {
5112 NV_ERROR(dev, "Do not understand init table\n");
5116 parse_script_table_pointers(bios, bitentry->offset);
5118 if (bitentry->length >= 16)
5119 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5120 if (bitentry->length >= 18)
5121 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5126 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5129 * BIT 'i' (info?) table
5131 * offset + 0 (32 bits): BIOS version dword (as in B table)
5132 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5133 * offset + 13 (16 bits): pointer to table containing DAC load
5134 * detection comparison values
5136 * There's other things in the table, purpose unknown
5139 uint16_t daccmpoffset;
5140 uint8_t dacver, dacheaderlen;
5142 if (bitentry->length < 6) {
5143 NV_ERROR(dev, "BIT i table too short for needed information\n");
5147 parse_bios_version(dev, bios, bitentry->offset);
5150 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5151 * Quadro identity crisis), other bits possibly as for BMP feature byte
5153 bios->feature_byte = bios->data[bitentry->offset + 5];
5154 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5156 if (bitentry->length < 15) {
5157 NV_WARN(dev, "BIT i table not long enough for DAC load "
5158 "detection comparison table\n");
5162 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5164 /* doesn't exist on g80 */
5169 * The first value in the table, following the header, is the
5170 * comparison value, the second entry is a comparison value for
5171 * TV load detection.
5174 dacver = bios->data[daccmpoffset];
5175 dacheaderlen = bios->data[daccmpoffset + 1];
5177 if (dacver != 0x00 && dacver != 0x10) {
5178 NV_WARN(dev, "DAC load detection comparison table version "
5179 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5183 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5184 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
5189 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5192 * Parses the LVDS table segment that the bit entry points to.
5193 * Starting at bitentry->offset:
5195 * offset + 0 (16 bits): LVDS strap xlate table pointer
5198 if (bitentry->length != 2) {
5199 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5204 * No idea if it's still called the LVDS manufacturer table, but
5205 * the concept's close enough.
5207 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5213 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5214 struct bit_entry *bitentry)
5217 * offset + 2 (8 bits): number of options in an
5218 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5219 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5220 * restrict option selection
5222 * There's a bunch of bits in this table other than the RAM restrict
5223 * stuff that we don't use - their use currently unknown
5227 * Older bios versions don't have a sufficiently long table for
5230 if (bitentry->length < 0x5)
5233 if (bitentry->version < 2) {
5234 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5235 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5237 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5238 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5244 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5247 * Parses the pointer to the TMDS table
5249 * Starting at bitentry->offset:
5251 * offset + 0 (16 bits): TMDS table pointer
5253 * The TMDS table is typically found just before the DCB table, with a
5254 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5257 * At offset +7 is a pointer to a script, which I don't know how to
5259 * At offset +9 is a pointer to another script, likewise
5260 * Offset +11 has a pointer to a table where the first word is a pxclk
5261 * frequency and the second word a pointer to a script, which should be
5262 * run if the comparison pxclk frequency is less than the pxclk desired.
5263 * This repeats for decreasing comparison frequencies
5264 * Offset +13 has a pointer to a similar table
5265 * The selection of table (and possibly +7/+9 script) is dictated by
5266 * "or" from the DCB.
5269 uint16_t tmdstableptr, script1, script2;
5271 if (bitentry->length != 2) {
5272 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5276 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5277 if (!tmdstableptr) {
5278 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5282 NV_INFO(dev, "TMDS table version %d.%d\n",
5283 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5285 /* nv50+ has v2.0, but we don't parse it atm */
5286 if (bios->data[tmdstableptr] != 0x11)
5290 * These two scripts are odd: they don't seem to get run even when
5291 * they are not stubbed.
5293 script1 = ROM16(bios->data[tmdstableptr + 7]);
5294 script2 = ROM16(bios->data[tmdstableptr + 9]);
5295 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5296 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5298 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5299 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5305 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5306 struct bit_entry *bitentry)
5309 * Parses the pointer to the G80 output script tables
5311 * Starting at bitentry->offset:
5313 * offset + 0 (16 bits): output script table pointer
5316 uint16_t outputscripttableptr;
5318 if (bitentry->length != 3) {
5319 NV_ERROR(dev, "Do not understand BIT U table\n");
5323 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5324 bios->display.script_table_ptr = outputscripttableptr;
5330 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5333 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5336 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5338 struct drm_nouveau_private *dev_priv = dev->dev_private;
5339 struct nvbios *bios = &dev_priv->vbios;
5342 if (bios->type != NVBIOS_BIT)
5345 entries = bios->data[bios->offset + 10];
5346 entry = &bios->data[bios->offset + 12];
5348 if (entry[0] == id) {
5350 bit->version = entry[1];
5351 bit->length = ROM16(entry[2]);
5352 bit->offset = ROM16(entry[4]);
5353 bit->data = ROMPTR(dev, entry[4]);
5357 entry += bios->data[bios->offset + 9];
5364 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5365 struct bit_table *table)
5367 struct drm_device *dev = bios->dev;
5368 struct bit_entry bitentry;
5370 if (bit_table(dev, table->id, &bitentry) == 0)
5371 return table->parse_fn(dev, bios, &bitentry);
5373 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5378 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5383 * The only restriction on parsing order currently is having 'i' first
5384 * for use of bios->*_version or bios->feature_byte while parsing;
5385 * functions shouldn't be actually *doing* anything apart from pulling
5386 * data from the image into the bios struct, thus no interdependencies
5388 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5389 if (ret) /* info? */
5391 if (bios->major_version >= 0x60) /* g80+ */
5392 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5393 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5396 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5397 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5400 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5401 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5402 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5403 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5408 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5411 * Parses the BMP structure for useful things, but does not act on them
5413 * offset + 5: BMP major version
5414 * offset + 6: BMP minor version
5415 * offset + 9: BMP feature byte
5416 * offset + 10: BCD encoded BIOS version
5418 * offset + 18: init script table pointer (for bios versions < 5.10h)
5419 * offset + 20: extra init script table pointer (for bios
5422 * offset + 24: memory init table pointer (used on early bios versions)
5423 * offset + 26: SDR memory sequencing setup data table
5424 * offset + 28: DDR memory sequencing setup data table
5426 * offset + 54: index of I2C CRTC pair to use for CRT output
5427 * offset + 55: index of I2C CRTC pair to use for TV output
5428 * offset + 56: index of I2C CRTC pair to use for flat panel output
5429 * offset + 58: write CRTC index for I2C pair 0
5430 * offset + 59: read CRTC index for I2C pair 0
5431 * offset + 60: write CRTC index for I2C pair 1
5432 * offset + 61: read CRTC index for I2C pair 1
5434 * offset + 67: maximum internal PLL frequency (single stage PLL)
5435 * offset + 71: minimum internal PLL frequency (single stage PLL)
5437 * offset + 75: script table pointers, as described in
5438 * parse_script_table_pointers
5440 * offset + 89: TMDS single link output A table pointer
5441 * offset + 91: TMDS single link output B table pointer
5442 * offset + 95: LVDS single link output A table pointer
5443 * offset + 105: flat panel timings table pointer
5444 * offset + 107: flat panel strapping translation table pointer
5445 * offset + 117: LVDS manufacturer panel config table pointer
5446 * offset + 119: LVDS manufacturer strapping translation table pointer
5448 * offset + 142: PLL limits table pointer
5450 * offset + 156: minimum pixel clock for LVDS dual link
5453 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5455 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5457 /* load needed defaults in case we can't parse this info */
5458 bios->digital_min_front_porch = 0x4b;
5459 bios->fmaxvco = 256000;
5460 bios->fminvco = 128000;
5461 bios->fp.duallink_transition_clk = 90000;
5463 bmp_version_major = bmp[5];
5464 bmp_version_minor = bmp[6];
5466 NV_TRACE(dev, "BMP version %d.%d\n",
5467 bmp_version_major, bmp_version_minor);
5470 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5471 * pointer on early versions
5473 if (bmp_version_major < 5)
5474 *(uint16_t *)&bios->data[0x36] = 0;
5477 * Seems that the minor version was 1 for all major versions prior
5478 * to 5. Version 6 could theoretically exist, but I suspect BIT
5481 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5482 NV_ERROR(dev, "You have an unsupported BMP version. "
5483 "Please send in your bios\n");
5487 if (bmp_version_major == 0)
5488 /* nothing that's currently useful in this version */
5490 else if (bmp_version_major == 1)
5491 bmplength = 44; /* exact for 1.01 */
5492 else if (bmp_version_major == 2)
5493 bmplength = 48; /* exact for 2.01 */
5494 else if (bmp_version_major == 3)
5496 /* guessed - mem init tables added in this version */
5497 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5498 /* don't know if 5.0 exists... */
5500 /* guessed - BMP I2C indices added in version 4*/
5501 else if (bmp_version_minor < 0x6)
5502 bmplength = 67; /* exact for 5.01 */
5503 else if (bmp_version_minor < 0x10)
5504 bmplength = 75; /* exact for 5.06 */
5505 else if (bmp_version_minor == 0x10)
5506 bmplength = 89; /* exact for 5.10h */
5507 else if (bmp_version_minor < 0x14)
5508 bmplength = 118; /* exact for 5.11h */
5509 else if (bmp_version_minor < 0x24)
5511 * Not sure of version where pll limits came in;
5512 * certainly exist by 0x24 though.
5514 /* length not exact: this is long enough to get lvds members */
5516 else if (bmp_version_minor < 0x27)
5518 * Length not exact: this is long enough to get pll limit
5524 * Length not exact: this is long enough to get dual link
5530 if (nv_cksum(bmp, 8)) {
5531 NV_ERROR(dev, "Bad BMP checksum\n");
5536 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5537 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5538 * (not nv10gl), bit 5 that the flat panel tables are present, and
5541 bios->feature_byte = bmp[9];
5543 parse_bios_version(dev, bios, offset + 10);
5545 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5546 bios->old_style_init = true;
5547 legacy_scripts_offset = 18;
5548 if (bmp_version_major < 2)
5549 legacy_scripts_offset -= 4;
5550 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5551 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5553 if (bmp_version_major > 2) { /* appears in BMP 3 */
5554 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5555 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5556 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5559 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5561 legacy_i2c_offset = offset + 54;
5562 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5563 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5564 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5566 if (bmplength > 74) {
5567 bios->fmaxvco = ROM32(bmp[67]);
5568 bios->fminvco = ROM32(bmp[71]);
5571 parse_script_table_pointers(bios, offset + 75);
5572 if (bmplength > 94) {
5573 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5574 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5576 * Never observed in use with lvds scripts, but is reused for
5577 * 18/24 bit panel interface default for EDID equipped panels
5578 * (if_is_24bit not set directly to avoid any oscillation).
5580 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5582 if (bmplength > 108) {
5583 bios->fp.fptablepointer = ROM16(bmp[105]);
5584 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5585 bios->fp.xlatwidth = 1;
5587 if (bmplength > 120) {
5588 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5589 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5591 if (bmplength > 143)
5592 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5594 if (bmplength > 157)
5595 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5600 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5604 for (i = 0; i <= (n - len); i++) {
5605 for (j = 0; j < len; j++)
5606 if (data[i + j] != str[j])
5616 dcb_table(struct drm_device *dev)
5618 struct drm_nouveau_private *dev_priv = dev->dev_private;
5621 if (dev_priv->card_type > NV_04)
5622 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5624 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5628 if (dcb[0] >= 0x41) {
5629 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5632 if (dcb[0] >= 0x30) {
5633 if (ROM32(dcb[6]) == 0x4edcbdcb)
5636 if (dcb[0] >= 0x20) {
5637 if (ROM32(dcb[4]) == 0x4edcbdcb)
5640 if (dcb[0] >= 0x15) {
5641 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5645 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5646 * always has the same single (crt) entry, even when tv-out
5647 * present, so the conclusion is this version cannot really
5650 * v1.2 tables (some NV6/10, and NV15+) normally have the
5651 * same 5 entries, which are not specific to the card and so
5654 * v1.2 does have an I2C table that read_dcb_i2c_table can
5655 * handle, but cards exist (nv11 in #14821) with a bad i2c
5656 * table pointer, so use the indices parsed in
5657 * parse_bmp_structure.
5659 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5661 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5665 NV_WARNONCE(dev, "DCB header validation failed\n");
5670 dcb_outp(struct drm_device *dev, u8 idx)
5672 u8 *dcb = dcb_table(dev);
5673 if (dcb && dcb[0] >= 0x30) {
5675 return dcb + dcb[1] + (idx * dcb[3]);
5677 if (dcb && dcb[0] >= 0x20) {
5678 u8 *i2c = ROMPTR(dev, dcb[2]);
5679 u8 *ent = dcb + 8 + (idx * 8);
5680 if (i2c && ent < i2c)
5683 if (dcb && dcb[0] >= 0x15) {
5684 u8 *i2c = ROMPTR(dev, dcb[2]);
5685 u8 *ent = dcb + 4 + (idx * 10);
5686 if (i2c && ent < i2c)
5694 dcb_outp_foreach(struct drm_device *dev, void *data,
5695 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
5699 while ((outp = dcb_outp(dev, ++idx))) {
5700 if (ROM32(outp[0]) == 0x00000000)
5701 break; /* seen on an NV11 with DCB v1.5 */
5702 if (ROM32(outp[0]) == 0xffffffff)
5703 break; /* seen on an NV17 with DCB v2.0 */
5705 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
5707 if ((outp[0] & 0x0f) == OUTPUT_EOL)
5710 ret = exec(dev, data, idx, outp);
5719 dcb_conntab(struct drm_device *dev)
5721 u8 *dcb = dcb_table(dev);
5722 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
5723 u8 *conntab = ROMPTR(dev, dcb[0x14]);
5724 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
5731 dcb_conn(struct drm_device *dev, u8 idx)
5733 u8 *conntab = dcb_conntab(dev);
5734 if (conntab && idx < conntab[2])
5735 return conntab + conntab[1] + (idx * conntab[3]);
5739 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
5741 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5743 memset(entry, 0, sizeof(struct dcb_entry));
5744 entry->index = dcb->entries++;
5749 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5752 struct dcb_entry *entry = new_dcb_entry(dcb);
5755 entry->i2c_index = i2c;
5756 entry->heads = heads;
5757 if (type != OUTPUT_ANALOG)
5758 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5763 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5764 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5766 entry->type = conn & 0xf;
5767 entry->i2c_index = (conn >> 4) & 0xf;
5768 entry->heads = (conn >> 8) & 0xf;
5769 entry->connector = (conn >> 12) & 0xf;
5770 entry->bus = (conn >> 16) & 0xf;
5771 entry->location = (conn >> 20) & 0x3;
5772 entry->or = (conn >> 24) & 0xf;
5774 switch (entry->type) {
5777 * Although the rest of a CRT conf dword is usually
5778 * zeros, mac biosen have stuff there so we must mask
5780 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
5781 (conf & 0xffff) * 10 :
5782 (conf & 0xff) * 10000;
5788 entry->lvdsconf.use_straps_for_mode = true;
5789 if (dcb->version < 0x22) {
5792 * The laptop in bug 14567 lies and claims to not use
5793 * straps when it does, so assume all DCB 2.0 laptops
5794 * use straps, until a broken EDID using one is produced
5796 entry->lvdsconf.use_straps_for_mode = true;
5798 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5799 * mean the same thing (probably wrong, but might work)
5801 if (conf & 0x4 || conf & 0x8)
5802 entry->lvdsconf.use_power_scripts = true;
5806 entry->lvdsconf.use_acpi_for_edid = true;
5808 entry->lvdsconf.use_power_scripts = true;
5809 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
5813 * Until we even try to use these on G8x, it's
5814 * useless reporting unknown bits. They all are.
5816 if (dcb->version >= 0x40)
5819 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5826 if (dcb->version >= 0x30)
5827 entry->tvconf.has_component_output = conf & (0x8 << 4);
5829 entry->tvconf.has_component_output = false;
5834 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5835 switch ((conf & 0x00e00000) >> 21) {
5837 entry->dpconf.link_bw = 162000;
5840 entry->dpconf.link_bw = 270000;
5843 switch ((conf & 0x0f000000) >> 24) {
5845 entry->dpconf.link_nr = 4;
5848 entry->dpconf.link_nr = 2;
5851 entry->dpconf.link_nr = 1;
5856 if (dcb->version >= 0x40)
5857 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5858 else if (dcb->version >= 0x30)
5859 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
5860 else if (dcb->version >= 0x22)
5861 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5865 /* weird g80 mobile type that "nv" treats as a terminator */
5872 if (dcb->version < 0x40) {
5873 /* Normal entries consist of a single bit, but dual link has
5874 * the next most significant bit set too
5876 entry->duallink_possible =
5877 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5879 entry->duallink_possible = (entry->sorconf.link == 3);
5882 /* unsure what DCB version introduces this, 3.0? */
5883 if (conf & 0x100000)
5884 entry->i2c_upper_default = true;
5890 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5891 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5893 switch (conn & 0x0000000f) {
5895 entry->type = OUTPUT_ANALOG;
5898 entry->type = OUTPUT_TV;
5903 entry->type = OUTPUT_LVDS;
5905 entry->type = OUTPUT_TMDS;
5908 entry->type = OUTPUT_LVDS;
5911 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5915 entry->i2c_index = (conn & 0x0003c000) >> 14;
5916 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5917 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5918 entry->location = (conn & 0x01e00000) >> 21;
5919 entry->bus = (conn & 0x0e000000) >> 25;
5920 entry->duallink_possible = false;
5922 switch (entry->type) {
5924 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5927 entry->tvconf.has_component_output = false;
5930 if ((conn & 0x00003f00) >> 8 != 0x10)
5931 entry->lvdsconf.use_straps_for_mode = true;
5932 entry->lvdsconf.use_power_scripts = true;
5942 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
5945 * DCB v2.0 lists each output combination separately.
5946 * Here we merge compatible entries to have fewer outputs, with
5950 int i, newentries = 0;
5952 for (i = 0; i < dcb->entries; i++) {
5953 struct dcb_entry *ient = &dcb->entry[i];
5956 for (j = i + 1; j < dcb->entries; j++) {
5957 struct dcb_entry *jent = &dcb->entry[j];
5959 if (jent->type == 100) /* already merged entry */
5962 /* merge heads field when all other fields the same */
5963 if (jent->i2c_index == ient->i2c_index &&
5964 jent->type == ient->type &&
5965 jent->location == ient->location &&
5966 jent->or == ient->or) {
5967 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5969 ient->heads |= jent->heads;
5970 jent->type = 100; /* dummy value */
5975 /* Compact entries merged into others out of dcb */
5976 for (i = 0; i < dcb->entries; i++) {
5977 if (dcb->entry[i].type == 100)
5980 if (newentries != i) {
5981 dcb->entry[newentries] = dcb->entry[i];
5982 dcb->entry[newentries].index = newentries;
5987 dcb->entries = newentries;
5991 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
5993 struct drm_nouveau_private *dev_priv = dev->dev_private;
5994 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5996 /* Dell Precision M6300
5997 * DCB entry 2: 02025312 00000010
5998 * DCB entry 3: 02026312 00000020
6000 * Identical, except apparently a different connector on a
6001 * different SOR link. Not a clue how we're supposed to know
6002 * which one is in use if it even shares an i2c line...
6004 * Ignore the connector on the second SOR link to prevent
6005 * nasty problems until this is sorted (assuming it's not a
6008 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6009 if (*conn == 0x02026312 && *conf == 0x00000020)
6015 * DCB reports an LVDS output that should be TMDS:
6016 * DCB entry 1: f2005014 ffffffff
6018 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6019 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6020 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6027 * So many things wrong here, replace the entire encoder table..
6029 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6031 *conn = 0x02001300; /* VGA, connector 1 */
6035 *conn = 0x01010312; /* DVI, connector 0 */
6039 *conn = 0x01010310; /* VGA, connector 0 */
6043 *conn = 0x02022362; /* HDMI, connector 2 */
6046 *conn = 0x0000000e; /* EOL */
6051 /* Some other twisted XFX board (rhbz#694914)
6053 * The DVI/VGA encoder combo that's supposed to represent the
6054 * DVI-I connector actually point at two different ones, and
6055 * the HDMI connector ends up paired with the VGA instead.
6057 * Connector table is missing anything for VGA at all, pointing it
6058 * an invalid conntab entry 2 so we figure it out ourself.
6060 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6062 *conn = 0x02002300; /* VGA, connector 2 */
6066 *conn = 0x01010312; /* DVI, connector 0 */
6070 *conn = 0x04020310; /* VGA, connector 0 */
6074 *conn = 0x02021322; /* HDMI, connector 1 */
6077 *conn = 0x0000000e; /* EOL */
6086 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6088 struct dcb_table *dcb = &bios->dcb;
6089 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6092 /* Apple iMac G4 NV17 */
6093 if (of_machine_is_compatible("PowerMac4,5")) {
6094 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6095 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6100 /* Make up some sane defaults */
6101 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6102 bios->legacy.i2c_indices.crt, 1, 1);
6104 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6105 fabricate_dcb_output(dcb, OUTPUT_TV,
6106 bios->legacy.i2c_indices.tv,
6109 else if (bios->tmds.output0_script_ptr ||
6110 bios->tmds.output1_script_ptr)
6111 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6112 bios->legacy.i2c_indices.panel,
6117 parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6119 struct drm_nouveau_private *dev_priv = dev->dev_private;
6120 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6121 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
6122 u32 conn = ROM32(outp[0]);
6125 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
6126 struct dcb_entry *entry = new_dcb_entry(dcb);
6128 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
6130 if (dcb->version >= 0x20)
6131 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6133 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6135 return 1; /* stop parsing */
6137 /* Ignore the I2C index for on-chip TV-out, as there
6138 * are cards with bogus values (nv31m in bug 23212),
6139 * and it's otherwise useless.
6141 if (entry->type == OUTPUT_TV &&
6142 entry->location == DCB_LOC_ON_CHIP)
6143 entry->i2c_index = 0x0f;
6150 dcb_fake_connectors(struct nvbios *bios)
6152 struct dcb_table *dcbt = &bios->dcb;
6156 /* heuristic: if we ever get a non-zero connector field, assume
6157 * that all the indices are valid and we don't need fake them.
6159 for (i = 0; i < dcbt->entries; i++) {
6160 if (dcbt->entry[i].connector)
6164 /* no useful connector info available, we need to make it up
6165 * ourselves. the rule here is: anything on the same i2c bus
6166 * is considered to be on the same connector. any output
6167 * without an associated i2c bus is assigned its own unique
6170 for (i = 0; i < dcbt->entries; i++) {
6171 u8 i2c = dcbt->entry[i].i2c_index;
6173 dcbt->entry[i].connector = idx++;
6177 dcbt->entry[i].connector = map[i2c] - 1;
6181 /* if we created more than one connector, destroy the connector
6182 * table - just in case it has random, rather than stub, entries.
6185 u8 *conntab = dcb_conntab(bios->dev);
6192 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6194 struct dcb_table *dcb = &bios->dcb;
6198 dcbt = dcb_table(dev);
6200 /* handle pre-DCB boards */
6201 if (bios->type == NVBIOS_BMP) {
6202 fabricate_dcb_encoder_table(dev, bios);
6209 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6211 dcb->version = dcbt[0];
6212 dcb_outp_foreach(dev, NULL, parse_dcb_entry);
6215 * apart for v2.1+ not being known for requiring merging, this
6216 * guarantees dcbent->index is the index of the entry in the rom image
6218 if (dcb->version < 0x21)
6219 merge_like_dcb_entries(dev, dcb);
6224 /* dump connector table entries to log, if any exist */
6226 while ((conn = dcb_conn(dev, ++idx))) {
6227 if (conn[0] != 0xff) {
6228 NV_TRACE(dev, "DCB conn %02d: ", idx);
6229 if (dcb_conntab(dev)[3] < 4)
6230 printk("%04x\n", ROM16(conn[0]));
6232 printk("%08x\n", ROM32(conn[0]));
6235 dcb_fake_connectors(bios);
6239 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6242 * The header following the "HWSQ" signature has the number of entries,
6243 * and the entry size
6245 * An entry consists of a dword to write to the sequencer control reg
6246 * (0x00001304), followed by the ucode bytes, written sequentially,
6247 * starting at reg 0x00001400
6250 uint8_t bytes_to_write;
6251 uint16_t hwsq_entry_offset;
6254 if (bios->data[hwsq_offset] <= entry) {
6255 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6256 "requested entry\n");
6260 bytes_to_write = bios->data[hwsq_offset + 1];
6262 if (bytes_to_write != 36) {
6263 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6267 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6269 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6271 /* set sequencer control */
6272 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6273 bytes_to_write -= 4;
6276 for (i = 0; i < bytes_to_write; i += 4)
6277 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6279 /* twiddle NV_PBUS_DEBUG_4 */
6280 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6285 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6286 struct nvbios *bios)
6289 * BMP based cards, from NV17, need a microcode loading to correctly
6290 * control the GPIO etc for LVDS panels
6292 * BIT based cards seem to do this directly in the init scripts
6294 * The microcode entries are found by the "HWSQ" signature.
6297 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6298 const int sz = sizeof(hwsq_signature);
6301 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6305 /* always use entry 0? */
6306 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6309 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6311 struct drm_nouveau_private *dev_priv = dev->dev_private;
6312 struct nvbios *bios = &dev_priv->vbios;
6313 const uint8_t edid_sig[] = {
6314 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6315 uint16_t offset = 0;
6317 int searchlen = NV_PROM_SIZE;
6320 return bios->fp.edid;
6323 newoffset = findstr(&bios->data[offset], searchlen,
6327 offset += newoffset;
6328 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6331 searchlen -= offset;
6335 NV_TRACE(dev, "Found EDID in BIOS\n");
6337 return bios->fp.edid = &bios->data[offset];
6341 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6342 struct dcb_entry *dcbent, int crtc)
6344 struct drm_nouveau_private *dev_priv = dev->dev_private;
6345 struct nvbios *bios = &dev_priv->vbios;
6346 struct init_exec iexec = { true, false };
6348 spin_lock_bh(&bios->lock);
6349 bios->display.output = dcbent;
6350 bios->display.crtc = crtc;
6351 parse_init_table(bios, table, &iexec);
6352 bios->display.output = NULL;
6353 spin_unlock_bh(&bios->lock);
6357 nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6359 struct drm_nouveau_private *dev_priv = dev->dev_private;
6360 struct nvbios *bios = &dev_priv->vbios;
6361 struct init_exec iexec = { true, false };
6363 parse_init_table(bios, table, &iexec);
6366 static bool NVInitVBIOS(struct drm_device *dev)
6368 struct drm_nouveau_private *dev_priv = dev->dev_private;
6369 struct nvbios *bios = &dev_priv->vbios;
6371 memset(bios, 0, sizeof(struct nvbios));
6372 spin_lock_init(&bios->lock);
6375 return bios_shadow(dev);
6378 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6380 struct drm_nouveau_private *dev_priv = dev->dev_private;
6381 struct nvbios *bios = &dev_priv->vbios;
6382 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6383 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6386 offset = findstr(bios->data, bios->length,
6387 bit_signature, sizeof(bit_signature));
6389 NV_TRACE(dev, "BIT BIOS found\n");
6390 bios->type = NVBIOS_BIT;
6391 bios->offset = offset;
6392 return parse_bit_structure(bios, offset + 6);
6395 offset = findstr(bios->data, bios->length,
6396 bmp_signature, sizeof(bmp_signature));
6398 NV_TRACE(dev, "BMP BIOS found\n");
6399 bios->type = NVBIOS_BMP;
6400 bios->offset = offset;
6401 return parse_bmp_structure(dev, bios, offset);
6404 NV_ERROR(dev, "No known BIOS signature found\n");
6409 nouveau_run_vbios_init(struct drm_device *dev)
6411 struct drm_nouveau_private *dev_priv = dev->dev_private;
6412 struct nvbios *bios = &dev_priv->vbios;
6415 /* Reset the BIOS head to 0. */
6416 bios->state.crtchead = 0;
6418 if (bios->major_version < 5) /* BMP only */
6419 load_nv17_hw_sequencer_ucode(dev, bios);
6421 if (bios->execute) {
6422 bios->fp.last_script_invoc = 0;
6423 bios->fp.lvds_init_run = false;
6426 parse_init_tables(bios);
6429 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6430 * parser will run this right after the init tables, the binary
6431 * driver appears to run it at some point later.
6433 if (bios->some_script_ptr) {
6434 struct init_exec iexec = {true, false};
6436 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6437 bios->some_script_ptr);
6438 parse_init_table(bios, bios->some_script_ptr, &iexec);
6441 if (dev_priv->card_type >= NV_50) {
6442 for (i = 0; i < bios->dcb.entries; i++) {
6443 nouveau_bios_run_display_table(dev, 0, 0,
6444 &bios->dcb.entry[i], -1);
6452 nouveau_bios_posted(struct drm_device *dev)
6454 struct drm_nouveau_private *dev_priv = dev->dev_private;
6457 if (dev_priv->card_type >= NV_50) {
6458 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6459 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6464 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6465 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6466 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6467 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6468 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6470 return (htotal != 0);
6474 nouveau_bios_init(struct drm_device *dev)
6476 struct drm_nouveau_private *dev_priv = dev->dev_private;
6477 struct nvbios *bios = &dev_priv->vbios;
6480 if (!NVInitVBIOS(dev))
6483 ret = nouveau_parse_vbios_struct(dev);
6487 ret = nouveau_i2c_init(dev);
6491 ret = nouveau_mxm_init(dev);
6495 ret = parse_dcb_table(dev, bios);
6499 if (!bios->major_version) /* we don't run version 0 bios */
6502 /* init script execution disabled */
6503 bios->execute = false;
6505 /* ... unless card isn't POSTed already */
6506 if (!nouveau_bios_posted(dev)) {
6507 NV_INFO(dev, "Adaptor not initialised, "
6508 "running VBIOS init tables.\n");
6509 bios->execute = true;
6511 if (nouveau_force_post)
6512 bios->execute = true;
6514 ret = nouveau_run_vbios_init(dev);
6518 /* feature_byte on BMP is poor, but init always sets CR4B */
6519 if (bios->major_version < 5)
6520 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6522 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6523 if (bios->is_mobile || bios->major_version >= 5)
6524 ret = parse_fp_mode_table(dev, bios);
6526 /* allow subsequent scripts to execute */
6527 bios->execute = true;
6533 nouveau_bios_takedown(struct drm_device *dev)
6535 struct drm_nouveau_private *dev_priv = dev->dev_private;
6537 nouveau_mxm_fini(dev);
6538 nouveau_i2c_fini(dev);
6540 kfree(dev_priv->vbios.data);