drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_panel_use_ssc __read_mostly = -1;
  84 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  85 MODULE_PARM_DESC(lvds_use_ssc,
  86                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  87                 "(default: auto from VBT)");
  88
  89 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  90 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  91 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  92                 "Override selection of SDVO panel mode in the VBT "
  93                 "(default: auto)");
  94
  95 static bool i915_try_reset __read_mostly = true;
  96 module_param_named(reset, i915_try_reset, bool, 0600);
  97 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
  98
  99 bool i915_enable_hangcheck __read_mostly = true;
 100 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 101 MODULE_PARM_DESC(enable_hangcheck,
 102                 "Periodically check GPU activity for detecting hangs. "
 103                 "WARNING: Disabling this can cause system wide hangs. "
 104                 "(default: true)");
 105
 106 bool i915_enable_ppgtt __read_mostly = 1;
 107 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 108 MODULE_PARM_DESC(i915_enable_ppgtt,
 109                 "Enable PPGTT (default: true)");
 110
 111 static struct drm_driver driver;
 112 extern int intel_agp_enabled;
 113
 114 #define INTEL_VGA_DEVICE(id, info) {            \
 115         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 116         .class_mask = 0xff0000,                 \
 117         .vendor = 0x8086,                       \
 118         .device = id,                           \
 119         .subvendor = PCI_ANY_ID,                \
 120         .subdevice = PCI_ANY_ID,                \
 121         .driver_data = (unsigned long) info }
 122
 123 static const struct intel_device_info intel_i830_info = {
 124         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 125         .has_overlay = 1, .overlay_needs_physical = 1,
 126 };
 127
 128 static const struct intel_device_info intel_845g_info = {
 129         .gen = 2,
 130         .has_overlay = 1, .overlay_needs_physical = 1,
 131 };
 132
 133 static const struct intel_device_info intel_i85x_info = {
 134         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 135         .cursor_needs_physical = 1,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i865g_info = {
 140         .gen = 2,
 141         .has_overlay = 1, .overlay_needs_physical = 1,
 142 };
 143
 144 static const struct intel_device_info intel_i915g_info = {
 145         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 146         .has_overlay = 1, .overlay_needs_physical = 1,
 147 };
 148 static const struct intel_device_info intel_i915gm_info = {
 149         .gen = 3, .is_mobile = 1,
 150         .cursor_needs_physical = 1,
 151         .has_overlay = 1, .overlay_needs_physical = 1,
 152         .supports_tv = 1,
 153 };
 154 static const struct intel_device_info intel_i945g_info = {
 155         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 156         .has_overlay = 1, .overlay_needs_physical = 1,
 157 };
 158 static const struct intel_device_info intel_i945gm_info = {
 159         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 160         .has_hotplug = 1, .cursor_needs_physical = 1,
 161         .has_overlay = 1, .overlay_needs_physical = 1,
 162         .supports_tv = 1,
 163 };
 164
 165 static const struct intel_device_info intel_i965g_info = {
 166         .gen = 4, .is_broadwater = 1,
 167         .has_hotplug = 1,
 168         .has_overlay = 1,
 169 };
 170
 171 static const struct intel_device_info intel_i965gm_info = {
 172         .gen = 4, .is_crestline = 1,
 173         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 174         .has_overlay = 1,
 175         .supports_tv = 1,
 176 };
 177
 178 static const struct intel_device_info intel_g33_info = {
 179         .gen = 3, .is_g33 = 1,
 180         .need_gfx_hws = 1, .has_hotplug = 1,
 181         .has_overlay = 1,
 182 };
 183
 184 static const struct intel_device_info intel_g45_info = {
 185         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 186         .has_pipe_cxsr = 1, .has_hotplug = 1,
 187         .has_bsd_ring = 1,
 188 };
 189
 190 static const struct intel_device_info intel_gm45_info = {
 191         .gen = 4, .is_g4x = 1,
 192         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 193         .has_pipe_cxsr = 1, .has_hotplug = 1,
 194         .supports_tv = 1,
 195         .has_bsd_ring = 1,
 196 };
 197
 198 static const struct intel_device_info intel_pineview_info = {
 199         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 200         .need_gfx_hws = 1, .has_hotplug = 1,
 201         .has_overlay = 1,
 202 };
 203
 204 static const struct intel_device_info intel_ironlake_d_info = {
 205         .gen = 5,
 206         .need_gfx_hws = 1, .has_hotplug = 1,
 207         .has_bsd_ring = 1,
 208 };
 209
 210 static const struct intel_device_info intel_ironlake_m_info = {
 211         .gen = 5, .is_mobile = 1,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_fbc = 1,
 214         .has_bsd_ring = 1,
 215 };
 216
 217 static const struct intel_device_info intel_sandybridge_d_info = {
 218         .gen = 6,
 219         .need_gfx_hws = 1, .has_hotplug = 1,
 220         .has_bsd_ring = 1,
 221         .has_blt_ring = 1,
 222         .has_llc = 1,
 223 };
 224
 225 static const struct intel_device_info intel_sandybridge_m_info = {
 226         .gen = 6, .is_mobile = 1,
 227         .need_gfx_hws = 1, .has_hotplug = 1,
 228         .has_fbc = 1,
 229         .has_bsd_ring = 1,
 230         .has_blt_ring = 1,
 231         .has_llc = 1,
 232 };
 233
 234 static const struct intel_device_info intel_ivybridge_d_info = {
 235         .is_ivybridge = 1, .gen = 7,
 236         .need_gfx_hws = 1, .has_hotplug = 1,
 237         .has_bsd_ring = 1,
 238         .has_blt_ring = 1,
 239         .has_llc = 1,
 240 };
 241
 242 static const struct intel_device_info intel_ivybridge_m_info = {
 243         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 244         .need_gfx_hws = 1, .has_hotplug = 1,
 245         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 246         .has_bsd_ring = 1,
 247         .has_blt_ring = 1,
 248         .has_llc = 1,
 249 };
 250
 251 static const struct pci_device_id pciidlist[] = {               /* aka */
 252         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 253         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 254         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 255         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 256         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 257         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 258         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 259         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 260         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 261         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 262         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 263         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 264         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 265         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 266         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 267         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 268         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 269         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 270         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 271         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 272         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 273         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 274         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 275         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 276         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 277         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 278         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 279         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 280         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 281         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 282         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 283         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 284         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 285         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 286         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 287         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 288         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 289         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 290         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 291         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 292         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 293         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 294         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 295         {0, 0, 0}
 296 };
 297
 298 #if defined(CONFIG_DRM_I915_KMS)
 299 MODULE_DEVICE_TABLE(pci, pciidlist);
 300 #endif
 301
 302 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 303 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 304 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 305 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 306
 307 void intel_detect_pch(struct drm_device *dev)
 308 {
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310         struct pci_dev *pch;
 311
 312         /*
 313          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 314          * make graphics device passthrough work easy for VMM, that only
 315          * need to expose ISA bridge to let driver know the real hardware
 316          * underneath. This is a requirement from virtualization team.
 317          */
 318         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 319         if (pch) {
 320                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 321                         int id;
 322                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 323
 324                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 325                                 dev_priv->pch_type = PCH_IBX;
 326                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 327                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 328                                 dev_priv->pch_type = PCH_CPT;
 329                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 330                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 331                                 /* PantherPoint is CPT compatible */
 332                                 dev_priv->pch_type = PCH_CPT;
 333                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 334                         }
 335                 }
 336                 pci_dev_put(pch);
 337         }
 338 }
 339
 340 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 341 {
 342         int count;
 343
 344         count = 0;
 345         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 346                 udelay(10);
 347
 348         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 349         POSTING_READ(FORCEWAKE);
 350
 351         count = 0;
 352         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 353                 udelay(10);
 354 }
 355
 356 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 357 {
 358         int count;
 359
 360         count = 0;
 361         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 362                 udelay(10);
 363
 364         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 365         POSTING_READ(FORCEWAKE_MT);
 366
 367         count = 0;
 368         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 369                 udelay(10);
 370 }
 371
 372 /*
 373  * Generally this is called implicitly by the register read function. However,
 374  * if some sequence requires the GT to not power down then this function should
 375  * be called at the beginning of the sequence followed by a call to
 376  * gen6_gt_force_wake_put() at the end of the sequence.
 377  */
 378 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 379 {
 380         unsigned long irqflags;
 381
 382         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 383         if (dev_priv->forcewake_count++ == 0)
 384                 dev_priv->display.force_wake_get(dev_priv);
 385         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 386 }
 387
 388 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 389 {
 390         u32 gtfifodbg;
 391         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 392         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 393              "MMIO read or write has been dropped %x\n", gtfifodbg))
 394                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 395 }
 396
 397 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 398 {
 399         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 400         /* The below doubles as a POSTING_READ */
 401         gen6_gt_check_fifodbg(dev_priv);
 402 }
 403
 404 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 405 {
 406         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 407         /* The below doubles as a POSTING_READ */
 408         gen6_gt_check_fifodbg(dev_priv);
 409 }
 410
 411 /*
 412  * see gen6_gt_force_wake_get()
 413  */
 414 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 415 {
 416         unsigned long irqflags;
 417
 418         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 419         if (--dev_priv->forcewake_count == 0)
 420                 dev_priv->display.force_wake_put(dev_priv);
 421         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 422 }
 423
 424 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 425 {
 426         int ret = 0;
 427
 428         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 429                 int loop = 500;
 430                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 431                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 432                         udelay(10);
 433                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 434                 }
 435                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 436                         ++ret;
 437                 dev_priv->gt_fifo_count = fifo;
 438         }
 439         dev_priv->gt_fifo_count--;
 440
 441         return ret;
 442 }
 443
 444 static int i915_drm_freeze(struct drm_device *dev)
 445 {
 446         struct drm_i915_private *dev_priv = dev->dev_private;
 447
 448         drm_kms_helper_poll_disable(dev);
 449
 450         pci_save_state(dev->pdev);
 451
 452         /* If KMS is active, we do the leavevt stuff here */
 453         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 454                 int error = i915_gem_idle(dev);
 455                 if (error) {
 456                         dev_err(&dev->pdev->dev,
 457                                 "GEM idle failed, resume might fail\n");
 458                         return error;
 459                 }
 460                 drm_irq_uninstall(dev);
 461         }
 462
 463         i915_save_state(dev);
 464
 465         intel_opregion_fini(dev);
 466
 467         /* Modeset on resume, not lid events */
 468         dev_priv->modeset_on_lid = 0;
 469
 470         console_lock();
 471         intel_fbdev_set_suspend(dev, 1);
 472         console_unlock();
 473
 474         return 0;
 475 }
 476
 477 int i915_suspend(struct drm_device *dev, pm_message_t state)
 478 {
 479         int error;
 480
 481         if (!dev || !dev->dev_private) {
 482                 DRM_ERROR("dev: %p\n", dev);
 483                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 484                 return -ENODEV;
 485         }
 486
 487         if (state.event == PM_EVENT_PRETHAW)
 488                 return 0;
 489
 490
 491         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 492                 return 0;
 493
 494         error = i915_drm_freeze(dev);
 495         if (error)
 496                 return error;
 497
 498         if (state.event == PM_EVENT_SUSPEND) {
 499                 /* Shut down the device */
 500                 pci_disable_device(dev->pdev);
 501                 pci_set_power_state(dev->pdev, PCI_D3hot);
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int i915_drm_thaw(struct drm_device *dev)
 508 {
 509         struct drm_i915_private *dev_priv = dev->dev_private;
 510         int error = 0;
 511
 512         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 513                 mutex_lock(&dev->struct_mutex);
 514                 i915_gem_restore_gtt_mappings(dev);
 515                 mutex_unlock(&dev->struct_mutex);
 516         }
 517
 518         i915_restore_state(dev);
 519         intel_opregion_setup(dev);
 520
 521         /* KMS EnterVT equivalent */
 522         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 523                 mutex_lock(&dev->struct_mutex);
 524                 dev_priv->mm.suspended = 0;
 525
 526                 error = i915_gem_init_hw(dev);
 527                 mutex_unlock(&dev->struct_mutex);
 528
 529                 if (HAS_PCH_SPLIT(dev))
 530                         ironlake_init_pch_refclk(dev);
 531
 532                 drm_mode_config_reset(dev);
 533                 drm_irq_install(dev);
 534
 535                 /* Resume the modeset for every activated CRTC */
 536                 drm_helper_resume_force_mode(dev);
 537
 538                 if (IS_IRONLAKE_M(dev))
 539                         ironlake_enable_rc6(dev);
 540         }
 541
 542         intel_opregion_init(dev);
 543
 544         dev_priv->modeset_on_lid = 0;
 545
 546         console_lock();
 547         intel_fbdev_set_suspend(dev, 0);
 548         console_unlock();
 549         return error;
 550 }
 551
 552 int i915_resume(struct drm_device *dev)
 553 {
 554         int ret;
 555
 556         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 557                 return 0;
 558
 559         if (pci_enable_device(dev->pdev))
 560                 return -EIO;
 561
 562         pci_set_master(dev->pdev);
 563
 564         ret = i915_drm_thaw(dev);
 565         if (ret)
 566                 return ret;
 567
 568         drm_kms_helper_poll_enable(dev);
 569         return 0;
 570 }
 571
 572 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 573 {
 574         struct drm_i915_private *dev_priv = dev->dev_private;
 575
 576         if (IS_I85X(dev))
 577                 return -ENODEV;
 578
 579         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 580         POSTING_READ(D_STATE);
 581
 582         if (IS_I830(dev) || IS_845G(dev)) {
 583                 I915_WRITE(DEBUG_RESET_I830,
 584                            DEBUG_RESET_DISPLAY |
 585                            DEBUG_RESET_RENDER |
 586                            DEBUG_RESET_FULL);
 587                 POSTING_READ(DEBUG_RESET_I830);
 588                 msleep(1);
 589
 590                 I915_WRITE(DEBUG_RESET_I830, 0);
 591                 POSTING_READ(DEBUG_RESET_I830);
 592         }
 593
 594         msleep(1);
 595
 596         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 597         POSTING_READ(D_STATE);
 598
 599         return 0;
 600 }
 601
 602 static int i965_reset_complete(struct drm_device *dev)
 603 {
 604         u8 gdrst;
 605         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 606         return gdrst & 0x1;
 607 }
 608
 609 static int i965_do_reset(struct drm_device *dev, u8 flags)
 610 {
 611         u8 gdrst;
 612
 613         /*
 614          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 615          * well as the reset bit (GR/bit 0).  Setting the GR bit
 616          * triggers the reset; when done, the hardware will clear it.
 617          */
 618         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 619         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 620
 621         return wait_for(i965_reset_complete(dev), 500);
 622 }
 623
 624 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 625 {
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 628         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 629         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 630 }
 631
 632 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 633 {
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         int     ret;
 636         unsigned long irqflags;
 637
 638         /* Hold gt_lock across reset to prevent any register access
 639          * with forcewake not set correctly
 640          */
 641         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 642
 643         /* Reset the chip */
 644
 645         /* GEN6_GDRST is not in the gt power well, no need to check
 646          * for fifo space for the write or forcewake the chip for
 647          * the read
 648          */
 649         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 650
 651         /* Spin waiting for the device to ack the reset request */
 652         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 653
 654         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 655         if (dev_priv->forcewake_count)
 656                 dev_priv->display.force_wake_get(dev_priv);
 657         else
 658                 dev_priv->display.force_wake_put(dev_priv);
 659
 660         /* Restore fifo count */
 661         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 662
 663         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 664         return ret;
 665 }
 666
 667 /**
 668  * i915_reset - reset chip after a hang
 669  * @dev: drm device to reset
 670  * @flags: reset domains
 671  *
 672  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 673  * reset or otherwise an error code.
 674  *
 675  * Procedure is fairly simple:
 676  *   - reset the chip using the reset reg
 677  *   - re-init context state
 678  *   - re-init hardware status page
 679  *   - re-init ring buffer
 680  *   - re-init interrupt state
 681  *   - re-init display
 682  */
 683 int i915_reset(struct drm_device *dev, u8 flags)
 684 {
 685         drm_i915_private_t *dev_priv = dev->dev_private;
 686         /*
 687          * We really should only reset the display subsystem if we actually
 688          * need to
 689          */
 690         bool need_display = true;
 691         int ret;
 692
 693         if (!i915_try_reset)
 694                 return 0;
 695
 696         if (!mutex_trylock(&dev->struct_mutex))
 697                 return -EBUSY;
 698
 699         i915_gem_reset(dev);
 700
 701         ret = -ENODEV;
 702         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 703                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 704         } else switch (INTEL_INFO(dev)->gen) {
 705         case 7:
 706         case 6:
 707                 ret = gen6_do_reset(dev, flags);
 708                 break;
 709         case 5:
 710                 ret = ironlake_do_reset(dev, flags);
 711                 break;
 712         case 4:
 713                 ret = i965_do_reset(dev, flags);
 714                 break;
 715         case 2:
 716                 ret = i8xx_do_reset(dev, flags);
 717                 break;
 718         }
 719         dev_priv->last_gpu_reset = get_seconds();
 720         if (ret) {
 721                 DRM_ERROR("Failed to reset chip.\n");
 722                 mutex_unlock(&dev->struct_mutex);
 723                 return ret;
 724         }
 725
 726         /* Ok, now get things going again... */
 727
 728         /*
 729          * Everything depends on having the GTT running, so we need to start
 730          * there.  Fortunately we don't need to do this unless we reset the
 731          * chip at a PCI level.
 732          *
 733          * Next we need to restore the context, but we don't use those
 734          * yet either...
 735          *
 736          * Ring buffer needs to be re-initialized in the KMS case, or if X
 737          * was running at the time of the reset (i.e. we weren't VT
 738          * switched away).
 739          */
 740         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 741                         !dev_priv->mm.suspended) {
 742                 dev_priv->mm.suspended = 0;
 743
 744                 i915_gem_init_swizzling(dev);
 745
 746                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 747                 if (HAS_BSD(dev))
 748                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 749                 if (HAS_BLT(dev))
 750                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 751
 752                 i915_gem_init_ppgtt(dev);
 753
 754                 mutex_unlock(&dev->struct_mutex);
 755                 drm_irq_uninstall(dev);
 756                 drm_mode_config_reset(dev);
 757                 drm_irq_install(dev);
 758                 mutex_lock(&dev->struct_mutex);
 759         }
 760
 761         mutex_unlock(&dev->struct_mutex);
 762
 763         /*
 764          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 765          * need to retrain the display link and cannot just restore the register
 766          * values.
 767          */
 768         if (need_display) {
 769                 mutex_lock(&dev->mode_config.mutex);
 770                 drm_helper_resume_force_mode(dev);
 771                 mutex_unlock(&dev->mode_config.mutex);
 772         }
 773
 774         return 0;
 775 }
 776
 777
 778 static int __devinit
 779 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 780 {
 781         /* Only bind to function 0 of the device. Early generations
 782          * used function 1 as a placeholder for multi-head. This causes
 783          * us confusion instead, especially on the systems where both
 784          * functions have the same PCI-ID!
 785          */
 786         if (PCI_FUNC(pdev->devfn))
 787                 return -ENODEV;
 788
 789         return drm_get_pci_dev(pdev, ent, &driver);
 790 }
 791
 792 static void
 793 i915_pci_remove(struct pci_dev *pdev)
 794 {
 795         struct drm_device *dev = pci_get_drvdata(pdev);
 796
 797         drm_put_dev(dev);
 798 }
 799
 800 static int i915_pm_suspend(struct device *dev)
 801 {
 802         struct pci_dev *pdev = to_pci_dev(dev);
 803         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 804         int error;
 805
 806         if (!drm_dev || !drm_dev->dev_private) {
 807                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 808                 return -ENODEV;
 809         }
 810
 811         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 812                 return 0;
 813
 814         error = i915_drm_freeze(drm_dev);
 815         if (error)
 816                 return error;
 817
 818         pci_disable_device(pdev);
 819         pci_set_power_state(pdev, PCI_D3hot);
 820
 821         return 0;
 822 }
 823
 824 static int i915_pm_resume(struct device *dev)
 825 {
 826         struct pci_dev *pdev = to_pci_dev(dev);
 827         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 828
 829         return i915_resume(drm_dev);
 830 }
 831
 832 static int i915_pm_freeze(struct device *dev)
 833 {
 834         struct pci_dev *pdev = to_pci_dev(dev);
 835         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 836
 837         if (!drm_dev || !drm_dev->dev_private) {
 838                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 839                 return -ENODEV;
 840         }
 841
 842         return i915_drm_freeze(drm_dev);
 843 }
 844
 845 static int i915_pm_thaw(struct device *dev)
 846 {
 847         struct pci_dev *pdev = to_pci_dev(dev);
 848         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 849
 850         return i915_drm_thaw(drm_dev);
 851 }
 852
 853 static int i915_pm_poweroff(struct device *dev)
 854 {
 855         struct pci_dev *pdev = to_pci_dev(dev);
 856         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 857
 858         return i915_drm_freeze(drm_dev);
 859 }
 860
 861 static const struct dev_pm_ops i915_pm_ops = {
 862         .suspend = i915_pm_suspend,
 863         .resume = i915_pm_resume,
 864         .freeze = i915_pm_freeze,
 865         .thaw = i915_pm_thaw,
 866         .poweroff = i915_pm_poweroff,
 867         .restore = i915_pm_resume,
 868 };
 869
 870 static struct vm_operations_struct i915_gem_vm_ops = {
 871         .fault = i915_gem_fault,
 872         .open = drm_gem_vm_open,
 873         .close = drm_gem_vm_close,
 874 };
 875
 876 static const struct file_operations i915_driver_fops = {
 877         .owner = THIS_MODULE,
 878         .open = drm_open,
 879         .release = drm_release,
 880         .unlocked_ioctl = drm_ioctl,
 881         .mmap = drm_gem_mmap,
 882         .poll = drm_poll,
 883         .fasync = drm_fasync,
 884         .read = drm_read,
 885 #ifdef CONFIG_COMPAT
 886         .compat_ioctl = i915_compat_ioctl,
 887 #endif
 888         .llseek = noop_llseek,
 889 };
 890
 891 static struct drm_driver driver = {
 892         /* Don't use MTRRs here; the Xserver or userspace app should
 893          * deal with them for Intel hardware.
 894          */
 895         .driver_features =
 896             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 897             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 898         .load = i915_driver_load,
 899         .unload = i915_driver_unload,
 900         .open = i915_driver_open,
 901         .lastclose = i915_driver_lastclose,
 902         .preclose = i915_driver_preclose,
 903         .postclose = i915_driver_postclose,
 904
 905         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 906         .suspend = i915_suspend,
 907         .resume = i915_resume,
 908
 909         .device_is_agp = i915_driver_device_is_agp,
 910         .reclaim_buffers = drm_core_reclaim_buffers,
 911         .master_create = i915_master_create,
 912         .master_destroy = i915_master_destroy,
 913 #if defined(CONFIG_DEBUG_FS)
 914         .debugfs_init = i915_debugfs_init,
 915         .debugfs_cleanup = i915_debugfs_cleanup,
 916 #endif
 917         .gem_init_object = i915_gem_init_object,
 918         .gem_free_object = i915_gem_free_object,
 919         .gem_vm_ops = &i915_gem_vm_ops,
 920         .dumb_create = i915_gem_dumb_create,
 921         .dumb_map_offset = i915_gem_mmap_gtt,
 922         .dumb_destroy = i915_gem_dumb_destroy,
 923         .ioctls = i915_ioctls,
 924         .fops = &i915_driver_fops,
 925         .name = DRIVER_NAME,
 926         .desc = DRIVER_DESC,
 927         .date = DRIVER_DATE,
 928         .major = DRIVER_MAJOR,
 929         .minor = DRIVER_MINOR,
 930         .patchlevel = DRIVER_PATCHLEVEL,
 931 };
 932
 933 static struct pci_driver i915_pci_driver = {
 934         .name = DRIVER_NAME,
 935         .id_table = pciidlist,
 936         .probe = i915_pci_probe,
 937         .remove = i915_pci_remove,
 938         .driver.pm = &i915_pm_ops,
 939 };
 940
 941 static int __init i915_init(void)
 942 {
 943         if (!intel_agp_enabled) {
 944                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 945                 return -ENODEV;
 946         }
 947
 948         driver.num_ioctls = i915_max_ioctl;
 949
 950         /*
 951          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 952          * explicitly disabled with the module pararmeter.
 953          *
 954          * Otherwise, just follow the parameter (defaulting to off).
 955          *
 956          * Allow optional vga_text_mode_force boot option to override
 957          * the default behavior.
 958          */
 959 #if defined(CONFIG_DRM_I915_KMS)
 960         if (i915_modeset != 0)
 961                 driver.driver_features |= DRIVER_MODESET;
 962 #endif
 963         if (i915_modeset == 1)
 964                 driver.driver_features |= DRIVER_MODESET;
 965
 966 #ifdef CONFIG_VGA_CONSOLE
 967         if (vgacon_text_force() && i915_modeset == -1)
 968                 driver.driver_features &= ~DRIVER_MODESET;
 969 #endif
 970
 971         if (!(driver.driver_features & DRIVER_MODESET))
 972                 driver.get_vblank_timestamp = NULL;
 973
 974         return drm_pci_init(&driver, &i915_pci_driver);
 975 }
 976
 977 static void __exit i915_exit(void)
 978 {
 979         drm_pci_exit(&driver, &i915_pci_driver);
 980 }
 981
 982 module_init(i915_init);
 983 module_exit(i915_exit);
 984
 985 MODULE_AUTHOR(DRIVER_AUTHOR);
 986 MODULE_DESCRIPTION(DRIVER_DESC);
 987 MODULE_LICENSE("GPL and additional rights");
 988
 989 #define __i915_read(x, y) \
 990 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 991         u##x val = 0; \
 992         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 993                 unsigned long irqflags; \
 994                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
 995                 if (dev_priv->forcewake_count == 0) \
 996                         dev_priv->display.force_wake_get(dev_priv); \
 997                 val = read##y(dev_priv->regs + reg); \
 998                 if (dev_priv->forcewake_count == 0) \
 999                         dev_priv->display.force_wake_put(dev_priv); \
1000                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1001         } else { \
1002                 val = read##y(dev_priv->regs + reg); \
1003         } \
1004         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1005         return val; \
1006 }
1007
1008 __i915_read(8, b)
1009 __i915_read(16, w)
1010 __i915_read(32, l)
1011 __i915_read(64, q)
1012 #undef __i915_read
1013
1014 #define __i915_write(x, y) \
1015 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1016         u32 __fifo_ret = 0; \
1017         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1018         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1019                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1020         } \
1021         write##y(val, dev_priv->regs + reg); \
1022         if (unlikely(__fifo_ret)) { \
1023                 gen6_gt_check_fifodbg(dev_priv); \
1024         } \
1025 }
1026 __i915_write(8, b)
1027 __i915_write(16, w)
1028 __i915_write(32, l)
1029 __i915_write(64, q)
1030 #undef __i915_write