2 * linux/arch/alpha/kernel/sys_nautilus.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1998 Richard Henderson
6 * Copyright (C) 1999 Alpha Processor, Inc.,
7 * (David Daniel, Stig Telfer, Soohoon Lee)
9 * Code supporting NAUTILUS systems.
12 * NAUTILUS has the following I/O features:
14 * a) Driven by AMD 751 aka IRONGATE (northbridge):
18 * b) Driven by ALI M1543C (southbridge)
21 * 1 dual drive capable FDD controller
23 * 1 ECP/EPP/SP parallel port
27 #include <linux/kernel.h>
28 #include <linux/types.h>
30 #include <linux/sched.h>
31 #include <linux/pci.h>
32 #include <linux/init.h>
33 #include <linux/reboot.h>
35 #include <asm/ptrace.h>
36 #include <asm/system.h>
39 #include <asm/bitops.h>
40 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/core_irongate.h>
45 #include <asm/hwrpb.h>
50 #include "machvec_impl.h"
54 nautilus_init_irq(void)
56 if (alpha_using_srm) {
57 alpha_mv.device_interrupt = srm_device_interrupt;
58 alpha_mv.kill_arch = NULL;
62 common_init_isa_dma();
66 nautilus_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
68 /* Preserve the IRQ set up by the console. */
71 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
76 nautilus_kill_arch(int mode)
79 case LINUX_REBOOT_CMD_RESTART:
82 pcibios_read_config_byte(0, 0x38, 0x43, &t8);
83 pcibios_write_config_byte(0, 0x38, 0x43, t8 | 0x80);
90 case LINUX_REBOOT_CMD_POWER_OFF:
93 pcibios_read_config_dword(0, 0x88, 0x10, &pmuport);
95 outl(0xffff, pmuport); /* clear pending events */
96 outw(0x2000, pmuport+4); /* power off */
103 /* Machine check handler code
105 * Perform analysis of a machine check that was triggered by the EV6
106 * CPU's fault-detection mechanism.
109 /* IPR structures for EV6, containing the necessary data for the
110 * machine check handler to unpick the logout frame
115 #define EV6__I_STAT__PAR ( 1 << 29 )
119 #define EV6__MM_STAT__DC_TAG_PERR ( 1 << 10 )
123 #define EV6__DC_STAT__SEO ( 1 << 4 )
124 #define EV6__DC_STAT__ECC_ERR_LD ( 1 << 3 )
125 #define EV6__DC_STAT__ECC_ERR_ST ( 1 << 2 )
126 #define EV6__DC_STAT__TPERR_P1 ( 1 << 1 )
127 #define EV6__DC_STAT__TPERR_P0 ( 1 )
131 #define EV6__C_STAT__BC_PERR ( 0x01 )
132 #define EV6__C_STAT__DC_PERR ( 0x02 )
133 #define EV6__C_STAT__DSTREAM_MEM_ERR ( 0x03 )
134 #define EV6__C_STAT__DSTREAM_BC_ERR ( 0x04 )
135 #define EV6__C_STAT__DSTREAM_DC_ERR ( 0x05 )
136 #define EV6__C_STAT__PROBE_BC_ERR0 ( 0x06 )
137 #define EV6__C_STAT__PROBE_BC_ERR1 ( 0x07 )
138 #define EV6__C_STAT__ISTREAM_MEM_ERR ( 0x0B )
139 #define EV6__C_STAT__ISTREAM_BC_ERR ( 0x0C )
140 #define EV6__C_STAT__DSTREAM_MEM_DBL ( 0x13 )
141 #define EV6__C_STAT__DSTREAM_BC_DBL ( 0x14 )
142 #define EV6__C_STAT__ISTREAM_MEM_DBL ( 0x1B )
143 #define EV6__C_STAT__ISTREAM_BC_DBL ( 0x1C )
146 /* Take the two syndromes from the CBOX error chain and convert them
147 * into a bit number. */
149 /* NOTE - since I don't know of any difference between C0 and C1 I
150 just ignore C1, since in all cases I've seen so far they are
153 static const unsigned char ev6_bit_to_syndrome[72] =
155 0xce, 0xcb, 0xd3, 0xd5, 0xd6, 0xd9, 0xda, 0xdc, /* 0 */
156 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34, /* 8 */
157 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c, /* 16 */
158 0xe3, 0xe5, 0xe6, 0xe9, 0xea, 0xec, 0xf1, 0xf4, /* 24 */
159 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d, /* 32 */
160 0xa2, 0xa4, 0xa7, 0xa8, 0xab, 0xad, 0xb0, 0xb5, /* 40 */
161 0x8f, 0x8a, 0x92, 0x94, 0x97, 0x98, 0x9b, 0x9d, /* 48 */
162 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75, /* 56 */
163 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 /* 64 */
167 static int ev6_syn2bit(unsigned long c0, unsigned long c1)
171 for (bit = 0; bit < 72; bit++)
172 if (ev6_bit_to_syndrome[bit] == c0) return bit;
173 for (bit = 0; bit < 72; bit++)
174 if (ev6_bit_to_syndrome[bit] == c1) return bit + 64;
176 return -1; /* not found */
180 /* Single bit ECC errors are categorized here. */
183 static const char *interr = "CPU internal error";
184 static const char *slotb= "Slot-B error";
185 static const char *membus= "Memory/EV6-bus error";
187 static const char *interr = "";
188 static const char *slotb = "";
189 static const char *membus = "";
193 ev6_crd_interp(char *interp, struct el_common_EV6_mcheck * L)
195 /* Icache data or tag parity error. */
196 if (L->I_STAT & EV6__I_STAT__PAR) {
197 sprintf(interp, "%s: I_STAT[PAR]\n "
198 "Icache data or tag parity error", interr);
202 /* Dcache tag parity error (on issue) (DFAULT). */
203 if (L->MM_STAT & EV6__MM_STAT__DC_TAG_PERR) {
204 sprintf(interp, "%s: MM_STAT[DC_TAG_PERR]\n "
205 "Dcache tag parity error(on issue)", interr);
209 /* Errors relating to D-stream set non-zero DC_STAT.
211 switch (L->DC_STAT & (EV6__DC_STAT__ECC_ERR_ST
212 | EV6__DC_STAT__ECC_ERR_LD)) {
213 case EV6__DC_STAT__ECC_ERR_ST:
214 /* Dcache single-bit ECC error on small store */
215 sprintf(interp, "%s: DC_STAT[ECC_ERR_ST]\n "
216 "Dcache single-bit ECC error on small store", interr);
219 case EV6__DC_STAT__ECC_ERR_LD:
222 /* Dcache single-bit error on speculative load */
223 /* Bcache victim read on Dcache/Bcache miss */
224 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT=0\n "
225 "Dcache single-bit ECC error on speculative load",
229 case EV6__C_STAT__DSTREAM_DC_ERR:
230 /* Dcache single bit error on load */
231 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT[DSTREAM_DC_ERR]\n"
232 " Dcache single-bit ECC error on speculative load, bit %d",
233 interr, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME));
236 case EV6__C_STAT__DSTREAM_BC_ERR:
237 /* Bcache single-bit error on Dcache fill */
238 sprintf(interp, "%s: DC_STAT[ECC_ERR_LD] C_STAT[DSTREAM_BC_ERR]\n"
239 " Bcache single-bit error on Dcache fill, bit %d",
240 slotb, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME));
243 case EV6__C_STAT__DSTREAM_MEM_ERR:
244 /* Memory single-bit error on Dcache fill */
245 sprintf(interp, "%s (to Dcache): DC_STAT[ECC_ERR_LD] "
246 "C_STAT[DSTREAM_MEM_ERR]\n "
247 "Memory single-bit error on Dcache fill, "
248 "Address 0x%lX, bit %d",
249 membus, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME,
255 /* I-stream, other misc errors go on C_STAT alone */
257 case EV6__C_STAT__ISTREAM_BC_ERR:
258 /* Bcache single-bit error on Icache fill (also MCHK) */
259 sprintf(interp, "%s: C_STAT[ISTREAM_BC_ERR]\n "
260 "Bcache single-bit error on Icache fill, bit %d",
261 slotb, ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME));
264 case EV6__C_STAT__ISTREAM_MEM_ERR:
265 /* Memory single-bit error on Icache fill (also MCHK) */
266 sprintf(interp, "%s : C_STATISTREAM_MEM_ERR]\n "
267 "Memory single-bit error on Icache fill "
268 "addr 0x%lX, bit %d",
269 membus, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME,
273 case EV6__C_STAT__PROBE_BC_ERR0:
274 case EV6__C_STAT__PROBE_BC_ERR1:
275 /* Bcache single-bit error on a probe hit */
276 sprintf(interp, "%s: C_STAT[PROBE_BC_ERR]\n "
277 "Bcache single-bit error on a probe hit, "
278 "addr 0x%lx, bit %d",
279 slotb, L->C_ADDR, ev6_syn2bit(L->DC0_SYNDROME,
286 ev6_mchk_interp(char *interp, struct el_common_EV6_mcheck * L)
288 /* Machine check errors described by DC_STAT */
289 switch (L->DC_STAT) {
290 case EV6__DC_STAT__TPERR_P0:
291 case EV6__DC_STAT__TPERR_P1:
292 /* Dcache tag parity error (on retry) */
293 sprintf(interp, "%s: DC_STAT[TPERR_P0|TPERR_P1]\n "
294 "Dcache tag parity error(on retry)", interr);
297 case EV6__DC_STAT__SEO:
298 /* Dcache second error on store */
299 sprintf(interp, "%s: DC_STAT[SEO]\n "
300 "Dcache second error during mcheck", interr);
304 /* Machine check errors described by C_STAT */
306 case EV6__C_STAT__DC_PERR:
307 /* Dcache duplicate tag parity error */
308 sprintf(interp, "%s: C_STAT[DC_PERR]\n "
309 "Dcache duplicate tag parity error at 0x%lX",
313 case EV6__C_STAT__BC_PERR:
314 /* Bcache tag parity error */
315 sprintf(interp, "%s: C_STAT[BC_PERR]\n "
316 "Bcache tag parity error at 0x%lX",
320 case EV6__C_STAT__ISTREAM_BC_ERR:
321 /* Bcache single-bit error on Icache fill (also CRD) */
322 sprintf(interp, "%s: C_STAT[ISTREAM_BC_ERR]\n "
323 "Bcache single-bit error on Icache fill 0x%lX bit %d",
325 ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME));
329 case EV6__C_STAT__ISTREAM_MEM_ERR:
330 /* Memory single-bit error on Icache fill (also CRD) */
331 sprintf(interp, "%s: C_STAT[ISTREAM_MEM_ERR]\n "
332 "Memory single-bit error on Icache fill 0x%lX, bit %d",
334 ev6_syn2bit(L->DC0_SYNDROME, L->DC1_SYNDROME));
338 case EV6__C_STAT__ISTREAM_BC_DBL:
339 /* Bcache double-bit error on Icache fill */
340 sprintf(interp, "%s: C_STAT[ISTREAM_BC_DBL]\n "
341 "Bcache double-bit error on Icache fill at 0x%lX",
344 case EV6__C_STAT__DSTREAM_BC_DBL:
345 /* Bcache double-bit error on Dcache fill */
346 sprintf(interp, "%s: C_STAT[DSTREAM_BC_DBL]\n "
347 "Bcache double-bit error on Dcache fill at 0x%lX",
351 case EV6__C_STAT__ISTREAM_MEM_DBL:
352 /* Memory double-bit error on Icache fill */
353 sprintf(interp, "%s: C_STAT[ISTREAM_MEM_DBL]\n "
354 "Memory double-bit error on Icache fill at 0x%lX",
358 case EV6__C_STAT__DSTREAM_MEM_DBL:
359 /* Memory double-bit error on Dcache fill */
360 sprintf(interp, "%s: C_STAT[DSTREAM_MEM_DBL]\n "
361 "Memory double-bit error on Dcache fill at 0x%lX",
368 ev6_cpu_machine_check(unsigned long vector, struct el_common_EV6_mcheck *L,
369 struct pt_regs *regs)
373 /* This is verbose and looks intimidating. Should it be printed for
374 corrected (CRD) machine checks? */
376 printk(KERN_CRIT "PALcode logout frame: "
378 "MCHK_Frame_Rev %d\n"
397 L->MCHK_Code, L->MCHK_Frame_Rev, L->I_STAT, L->DC_STAT,
398 L->C_ADDR, L->DC1_SYNDROME, L->DC0_SYNDROME, L->C_STAT,
399 L->C_STS, L->RESERVED0, L->EXC_ADDR, L->IER_CM, L->ISUM,
400 L->MM_STAT, L->PAL_BASE, L->I_CTL, L->PCTX,
401 regs->pc, regs->r26);
403 /* Attempt an interpretation on the meanings of the fields above. */
404 sprintf(interp, "No interpretation available!" );
405 if (vector == SCB_Q_PROCERR)
406 ev6_crd_interp(interp, L);
407 else if (vector == SCB_Q_PROCMCHK)
408 ev6_mchk_interp(interp, L);
410 printk(KERN_CRIT "interpretation: %s\n\n", interp);
414 /* Perform analysis of a machine check that arrived from the system (NMI) */
417 naut_sys_machine_check(unsigned long vector, unsigned long la_ptr,
418 struct pt_regs *regs)
420 printk("xtime %lx\n", CURRENT_TIME);
421 printk("PC %lx RA %lx\n", regs->pc, regs->r26);
422 irongate_pci_clr_err();
425 /* Machine checks can come from two sources - those on the CPU and those
426 in the system. They are analysed separately but all starts here. */
429 nautilus_machine_check(unsigned long vector, unsigned long la_ptr,
430 struct pt_regs *regs)
433 unsigned cpu_analysis=0, sys_analysis=0;
435 /* Now for some analysis. Machine checks fall into two classes --
436 those picked up by the system, and those picked up by the CPU.
437 Add to that the two levels of severity - correctable or not. */
439 if (vector == SCB_Q_SYSMCHK
440 && ((IRONGATE0->dramms & 0x300) == 0x300)) {
441 unsigned long nmi_ctl;
450 /* Write again clears error bits. */
451 IRONGATE0->stat_cmd = IRONGATE0->stat_cmd & ~0x100;
455 /* Write again clears error bits. */
456 IRONGATE0->dramms = IRONGATE0->dramms;
468 mchk_class = "Correctable System Machine Check (NMI)";
472 mchk_class = "Fatal System Machine Check (NMI)";
477 mchk_class = "Correctable Processor Machine Check";
481 mchk_class = "Fatal Processor Machine Check";
486 mchk_class = "Unknown vector!";
490 printk(KERN_CRIT "NAUTILUS Machine check 0x%lx [%s]\n",
494 ev6_cpu_machine_check(vector,
495 (struct el_common_EV6_mcheck *)la_ptr,
498 naut_sys_machine_check(vector, la_ptr, regs);
500 /* Tell the PALcode to clear the machine check */
512 struct alpha_machine_vector nautilus_mv __initmv = {
513 vector_name: "Nautilus",
518 machine_check: nautilus_machine_check,
519 max_dma_address: ALPHA_NAUTILUS_MAX_DMA_ADDRESS,
520 min_io_address: DEFAULT_IO_BASE,
521 min_mem_address: DEFAULT_MEM_BASE,
524 device_interrupt: isa_device_interrupt,
526 init_arch: irongate_init_arch,
527 init_irq: nautilus_init_irq,
528 init_rtc: common_init_rtc,
529 init_pci: common_init_pci,
530 kill_arch: nautilus_kill_arch,
531 pci_map_irq: nautilus_map_irq,
532 pci_swizzle: common_swizzle,