arch/arm/mach-shmobile/setup-sh73a0.c

   1 /*
   2  * sh73a0 processor support
   3  *
   4  * Copyright (C) 2010  Takashi Yoshii
   5  * Copyright (C) 2010  Magnus Damm
   6  * Copyright (C) 2008  Yoshihiro Shimoda
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/input.h>
  28 #include <linux/io.h>
  29 #include <linux/serial_sci.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/sh_intc.h>
  32 #include <linux/sh_timer.h>
  33 #include <mach/hardware.h>
  34 #include <mach/sh73a0.h>
  35 #include <mach/common.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/time.h>
  40
  41 static struct map_desc sh73a0_io_desc[] __initdata = {
  42         /* create a 1:1 entity map for 0xe6xxxxxx
  43          * used by CPGA, INTC and PFC.
  44          */
  45         {
  46                 .virtual        = 0xe6000000,
  47                 .pfn            = __phys_to_pfn(0xe6000000),
  48                 .length         = 256 << 20,
  49                 .type           = MT_DEVICE_NONSHARED
  50         },
  51 };
  52
  53 void __init sh73a0_map_io(void)
  54 {
  55         iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
  56 }
  57
  58 static struct plat_sci_port scif0_platform_data = {
  59         .mapbase        = 0xe6c40000,
  60         .flags          = UPF_BOOT_AUTOCONF,
  61         .scscr          = SCSCR_RE | SCSCR_TE,
  62         .scbrr_algo_id  = SCBRR_ALGO_4,
  63         .type           = PORT_SCIFA,
  64         .irqs           = { gic_spi(72), gic_spi(72),
  65                             gic_spi(72), gic_spi(72) },
  66 };
  67
  68 static struct platform_device scif0_device = {
  69         .name           = "sh-sci",
  70         .id             = 0,
  71         .dev            = {
  72                 .platform_data  = &scif0_platform_data,
  73         },
  74 };
  75
  76 static struct plat_sci_port scif1_platform_data = {
  77         .mapbase        = 0xe6c50000,
  78         .flags          = UPF_BOOT_AUTOCONF,
  79         .scscr          = SCSCR_RE | SCSCR_TE,
  80         .scbrr_algo_id  = SCBRR_ALGO_4,
  81         .type           = PORT_SCIFA,
  82         .irqs           = { gic_spi(73), gic_spi(73),
  83                             gic_spi(73), gic_spi(73) },
  84 };
  85
  86 static struct platform_device scif1_device = {
  87         .name           = "sh-sci",
  88         .id             = 1,
  89         .dev            = {
  90                 .platform_data  = &scif1_platform_data,
  91         },
  92 };
  93
  94 static struct plat_sci_port scif2_platform_data = {
  95         .mapbase        = 0xe6c60000,
  96         .flags          = UPF_BOOT_AUTOCONF,
  97         .scscr          = SCSCR_RE | SCSCR_TE,
  98         .scbrr_algo_id  = SCBRR_ALGO_4,
  99         .type           = PORT_SCIFA,
 100         .irqs           = { gic_spi(74), gic_spi(74),
 101                             gic_spi(74), gic_spi(74) },
 102 };
 103
 104 static struct platform_device scif2_device = {
 105         .name           = "sh-sci",
 106         .id             = 2,
 107         .dev            = {
 108                 .platform_data  = &scif2_platform_data,
 109         },
 110 };
 111
 112 static struct plat_sci_port scif3_platform_data = {
 113         .mapbase        = 0xe6c70000,
 114         .flags          = UPF_BOOT_AUTOCONF,
 115         .scscr          = SCSCR_RE | SCSCR_TE,
 116         .scbrr_algo_id  = SCBRR_ALGO_4,
 117         .type           = PORT_SCIFA,
 118         .irqs           = { gic_spi(75), gic_spi(75),
 119                             gic_spi(75), gic_spi(75) },
 120 };
 121
 122 static struct platform_device scif3_device = {
 123         .name           = "sh-sci",
 124         .id             = 3,
 125         .dev            = {
 126                 .platform_data  = &scif3_platform_data,
 127         },
 128 };
 129
 130 static struct plat_sci_port scif4_platform_data = {
 131         .mapbase        = 0xe6c80000,
 132         .flags          = UPF_BOOT_AUTOCONF,
 133         .scscr          = SCSCR_RE | SCSCR_TE,
 134         .scbrr_algo_id  = SCBRR_ALGO_4,
 135         .type           = PORT_SCIFA,
 136         .irqs           = { gic_spi(78), gic_spi(78),
 137                             gic_spi(78), gic_spi(78) },
 138 };
 139
 140 static struct platform_device scif4_device = {
 141         .name           = "sh-sci",
 142         .id             = 4,
 143         .dev            = {
 144                 .platform_data  = &scif4_platform_data,
 145         },
 146 };
 147
 148 static struct plat_sci_port scif5_platform_data = {
 149         .mapbase        = 0xe6cb0000,
 150         .flags          = UPF_BOOT_AUTOCONF,
 151         .scscr          = SCSCR_RE | SCSCR_TE,
 152         .scbrr_algo_id  = SCBRR_ALGO_4,
 153         .type           = PORT_SCIFA,
 154         .irqs           = { gic_spi(79), gic_spi(79),
 155                             gic_spi(79), gic_spi(79) },
 156 };
 157
 158 static struct platform_device scif5_device = {
 159         .name           = "sh-sci",
 160         .id             = 5,
 161         .dev            = {
 162                 .platform_data  = &scif5_platform_data,
 163         },
 164 };
 165
 166 static struct plat_sci_port scif6_platform_data = {
 167         .mapbase        = 0xe6cc0000,
 168         .flags          = UPF_BOOT_AUTOCONF,
 169         .scscr          = SCSCR_RE | SCSCR_TE,
 170         .scbrr_algo_id  = SCBRR_ALGO_4,
 171         .type           = PORT_SCIFA,
 172         .irqs           = { gic_spi(156), gic_spi(156),
 173                             gic_spi(156), gic_spi(156) },
 174 };
 175
 176 static struct platform_device scif6_device = {
 177         .name           = "sh-sci",
 178         .id             = 6,
 179         .dev            = {
 180                 .platform_data  = &scif6_platform_data,
 181         },
 182 };
 183
 184 static struct plat_sci_port scif7_platform_data = {
 185         .mapbase        = 0xe6cd0000,
 186         .flags          = UPF_BOOT_AUTOCONF,
 187         .scscr          = SCSCR_RE | SCSCR_TE,
 188         .scbrr_algo_id  = SCBRR_ALGO_4,
 189         .type           = PORT_SCIFA,
 190         .irqs           = { gic_spi(143), gic_spi(143),
 191                             gic_spi(143), gic_spi(143) },
 192 };
 193
 194 static struct platform_device scif7_device = {
 195         .name           = "sh-sci",
 196         .id             = 7,
 197         .dev            = {
 198                 .platform_data  = &scif7_platform_data,
 199         },
 200 };
 201
 202 static struct plat_sci_port scif8_platform_data = {
 203         .mapbase        = 0xe6c30000,
 204         .flags          = UPF_BOOT_AUTOCONF,
 205         .scscr          = SCSCR_RE | SCSCR_TE,
 206         .scbrr_algo_id  = SCBRR_ALGO_4,
 207         .type           = PORT_SCIFB,
 208         .irqs           = { gic_spi(80), gic_spi(80),
 209                             gic_spi(80), gic_spi(80) },
 210 };
 211
 212 static struct platform_device scif8_device = {
 213         .name           = "sh-sci",
 214         .id             = 8,
 215         .dev            = {
 216                 .platform_data  = &scif8_platform_data,
 217         },
 218 };
 219
 220 static struct sh_timer_config cmt10_platform_data = {
 221         .name = "CMT10",
 222         .channel_offset = 0x10,
 223         .timer_bit = 0,
 224         .clockevent_rating = 125,
 225         .clocksource_rating = 125,
 226 };
 227
 228 static struct resource cmt10_resources[] = {
 229         [0] = {
 230                 .name   = "CMT10",
 231                 .start  = 0xe6138010,
 232                 .end    = 0xe613801b,
 233                 .flags  = IORESOURCE_MEM,
 234         },
 235         [1] = {
 236                 .start  = gic_spi(65),
 237                 .flags  = IORESOURCE_IRQ,
 238         },
 239 };
 240
 241 static struct platform_device cmt10_device = {
 242         .name           = "sh_cmt",
 243         .id             = 10,
 244         .dev = {
 245                 .platform_data  = &cmt10_platform_data,
 246         },
 247         .resource       = cmt10_resources,
 248         .num_resources  = ARRAY_SIZE(cmt10_resources),
 249 };
 250
 251 /* TMU */
 252 static struct sh_timer_config tmu00_platform_data = {
 253         .name = "TMU00",
 254         .channel_offset = 0x4,
 255         .timer_bit = 0,
 256         .clockevent_rating = 200,
 257 };
 258
 259 static struct resource tmu00_resources[] = {
 260         [0] = {
 261                 .name   = "TMU00",
 262                 .start  = 0xfff60008,
 263                 .end    = 0xfff60013,
 264                 .flags  = IORESOURCE_MEM,
 265         },
 266         [1] = {
 267                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
 268                 .flags  = IORESOURCE_IRQ,
 269         },
 270 };
 271
 272 static struct platform_device tmu00_device = {
 273         .name           = "sh_tmu",
 274         .id             = 0,
 275         .dev = {
 276                 .platform_data  = &tmu00_platform_data,
 277         },
 278         .resource       = tmu00_resources,
 279         .num_resources  = ARRAY_SIZE(tmu00_resources),
 280 };
 281
 282 static struct sh_timer_config tmu01_platform_data = {
 283         .name = "TMU01",
 284         .channel_offset = 0x10,
 285         .timer_bit = 1,
 286         .clocksource_rating = 200,
 287 };
 288
 289 static struct resource tmu01_resources[] = {
 290         [0] = {
 291                 .name   = "TMU01",
 292                 .start  = 0xfff60014,
 293                 .end    = 0xfff6001f,
 294                 .flags  = IORESOURCE_MEM,
 295         },
 296         [1] = {
 297                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
 298                 .flags  = IORESOURCE_IRQ,
 299         },
 300 };
 301
 302 static struct platform_device tmu01_device = {
 303         .name           = "sh_tmu",
 304         .id             = 1,
 305         .dev = {
 306                 .platform_data  = &tmu01_platform_data,
 307         },
 308         .resource       = tmu01_resources,
 309         .num_resources  = ARRAY_SIZE(tmu01_resources),
 310 };
 311
 312 static struct resource i2c0_resources[] = {
 313         [0] = {
 314                 .name   = "IIC0",
 315                 .start  = 0xe6820000,
 316                 .end    = 0xe6820425 - 1,
 317                 .flags  = IORESOURCE_MEM,
 318         },
 319         [1] = {
 320                 .start  = gic_spi(167),
 321                 .end    = gic_spi(170),
 322                 .flags  = IORESOURCE_IRQ,
 323         },
 324 };
 325
 326 static struct resource i2c1_resources[] = {
 327         [0] = {
 328                 .name   = "IIC1",
 329                 .start  = 0xe6822000,
 330                 .end    = 0xe6822425 - 1,
 331                 .flags  = IORESOURCE_MEM,
 332         },
 333         [1] = {
 334                 .start  = gic_spi(51),
 335                 .end    = gic_spi(54),
 336                 .flags  = IORESOURCE_IRQ,
 337         },
 338 };
 339
 340 static struct resource i2c2_resources[] = {
 341         [0] = {
 342                 .name   = "IIC2",
 343                 .start  = 0xe6824000,
 344                 .end    = 0xe6824425 - 1,
 345                 .flags  = IORESOURCE_MEM,
 346         },
 347         [1] = {
 348                 .start  = gic_spi(171),
 349                 .end    = gic_spi(174),
 350                 .flags  = IORESOURCE_IRQ,
 351         },
 352 };
 353
 354 static struct resource i2c3_resources[] = {
 355         [0] = {
 356                 .name   = "IIC3",
 357                 .start  = 0xe6826000,
 358                 .end    = 0xe6826425 - 1,
 359                 .flags  = IORESOURCE_MEM,
 360         },
 361         [1] = {
 362                 .start  = gic_spi(183),
 363                 .end    = gic_spi(186),
 364                 .flags  = IORESOURCE_IRQ,
 365         },
 366 };
 367
 368 static struct resource i2c4_resources[] = {
 369         [0] = {
 370                 .name   = "IIC4",
 371                 .start  = 0xe6828000,
 372                 .end    = 0xe6828425 - 1,
 373                 .flags  = IORESOURCE_MEM,
 374         },
 375         [1] = {
 376                 .start  = gic_spi(187),
 377                 .end    = gic_spi(190),
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380 };
 381
 382 static struct platform_device i2c0_device = {
 383         .name           = "i2c-sh_mobile",
 384         .id             = 0,
 385         .resource       = i2c0_resources,
 386         .num_resources  = ARRAY_SIZE(i2c0_resources),
 387 };
 388
 389 static struct platform_device i2c1_device = {
 390         .name           = "i2c-sh_mobile",
 391         .id             = 1,
 392         .resource       = i2c1_resources,
 393         .num_resources  = ARRAY_SIZE(i2c1_resources),
 394 };
 395
 396 static struct platform_device i2c2_device = {
 397         .name           = "i2c-sh_mobile",
 398         .id             = 2,
 399         .resource       = i2c2_resources,
 400         .num_resources  = ARRAY_SIZE(i2c2_resources),
 401 };
 402
 403 static struct platform_device i2c3_device = {
 404         .name           = "i2c-sh_mobile",
 405         .id             = 3,
 406         .resource       = i2c3_resources,
 407         .num_resources  = ARRAY_SIZE(i2c3_resources),
 408 };
 409
 410 static struct platform_device i2c4_device = {
 411         .name           = "i2c-sh_mobile",
 412         .id             = 4,
 413         .resource       = i2c4_resources,
 414         .num_resources  = ARRAY_SIZE(i2c4_resources),
 415 };
 416
 417 /* Transmit sizes and respective CHCR register values */
 418 enum {
 419         XMIT_SZ_8BIT            = 0,
 420         XMIT_SZ_16BIT           = 1,
 421         XMIT_SZ_32BIT           = 2,
 422         XMIT_SZ_64BIT           = 7,
 423         XMIT_SZ_128BIT          = 3,
 424         XMIT_SZ_256BIT          = 4,
 425         XMIT_SZ_512BIT          = 5,
 426 };
 427
 428 /* log2(size / 8) - used to calculate number of transfers */
 429 #define TS_SHIFT {                      \
 430         [XMIT_SZ_8BIT]          = 0,    \
 431         [XMIT_SZ_16BIT]         = 1,    \
 432         [XMIT_SZ_32BIT]         = 2,    \
 433         [XMIT_SZ_64BIT]         = 3,    \
 434         [XMIT_SZ_128BIT]        = 4,    \
 435         [XMIT_SZ_256BIT]        = 5,    \
 436         [XMIT_SZ_512BIT]        = 6,    \
 437 }
 438
 439 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
 440 #define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
 441 #define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
 442
 443 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
 444         {
 445                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 446                 .addr           = 0xe6c40020,
 447                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 448                 .mid_rid        = 0x21,
 449         }, {
 450                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 451                 .addr           = 0xe6c40024,
 452                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 453                 .mid_rid        = 0x22,
 454         }, {
 455                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 456                 .addr           = 0xe6c50020,
 457                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 458                 .mid_rid        = 0x25,
 459         }, {
 460                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 461                 .addr           = 0xe6c50024,
 462                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 463                 .mid_rid        = 0x26,
 464         }, {
 465                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 466                 .addr           = 0xe6c60020,
 467                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 468                 .mid_rid        = 0x29,
 469         }, {
 470                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 471                 .addr           = 0xe6c60024,
 472                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 473                 .mid_rid        = 0x2a,
 474         }, {
 475                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 476                 .addr           = 0xe6c70020,
 477                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 478                 .mid_rid        = 0x2d,
 479         }, {
 480                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 481                 .addr           = 0xe6c70024,
 482                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 483                 .mid_rid        = 0x2e,
 484         }, {
 485                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 486                 .addr           = 0xe6c80020,
 487                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 488                 .mid_rid        = 0x39,
 489         }, {
 490                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 491                 .addr           = 0xe6c80024,
 492                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 493                 .mid_rid        = 0x3a,
 494         }, {
 495                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 496                 .addr           = 0xe6cb0020,
 497                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 498                 .mid_rid        = 0x35,
 499         }, {
 500                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 501                 .addr           = 0xe6cb0024,
 502                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 503                 .mid_rid        = 0x36,
 504         }, {
 505                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 506                 .addr           = 0xe6cc0020,
 507                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 508                 .mid_rid        = 0x1d,
 509         }, {
 510                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 511                 .addr           = 0xe6cc0024,
 512                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 513                 .mid_rid        = 0x1e,
 514         }, {
 515                 .slave_id       = SHDMA_SLAVE_SCIF7_TX,
 516                 .addr           = 0xe6cd0020,
 517                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 518                 .mid_rid        = 0x19,
 519         }, {
 520                 .slave_id       = SHDMA_SLAVE_SCIF7_RX,
 521                 .addr           = 0xe6cd0024,
 522                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 523                 .mid_rid        = 0x1a,
 524         }, {
 525                 .slave_id       = SHDMA_SLAVE_SCIF8_TX,
 526                 .addr           = 0xe6c30040,
 527                 .chcr           = CHCR_TX(XMIT_SZ_8BIT),
 528                 .mid_rid        = 0x3d,
 529         }, {
 530                 .slave_id       = SHDMA_SLAVE_SCIF8_RX,
 531                 .addr           = 0xe6c30060,
 532                 .chcr           = CHCR_RX(XMIT_SZ_8BIT),
 533                 .mid_rid        = 0x3e,
 534         }, {
 535                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 536                 .addr           = 0xee100030,
 537                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 538                 .mid_rid        = 0xc1,
 539         }, {
 540                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 541                 .addr           = 0xee100030,
 542                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 543                 .mid_rid        = 0xc2,
 544         }, {
 545                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 546                 .addr           = 0xee120030,
 547                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 548                 .mid_rid        = 0xc9,
 549         }, {
 550                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 551                 .addr           = 0xee120030,
 552                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 553                 .mid_rid        = 0xca,
 554         }, {
 555                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 556                 .addr           = 0xee140030,
 557                 .chcr           = CHCR_TX(XMIT_SZ_16BIT),
 558                 .mid_rid        = 0xcd,
 559         }, {
 560                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 561                 .addr           = 0xee140030,
 562                 .chcr           = CHCR_RX(XMIT_SZ_16BIT),
 563                 .mid_rid        = 0xce,
 564         }, {
 565                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
 566                 .addr           = 0xe6bd0034,
 567                 .chcr           = CHCR_TX(XMIT_SZ_32BIT),
 568                 .mid_rid        = 0xd1,
 569         }, {
 570                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
 571                 .addr           = 0xe6bd0034,
 572                 .chcr           = CHCR_RX(XMIT_SZ_32BIT),
 573                 .mid_rid        = 0xd2,
 574         },
 575 };
 576
 577 #define DMAE_CHANNEL(_offset)                                   \
 578         {                                                       \
 579                 .offset         = _offset - 0x20,               \
 580                 .dmars          = _offset - 0x20 + 0x40,        \
 581         }
 582
 583 static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
 584         DMAE_CHANNEL(0x8000),
 585         DMAE_CHANNEL(0x8080),
 586         DMAE_CHANNEL(0x8100),
 587         DMAE_CHANNEL(0x8180),
 588         DMAE_CHANNEL(0x8200),
 589         DMAE_CHANNEL(0x8280),
 590         DMAE_CHANNEL(0x8300),
 591         DMAE_CHANNEL(0x8380),
 592         DMAE_CHANNEL(0x8400),
 593         DMAE_CHANNEL(0x8480),
 594         DMAE_CHANNEL(0x8500),
 595         DMAE_CHANNEL(0x8580),
 596         DMAE_CHANNEL(0x8600),
 597         DMAE_CHANNEL(0x8680),
 598         DMAE_CHANNEL(0x8700),
 599         DMAE_CHANNEL(0x8780),
 600         DMAE_CHANNEL(0x8800),
 601         DMAE_CHANNEL(0x8880),
 602         DMAE_CHANNEL(0x8900),
 603         DMAE_CHANNEL(0x8980),
 604 };
 605
 606 static const unsigned int ts_shift[] = TS_SHIFT;
 607
 608 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 609         .slave          = sh73a0_dmae_slaves,
 610         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
 611         .channel        = sh73a0_dmae_channels,
 612         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
 613         .ts_low_shift   = 3,
 614         .ts_low_mask    = 0x18,
 615         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 616         .ts_high_mask   = 0x00300000,
 617         .ts_shift       = ts_shift,
 618         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 619         .dmaor_init     = DMAOR_DME,
 620 };
 621
 622 static struct resource sh73a0_dmae_resources[] = {
 623         {
 624                 /* Registers including DMAOR and channels including DMARSx */
 625                 .start  = 0xfe000020,
 626                 .end    = 0xfe008a00 - 1,
 627                 .flags  = IORESOURCE_MEM,
 628         },
 629         {
 630                 .name   = "error_irq",
 631                 .start  = gic_spi(129),
 632                 .end    = gic_spi(129),
 633                 .flags  = IORESOURCE_IRQ,
 634         },
 635         {
 636                 /* IRQ for channels 0-19 */
 637                 .start  = gic_spi(109),
 638                 .end    = gic_spi(128),
 639                 .flags  = IORESOURCE_IRQ,
 640         },
 641 };
 642
 643 static struct platform_device dma0_device = {
 644         .name           = "sh-dma-engine",
 645         .id             = 0,
 646         .resource       = sh73a0_dmae_resources,
 647         .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
 648         .dev            = {
 649                 .platform_data  = &sh73a0_dmae_platform_data,
 650         },
 651 };
 652
 653 static struct platform_device *sh73a0_early_devices[] __initdata = {
 654         &scif0_device,
 655         &scif1_device,
 656         &scif2_device,
 657         &scif3_device,
 658         &scif4_device,
 659         &scif5_device,
 660         &scif6_device,
 661         &scif7_device,
 662         &scif8_device,
 663         &cmt10_device,
 664         &tmu00_device,
 665         &tmu01_device,
 666 };
 667
 668 static struct platform_device *sh73a0_late_devices[] __initdata = {
 669         &i2c0_device,
 670         &i2c1_device,
 671         &i2c2_device,
 672         &i2c3_device,
 673         &i2c4_device,
 674         &dma0_device,
 675 };
 676
 677 #define SRCR2          0xe61580b0
 678
 679 void __init sh73a0_add_standard_devices(void)
 680 {
 681         /* Clear software reset bit on SY-DMAC module */
 682         __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
 683
 684         platform_add_devices(sh73a0_early_devices,
 685                             ARRAY_SIZE(sh73a0_early_devices));
 686         platform_add_devices(sh73a0_late_devices,
 687                             ARRAY_SIZE(sh73a0_late_devices));
 688 }
 689
 690 static void __init sh73a0_earlytimer_init(void)
 691 {
 692         sh73a0_clock_init();
 693         shmobile_earlytimer_init();
 694 }
 695
 696 void __init sh73a0_add_early_devices(void)
 697 {
 698         early_platform_add_devices(sh73a0_early_devices,
 699                                    ARRAY_SIZE(sh73a0_early_devices));
 700
 701         /* setup early console here as well */
 702         shmobile_setup_console();
 703
 704         /* override timer setup with soc-specific code */
 705         shmobile_timer.init = sh73a0_earlytimer_init;
 706 }