2 * linux/drivers/ide/pci/alim15x3.c Version 0.16 2003/01/02
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
12 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 **********************************************************************
15 * 9/7/99 --Parts from the above author are included and need to be
16 * converted into standard interface, once I finish the thought.
19 * Don't use LBA48 mode on ALi <= 0xC4
20 * Don't poke 0x79 with a non ALi northbridge
21 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
24 * Chipset documentation available under NDA only
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/types.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/delay.h>
34 #include <linux/hdreg.h>
35 #include <linux/ide.h>
36 #include <linux/init.h>
43 * ALi devices are not plug in. Otherwise these static values would
44 * need to go. They ought to go away anyway
47 static u8 m5229_revision;
48 static u8 chip_is_1543c_e;
49 static struct pci_dev *isa_dev;
51 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
52 #include <linux/stat.h>
53 #include <linux/proc_fs.h>
55 static u8 ali_proc = 0;
57 static struct pci_dev *bmide_dev;
59 static char *fifo[4] = {
65 static char *udmaT[8] = {
76 static char *channel_status[8] = {
88 * ali_get_info - generate proc file for ALi IDE
89 * @buffer: buffer to fill
90 * @addr: address of user start in buffer
91 * @offset: offset into 'file'
92 * @count: buffer count
94 * Walks the Ali devices and outputs summary data on the tuning and
95 * anything else that will help with debugging
98 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
101 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
102 char *q, *p = buffer;
105 pci_read_config_byte(bmide_dev, 0x08, &rev);
106 if (rev >= 0xc1) /* M1543C or newer */
111 /* first fetch bibma: */
113 bibma = pci_resource_start(bmide_dev, 4);
116 * at that point bibma+0x2 et bibma+0xa are byte
117 * registers to investigate:
119 c0 = inb(bibma + 0x02);
120 c1 = inb(bibma + 0x0a);
123 "\n Ali M15x3 Chipset.\n");
125 " ------------------\n");
126 pci_read_config_byte(bmide_dev, 0x78, ®53h);
127 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
129 pci_read_config_byte(bmide_dev, 0x53, ®53h);
131 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
132 (reg53h & 0x02) ? "Yes" : "No ",
133 (reg53h & 0x01) ? "Yes" : "No " );
134 pci_read_config_byte(bmide_dev, 0x74, ®53h);
136 "FIFO Status: contains %d Words, runs%s%s\n\n",
138 (reg53h & 0x40) ? " OVERWR" : "",
139 (reg53h & 0x80) ? " OVERRD." : "." );
142 "-------------------primary channel"
143 "-------------------secondary channel"
146 pci_read_config_byte(bmide_dev, 0x09, ®53h);
150 (reg53h & 0x20) ? "On " : "Off",
151 (reg53h & 0x10) ? "On " : "Off" );
154 "both channels togth: %s"
156 (c0&0x80) ? "No " : "Yes",
157 (c1&0x80) ? "No " : "Yes" );
159 pci_read_config_byte(bmide_dev, 0x76, ®53h);
161 "Channel state: %s %s\n",
162 channel_status[reg53h & 0x07],
163 channel_status[(reg53h & 0x70) >> 4] );
165 pci_read_config_byte(bmide_dev, 0x58, ®5xh);
166 pci_read_config_byte(bmide_dev, 0x5c, ®5yh);
168 "Add. Setup Timing: %dT"
170 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
171 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
173 pci_read_config_byte(bmide_dev, 0x59, ®5xh);
174 pci_read_config_byte(bmide_dev, 0x5d, ®5yh);
176 "Command Act. Count: %dT"
178 "Command Rec. Count: %dT"
180 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
181 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
182 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
183 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
186 "----------------drive0-----------drive1"
187 "------------drive0-----------drive1------\n\n");
191 (c0&0x20) ? "Yes" : "No ",
192 (c0&0x40) ? "Yes" : "No ",
193 (c1&0x20) ? "Yes" : "No ",
194 (c1&0x40) ? "Yes" : "No " );
196 pci_read_config_byte(bmide_dev, 0x54, ®5xh);
197 pci_read_config_byte(bmide_dev, 0x55, ®5yh);
198 q = "FIFO threshold: %2d Words %2d Words"
199 " %2d Words %2d Words\n";
202 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
203 p += sprintf(p, q, 8, 8, 8, 8);
206 (reg5xh & 0x03) + 12,
207 ((reg5xh & 0x30)>>4) + 12,
208 (reg5yh & 0x03) + 12,
209 ((reg5yh & 0x30)>>4) + 12 );
212 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
213 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
214 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
215 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
216 p += sprintf(p, q, t1, t2, t3, t4);
221 "FIFO threshold: %2d Words %2d Words"
222 " %2d Words %2d Words\n",
223 (reg5xh & 0x03) + 12,
224 ((reg5xh & 0x30)>>4) + 12,
225 (reg5yh & 0x03) + 12,
226 ((reg5yh & 0x30)>>4) + 12 );
230 "FIFO mode: %s %s %s %s\n",
231 fifo[((reg5xh & 0x0c) >> 2)],
232 fifo[((reg5xh & 0xc0) >> 6)],
233 fifo[((reg5yh & 0x0c) >> 2)],
234 fifo[((reg5yh & 0xc0) >> 6)] );
236 pci_read_config_byte(bmide_dev, 0x5a, ®5xh);
237 pci_read_config_byte(bmide_dev, 0x5b, ®5xh1);
238 pci_read_config_byte(bmide_dev, 0x5e, ®5yh);
239 pci_read_config_byte(bmide_dev, 0x5f, ®5yh1);
242 "------------------drive0-----------drive1"
243 "------------drive0-----------drive1------\n")*/
244 "Dt RW act. Cnt %2dT %2dT"
246 "Dt RW rec. Cnt %2dT %2dT"
248 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
249 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
250 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
251 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
252 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
253 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
254 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
255 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
258 "-----------------------------------UDMA Timings"
259 "--------------------------------\n\n");
261 pci_read_config_byte(bmide_dev, 0x56, ®5xh);
262 pci_read_config_byte(bmide_dev, 0x57, ®5yh);
266 "UDMA timings: %s %s"
268 (reg5xh & 0x08) ? "OK" : "No",
269 (reg5xh & 0x80) ? "OK" : "No",
270 (reg5yh & 0x08) ? "OK" : "No",
271 (reg5yh & 0x80) ? "OK" : "No",
272 udmaT[(reg5xh & 0x07)],
273 udmaT[(reg5xh & 0x70) >> 4],
274 udmaT[reg5yh & 0x07],
275 udmaT[(reg5yh & 0x70) >> 4] );
277 return p-buffer; /* => must be less than 4k! */
279 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
282 * ali15x3_tune_drive - set up a drive
283 * @drive: drive to tune
286 * Select the best PIO timing for the drive in question. Then
287 * program the controller for this drive set up
290 static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio)
293 ide_hwif_t *hwif = HWIF(drive);
294 struct pci_dev *dev = hwif->pci_dev;
295 int s_time, a_time, c_time;
296 u8 s_clc, a_clc, r_clc;
298 int bus_speed = system_bus_clock();
299 int port = hwif->channel ? 0x5c : 0x58;
300 int portFIFO = hwif->channel ? 0x55 : 0x54;
302 int unit = drive->select.b.unit & 1;
304 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
305 s_time = ide_pio_timings[pio].setup_time;
306 a_time = ide_pio_timings[pio].active_time;
307 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
309 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
311 c_time = ide_pio_timings[pio].cycle_time;
314 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
318 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
324 local_irq_save(flags);
327 * PIO mode => ATA FIFO on, ATAPI FIFO off
329 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
330 if (drive->media==ide_disk) {
332 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
334 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
338 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
340 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
344 pci_write_config_byte(dev, port, s_clc);
345 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
346 local_irq_restore(flags);
350 * { 70, 165, 365 }, PIO Mode 0
351 * { 50, 125, 208 }, PIO Mode 1
352 * { 30, 100, 110 }, PIO Mode 2
353 * { 30, 80, 70 }, PIO Mode 3 with IORDY
354 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
355 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
361 * ali15x3_can_ultra - check for ultra DMA support
362 * @drive: drive to do the check
364 * Check the drive and controller revisions. Return 0 if UDMA is
365 * not available, or 1 if UDMA can be used. The actual rules for
367 * No UDMA on revisions <= 0x20
368 * Disk only for revisions < 0xC2
369 * Not WDC drives for revisions < 0xC2
371 * FIXME: WDC ifdef needs to die
374 static u8 ali15x3_can_ultra (ide_drive_t *drive)
376 #ifndef CONFIG_WDC_ALI15X3
377 struct hd_driveid *id = drive->id;
378 #endif /* CONFIG_WDC_ALI15X3 */
380 if (m5229_revision <= 0x20) {
382 } else if ((m5229_revision < 0xC2) &&
383 #ifndef CONFIG_WDC_ALI15X3
384 ((chip_is_1543c_e && strstr(id->model, "WDC ")) ||
385 (drive->media!=ide_disk))) {
386 #else /* CONFIG_WDC_ALI15X3 */
387 (drive->media!=ide_disk)) {
388 #endif /* CONFIG_WDC_ALI15X3 */
396 * ali15x3_ratemask - generate DMA mode list
397 * @drive: drive to compute against
399 * Generate a list of the available DMA modes for the drive.
400 * FIXME: this function contains lots of bogus masking we can dump
402 * Return the highest available mode (UDMA33, UDMA66, UDMA100,..)
405 static u8 ali15x3_ratemask (ide_drive_t *drive)
407 u8 mode = 0, can_ultra = ali15x3_can_ultra(drive);
409 if (m5229_revision >= 0xC4 && can_ultra) {
411 } else if (m5229_revision >= 0xC2 && can_ultra) {
413 } else if (can_ultra) {
420 * If the drive sees no suitable cable then UDMA 33
421 * is the highest permitted mode
424 if (!eighty_ninty_three(drive))
425 mode = min(mode, (u8)1);
430 * ali15x3_tune_chipset - set up chiset for new speed
431 * @drive: drive to configure for
432 * @xferspeed: desired speed
434 * Configure the hardware for the desired IDE transfer mode.
435 * We also do the needed drive configuration through helpers
438 static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
440 ide_hwif_t *hwif = HWIF(drive);
441 struct pci_dev *dev = hwif->pci_dev;
442 u8 speed = ide_rate_filter(ali15x3_ratemask(drive), xferspeed);
443 u8 unit = (drive->select.b.unit & 0x01);
445 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
447 if (speed < XFER_UDMA_0) {
448 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
450 * clear "ultra enable" bit
452 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
453 tmpbyte &= ultra_enable;
454 pci_write_config_byte(dev, m5229_udma, tmpbyte);
456 if (speed < XFER_SW_DMA_0)
457 ali15x3_tune_drive(drive, speed);
459 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
460 tmpbyte &= (0x0f << ((1-unit) << 2));
462 * enable ultra dma and set timing
464 tmpbyte |= ((0x08 | ((4-speed)&0x07)) << (unit << 2));
465 pci_write_config_byte(dev, m5229_udma, tmpbyte);
466 if (speed >= XFER_UDMA_3) {
467 pci_read_config_byte(dev, 0x4b, &tmpbyte);
469 pci_write_config_byte(dev, 0x4b, tmpbyte);
472 return (ide_config_drive_speed(drive, speed));
477 * config_chipset_for_dma - set up DMA mode
478 * @drive: drive to configure for
480 * Place a drive into DMA mode and tune the chipset for
481 * the selected speed.
483 * Returns true if DMA mode can be used
486 static int config_chipset_for_dma (ide_drive_t *drive)
488 u8 speed = ide_dma_speed(drive, ali15x3_ratemask(drive));
493 (void) ali15x3_tune_chipset(drive, speed);
494 return ide_dma_enable(drive);
498 * ali15x3_config_drive_for_dma - configure for DMA
499 * @drive: drive to configure
501 * Configure a drive for DMA operation. If DMA is not possible we
502 * drop the drive into PIO mode instead.
504 * FIXME: exactly what are we trying to return here
507 static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
509 ide_hwif_t *hwif = HWIF(drive);
510 struct hd_driveid *id = drive->id;
512 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
513 return hwif->ide_dma_off_quietly(drive);
515 drive->init_speed = 0;
517 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
518 /* Consult the list of known "bad" drives */
519 if (__ide_dma_bad_drive(drive))
521 if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
522 if (id->dma_ultra & hwif->ultra_mask) {
523 /* Force if Capable UltraDMA */
524 int dma = config_chipset_for_dma(drive);
525 if ((id->field_valid & 2) && !dma)
528 } else if (id->field_valid & 2) {
530 if ((id->dma_mword & hwif->mwdma_mask) ||
531 (id->dma_1word & hwif->swdma_mask)) {
532 /* Force if Capable regular DMA modes */
533 if (!config_chipset_for_dma(drive))
536 } else if (__ide_dma_good_drive(drive) &&
537 (id->eide_dma_time < 150)) {
538 /* Consult the list of known "good" drives */
539 if (!config_chipset_for_dma(drive))
546 hwif->tuneproc(drive, 255);
548 return hwif->ide_dma_off_quietly(drive);
550 return hwif->ide_dma_on(drive);
554 * ali15x3_dma_write - do a DMA IDE write
555 * @drive: drive to issue write for
557 * Returns 1 if the DMA write cannot be performed, zero on
561 static int ali15x3_dma_write (ide_drive_t *drive)
563 if ((m5229_revision < 0xC2) && (drive->media != ide_disk))
564 return 1; /* try PIO instead of DMA */
565 return __ide_dma_write(drive);
569 * init_chipset_ali15x3 - Initialise an ALi IDE controller
571 * @name: Name of the controller
573 * This function initializes the ALI IDE controller and where
574 * appropriate also sets up the 1533 southbridge.
577 static unsigned int __init init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
581 struct pci_dev *north = pci_find_slot(0, PCI_DEVFN(0,0));
583 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
585 isa_dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
587 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
591 ide_pci_register_host_proc(&ali_procs[0]);
593 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
595 local_irq_save(flags);
597 if (m5229_revision < 0xC2) {
599 * revision 0x20 (1543-E, 1543-F)
600 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
601 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
603 pci_read_config_byte(dev, 0x4b, &tmpbyte);
607 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
608 local_irq_restore(flags);
613 * 1543C-B?, 1535, 1535D, 1553
614 * Note 1: not all "motherboard" support this detection
615 * Note 2: if no udma 66 device, the detection may "error".
616 * but in this case, we will not set the device to
617 * ultra 66, the detection result is not important
621 * enable "Cable Detection", m5229, 0x4b, bit3
623 pci_read_config_byte(dev, 0x4b, &tmpbyte);
624 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
627 * We should only tune the 1533 enable if we are using an ALi
628 * North bridge. We might have no north found on some zany
629 * box without a device at 0:0.0. The ALi bridge will be at
630 * 0:0.0 so if we didn't find one we know what is cooking.
632 if (north && north->vendor != PCI_VENDOR_ID_AL) {
633 local_irq_restore(flags);
637 if (m5229_revision < 0xC5 && isa_dev)
640 * set south-bridge's enable bit, m1533, 0x79
643 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
644 if (m5229_revision == 0xC2) {
646 * 1543C-B0 (m1533, 0x79, bit 2)
648 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
649 } else if (m5229_revision >= 0xC3) {
651 * 1553/1535 (m1533, 0x79, bit 1)
653 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
656 local_irq_restore(flags);
661 * ata66_ali15x3 - check for UDMA 66 support
662 * @hwif: IDE interface
664 * This checks if the controller and the cable are capable
665 * of UDMA66 transfers. It doesn't check the drives.
666 * But see note 2 below!
668 * FIXME: frobs bits that are not defined on newer ALi devicea
671 static unsigned int __init ata66_ali15x3 (ide_hwif_t *hwif)
673 struct pci_dev *dev = hwif->pci_dev;
674 unsigned int ata66 = 0;
675 u8 cable_80_pin[2] = { 0, 0 };
680 local_irq_save(flags);
682 if (m5229_revision >= 0xC2) {
684 * Ultra66 cable detection (from Host View)
685 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
687 pci_read_config_byte(dev, 0x4a, &tmpbyte);
689 * 0x4a, bit0 is 0 => primary channel
690 * has 80-pin (from host view)
692 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1;
694 * 0x4a, bit1 is 0 => secondary channel
695 * has 80-pin (from host view)
697 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1;
699 * Allow ata66 if cable of current channel has 80 pins
701 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0];
704 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
706 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
707 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
711 * CD_ROM DMA on (m5229, 0x53, bit0)
712 * Enable this bit even if we want to use PIO
713 * PIO FIFO off (m5229, 0x53, bit1)
714 * The hardware will use 0x54h and 0x55h to control PIO FIFO
715 * (Not on later devices it seems)
717 * 0x53 changes meaning on later revs - we must no touch
718 * bit 1 on them. Need to check if 0x20 is the right break
721 pci_read_config_byte(dev, 0x53, &tmpbyte);
723 if(m5229_revision <= 0x20)
724 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
728 pci_write_config_byte(dev, 0x53, tmpbyte);
730 local_irq_restore(flags);
736 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
737 * @hwif: IDE interface
739 * Initialize the IDE structure side of the ALi 15x3 driver.
742 static void __init init_hwif_common_ali15x3 (ide_hwif_t *hwif)
745 hwif->tuneproc = &ali15x3_tune_drive;
746 hwif->speedproc = &ali15x3_tune_chipset;
748 /* Don't use LBA48 on ALi devices before rev 0xC5 */
749 hwif->no_lba48 = (m5229_revision <= 0xC4) ? 1 : 0;
751 if (!hwif->dma_base) {
752 hwif->drives[0].autotune = 1;
753 hwif->drives[1].autotune = 1;
759 if (m5229_revision > 0x20)
760 hwif->ultra_mask = 0x3f;
761 hwif->mwdma_mask = 0x07;
762 hwif->swdma_mask = 0x07;
764 if (m5229_revision >= 0x20) {
766 * M1543C or newer for DMAing
768 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
769 hwif->ide_dma_write = &ali15x3_dma_write;
772 if (!(hwif->udma_four))
773 hwif->udma_four = ata66_ali15x3(hwif);
775 hwif->drives[0].autodma = hwif->autodma;
776 hwif->drives[1].autodma = hwif->autodma;
780 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
781 * @hwif: interface to configure
783 * Obtain the IRQ tables for an ALi based IDE solution on the PC
784 * class platforms. This part of the code isn't applicable to the
788 static void __init init_hwif_ali15x3 (ide_hwif_t *hwif)
791 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
792 1, 11, 0, 12, 0, 14, 0, 15 };
795 hwif->irq = hwif->channel ? 15 : 14;
799 * read IDE interface control
801 pci_read_config_byte(isa_dev, 0x58, &ideic);
804 ideic = ideic & 0x03;
806 /* get IRQ for IDE Controller */
807 if ((hwif->channel && ideic == 0x03) ||
808 (!hwif->channel && !ideic)) {
810 * get SIRQ1 routing table
812 pci_read_config_byte(isa_dev, 0x44, &inmir);
813 inmir = inmir & 0x0f;
814 irq = irq_routing_table[inmir];
815 } else if (hwif->channel && !(ideic & 0x01)) {
817 * get SIRQ2 routing table
819 pci_read_config_byte(isa_dev, 0x75, &inmir);
820 inmir = inmir & 0x0f;
821 irq = irq_routing_table[inmir];
827 init_hwif_common_ali15x3(hwif);
831 * init_dma_ali15x3 - set up DMA on ALi15x3
832 * @hwif: IDE interface
833 * @dmabase: DMA interface base PCI address
835 * Set up the DMA functionality on the ALi 15x3. For the ALi
836 * controllers this is generic so we can let the generic code do
840 static void __init init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
842 if (m5229_revision < 0x20)
844 if (!(hwif->channel))
845 hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
846 ide_setup_dma(hwif, dmabase, 8);
849 extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
853 * alim15x3_init_one - set up an ALi15x3 IDE controller
854 * @dev: PCI device to set up
856 * Perform the actual set up for an ALi15x3 that has been found by the
860 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
862 ide_pci_device_t *d = &ali15x3_chipsets[id->driver_data];
864 if(pci_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, NULL))
865 printk(KERN_ERR "Warning: ATI Radeon IGP Northbridge is not yet fully tested.\n");
867 #if defined(CONFIG_SPARC64)
868 d->init_hwif = init_hwif_common_ali15x3;
869 #endif /* CONFIG_SPARC64 */
870 ide_setup_pci_device(dev, d);
875 static struct pci_device_id alim15x3_pci_tbl[] = {
876 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
880 static struct pci_driver driver = {
881 .name = "ALI15x3 IDE",
882 .id_table = alim15x3_pci_tbl,
883 .probe = alim15x3_init_one,
886 static int ali15x3_ide_init(void)
888 return ide_pci_register_driver(&driver);
891 module_init(ali15x3_ide_init);
893 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
894 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
895 MODULE_LICENSE("GPL");