drivers/usb/gadget/mv_udc_core.c

   1 /*
   2  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   3  * Author: Chao Xie <chao.xie@marvell.com>
   4  *         Neil Zhang <zhangwm@marvell.com>
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/kernel.h>
  17 #include <linux/delay.h>
  18 #include <linux/ioport.h>
  19 #include <linux/sched.h>
  20 #include <linux/slab.h>
  21 #include <linux/errno.h>
  22 #include <linux/init.h>
  23 #include <linux/timer.h>
  24 #include <linux/list.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/device.h>
  28 #include <linux/usb/ch9.h>
  29 #include <linux/usb/gadget.h>
  30 #include <linux/usb/otg.h>
  31 #include <linux/pm.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36 #include <linux/platform_data/mv_usb.h>
  37 #include <asm/system.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "mv_udc.h"
  41
  42 #define DRIVER_DESC             "Marvell PXA USB Device Controller driver"
  43 #define DRIVER_VERSION          "8 Nov 2010"
  44
  45 #define ep_dir(ep)      (((ep)->ep_num == 0) ? \
  46                                 ((ep)->udc->ep0_dir) : ((ep)->direction))
  47
  48 /* timeout value -- usec */
  49 #define RESET_TIMEOUT           10000
  50 #define FLUSH_TIMEOUT           10000
  51 #define EPSTATUS_TIMEOUT        10000
  52 #define PRIME_TIMEOUT           10000
  53 #define READSAFE_TIMEOUT        1000
  54 #define DTD_TIMEOUT             1000
  55
  56 #define LOOPS_USEC_SHIFT        4
  57 #define LOOPS_USEC              (1 << LOOPS_USEC_SHIFT)
  58 #define LOOPS(timeout)          ((timeout) >> LOOPS_USEC_SHIFT)
  59
  60 static DECLARE_COMPLETION(release_done);
  61
  62 static const char driver_name[] = "mv_udc";
  63 static const char driver_desc[] = DRIVER_DESC;
  64
  65 /* controller device global variable */
  66 static struct mv_udc    *the_controller;
  67 int mv_usb_otgsc;
  68
  69 static void nuke(struct mv_ep *ep, int status);
  70 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver);
  71
  72 /* for endpoint 0 operations */
  73 static const struct usb_endpoint_descriptor mv_ep0_desc = {
  74         .bLength =              USB_DT_ENDPOINT_SIZE,
  75         .bDescriptorType =      USB_DT_ENDPOINT,
  76         .bEndpointAddress =     0,
  77         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  78         .wMaxPacketSize =       EP0_MAX_PKT_SIZE,
  79 };
  80
  81 static void ep0_reset(struct mv_udc *udc)
  82 {
  83         struct mv_ep *ep;
  84         u32 epctrlx;
  85         int i = 0;
  86
  87         /* ep0 in and out */
  88         for (i = 0; i < 2; i++) {
  89                 ep = &udc->eps[i];
  90                 ep->udc = udc;
  91
  92                 /* ep0 dQH */
  93                 ep->dqh = &udc->ep_dqh[i];
  94
  95                 /* configure ep0 endpoint capabilities in dQH */
  96                 ep->dqh->max_packet_length =
  97                         (EP0_MAX_PKT_SIZE << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
  98                         | EP_QUEUE_HEAD_IOS;
  99
 100                 ep->dqh->next_dtd_ptr = EP_QUEUE_HEAD_NEXT_TERMINATE;
 101
 102                 epctrlx = readl(&udc->op_regs->epctrlx[0]);
 103                 if (i) {        /* TX */
 104                         epctrlx |= EPCTRL_TX_ENABLE
 105                                 | (USB_ENDPOINT_XFER_CONTROL
 106                                         << EPCTRL_TX_EP_TYPE_SHIFT);
 107
 108                 } else {        /* RX */
 109                         epctrlx |= EPCTRL_RX_ENABLE
 110                                 | (USB_ENDPOINT_XFER_CONTROL
 111                                         << EPCTRL_RX_EP_TYPE_SHIFT);
 112                 }
 113
 114                 writel(epctrlx, &udc->op_regs->epctrlx[0]);
 115         }
 116 }
 117
 118 /* protocol ep0 stall, will automatically be cleared on new transaction */
 119 static void ep0_stall(struct mv_udc *udc)
 120 {
 121         u32     epctrlx;
 122
 123         /* set TX and RX to stall */
 124         epctrlx = readl(&udc->op_regs->epctrlx[0]);
 125         epctrlx |= EPCTRL_RX_EP_STALL | EPCTRL_TX_EP_STALL;
 126         writel(epctrlx, &udc->op_regs->epctrlx[0]);
 127
 128         /* update ep0 state */
 129         udc->ep0_state = WAIT_FOR_SETUP;
 130         udc->ep0_dir = EP_DIR_OUT;
 131 }
 132
 133 static int process_ep_req(struct mv_udc *udc, int index,
 134         struct mv_req *curr_req)
 135 {
 136         struct mv_dtd   *curr_dtd;
 137         struct mv_dqh   *curr_dqh;
 138         int td_complete, actual, remaining_length;
 139         int i, direction;
 140         int retval = 0;
 141         u32 errors;
 142         u32 bit_pos;
 143
 144         curr_dqh = &udc->ep_dqh[index];
 145         direction = index % 2;
 146
 147         curr_dtd = curr_req->head;
 148         td_complete = 0;
 149         actual = curr_req->req.length;
 150
 151         for (i = 0; i < curr_req->dtd_count; i++) {
 152                 if (curr_dtd->size_ioc_sts & DTD_STATUS_ACTIVE) {
 153                         dev_dbg(&udc->dev->dev, "%s, dTD not completed\n",
 154                                 udc->eps[index].name);
 155                         return 1;
 156                 }
 157
 158                 errors = curr_dtd->size_ioc_sts & DTD_ERROR_MASK;
 159                 if (!errors) {
 160                         remaining_length =
 161                                 (curr_dtd->size_ioc_sts & DTD_PACKET_SIZE)
 162                                         >> DTD_LENGTH_BIT_POS;
 163                         actual -= remaining_length;
 164
 165                         if (remaining_length) {
 166                                 if (direction) {
 167                                         dev_dbg(&udc->dev->dev,
 168                                                 "TX dTD remains data\n");
 169                                         retval = -EPROTO;
 170                                         break;
 171                                 } else
 172                                         break;
 173                         }
 174                 } else {
 175                         dev_info(&udc->dev->dev,
 176                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 177                                 index >> 1, direction ? "SEND" : "RECV",
 178                                 errors);
 179                         if (errors & DTD_STATUS_HALTED) {
 180                                 /* Clear the errors and Halt condition */
 181                                 curr_dqh->size_ioc_int_sts &= ~errors;
 182                                 retval = -EPIPE;
 183                         } else if (errors & DTD_STATUS_DATA_BUFF_ERR) {
 184                                 retval = -EPROTO;
 185                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
 186                                 retval = -EILSEQ;
 187                         }
 188                 }
 189                 if (i != curr_req->dtd_count - 1)
 190                         curr_dtd = (struct mv_dtd *)curr_dtd->next_dtd_virt;
 191         }
 192         if (retval)
 193                 return retval;
 194
 195         if (direction == EP_DIR_OUT)
 196                 bit_pos = 1 << curr_req->ep->ep_num;
 197         else
 198                 bit_pos = 1 << (16 + curr_req->ep->ep_num);
 199
 200         while ((curr_dqh->curr_dtd_ptr == curr_dtd->td_dma)) {
 201                 if (curr_dtd->dtd_next == EP_QUEUE_HEAD_NEXT_TERMINATE) {
 202                         while (readl(&udc->op_regs->epstatus) & bit_pos)
 203                                 udelay(1);
 204                         break;
 205                 }
 206                 udelay(1);
 207         }
 208
 209         curr_req->req.actual = actual;
 210
 211         return 0;
 212 }
 213
 214 /*
 215  * done() - retire a request; caller blocked irqs
 216  * @status : request status to be set, only works when
 217  * request is still in progress.
 218  */
 219 static void done(struct mv_ep *ep, struct mv_req *req, int status)
 220 {
 221         struct mv_udc *udc = NULL;
 222         unsigned char stopped = ep->stopped;
 223         struct mv_dtd *curr_td, *next_td;
 224         int j;
 225
 226         udc = (struct mv_udc *)ep->udc;
 227         /* Removed the req from fsl_ep->queue */
 228         list_del_init(&req->queue);
 229
 230         /* req.status should be set as -EINPROGRESS in ep_queue() */
 231         if (req->req.status == -EINPROGRESS)
 232                 req->req.status = status;
 233         else
 234                 status = req->req.status;
 235
 236         /* Free dtd for the request */
 237         next_td = req->head;
 238         for (j = 0; j < req->dtd_count; j++) {
 239                 curr_td = next_td;
 240                 if (j != req->dtd_count - 1)
 241                         next_td = curr_td->next_dtd_virt;
 242                 dma_pool_free(udc->dtd_pool, curr_td, curr_td->td_dma);
 243         }
 244
 245         if (req->mapped) {
 246                 dma_unmap_single(ep->udc->gadget.dev.parent,
 247                         req->req.dma, req->req.length,
 248                         ((ep_dir(ep) == EP_DIR_IN) ?
 249                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 250                 req->req.dma = DMA_ADDR_INVALID;
 251                 req->mapped = 0;
 252         } else
 253                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 254                         req->req.dma, req->req.length,
 255                         ((ep_dir(ep) == EP_DIR_IN) ?
 256                                 DMA_TO_DEVICE : DMA_FROM_DEVICE));
 257
 258         if (status && (status != -ESHUTDOWN))
 259                 dev_info(&udc->dev->dev, "complete %s req %p stat %d len %u/%u",
 260                         ep->ep.name, &req->req, status,
 261                         req->req.actual, req->req.length);
 262
 263         ep->stopped = 1;
 264
 265         spin_unlock(&ep->udc->lock);
 266         /*
 267          * complete() is from gadget layer,
 268          * eg fsg->bulk_in_complete()
 269          */
 270         if (req->req.complete)
 271                 req->req.complete(&ep->ep, &req->req);
 272
 273         spin_lock(&ep->udc->lock);
 274         ep->stopped = stopped;
 275 }
 276
 277 static int queue_dtd(struct mv_ep *ep, struct mv_req *req)
 278 {
 279         struct mv_udc *udc;
 280         struct mv_dqh *dqh;
 281         u32 bit_pos, direction;
 282         u32 usbcmd, epstatus;
 283         unsigned int loops;
 284         int retval = 0;
 285
 286         udc = ep->udc;
 287         direction = ep_dir(ep);
 288         dqh = &(udc->ep_dqh[ep->ep_num * 2 + direction]);
 289         bit_pos = 1 << (((direction == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 290
 291         /* check if the pipe is empty */
 292         if (!(list_empty(&ep->queue))) {
 293                 struct mv_req *lastreq;
 294                 lastreq = list_entry(ep->queue.prev, struct mv_req, queue);
 295                 lastreq->tail->dtd_next =
 296                         req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 297
 298                 wmb();
 299
 300                 if (readl(&udc->op_regs->epprime) & bit_pos)
 301                         goto done;
 302
 303                 loops = LOOPS(READSAFE_TIMEOUT);
 304                 while (1) {
 305                         /* start with setting the semaphores */
 306                         usbcmd = readl(&udc->op_regs->usbcmd);
 307                         usbcmd |= USBCMD_ATDTW_TRIPWIRE_SET;
 308                         writel(usbcmd, &udc->op_regs->usbcmd);
 309
 310                         /* read the endpoint status */
 311                         epstatus = readl(&udc->op_regs->epstatus) & bit_pos;
 312
 313                         /*
 314                          * Reread the ATDTW semaphore bit to check if it is
 315                          * cleared. When hardware see a hazard, it will clear
 316                          * the bit or else we remain set to 1 and we can
 317                          * proceed with priming of endpoint if not already
 318                          * primed.
 319                          */
 320                         if (readl(&udc->op_regs->usbcmd)
 321                                 & USBCMD_ATDTW_TRIPWIRE_SET)
 322                                 break;
 323
 324                         loops--;
 325                         if (loops == 0) {
 326                                 dev_err(&udc->dev->dev,
 327                                         "Timeout for ATDTW_TRIPWIRE...\n");
 328                                 retval = -ETIME;
 329                                 goto done;
 330                         }
 331                         udelay(LOOPS_USEC);
 332                 }
 333
 334                 /* Clear the semaphore */
 335                 usbcmd = readl(&udc->op_regs->usbcmd);
 336                 usbcmd &= USBCMD_ATDTW_TRIPWIRE_CLEAR;
 337                 writel(usbcmd, &udc->op_regs->usbcmd);
 338
 339                 if (epstatus)
 340                         goto done;
 341         }
 342
 343         /* Write dQH next pointer and terminate bit to 0 */
 344         dqh->next_dtd_ptr = req->head->td_dma
 345                                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 346
 347         /* clear active and halt bit, in case set from a previous error */
 348         dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
 349
 350         /* Ensure that updates to the QH will occure before priming. */
 351         wmb();
 352
 353         /* Prime the Endpoint */
 354         writel(bit_pos, &udc->op_regs->epprime);
 355
 356 done:
 357         return retval;
 358 }
 359
 360
 361 static struct mv_dtd *build_dtd(struct mv_req *req, unsigned *length,
 362                 dma_addr_t *dma, int *is_last)
 363 {
 364         u32 temp;
 365         struct mv_dtd *dtd;
 366         struct mv_udc *udc;
 367
 368         /* how big will this transfer be? */
 369         *length = min(req->req.length - req->req.actual,
 370                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 371
 372         udc = req->ep->udc;
 373
 374         /*
 375          * Be careful that no _GFP_HIGHMEM is set,
 376          * or we can not use dma_to_virt
 377          */
 378         dtd = dma_pool_alloc(udc->dtd_pool, GFP_KERNEL, dma);
 379         if (dtd == NULL)
 380                 return dtd;
 381
 382         dtd->td_dma = *dma;
 383         /* initialize buffer page pointers */
 384         temp = (u32)(req->req.dma + req->req.actual);
 385         dtd->buff_ptr0 = cpu_to_le32(temp);
 386         temp &= ~0xFFF;
 387         dtd->buff_ptr1 = cpu_to_le32(temp + 0x1000);
 388         dtd->buff_ptr2 = cpu_to_le32(temp + 0x2000);
 389         dtd->buff_ptr3 = cpu_to_le32(temp + 0x3000);
 390         dtd->buff_ptr4 = cpu_to_le32(temp + 0x4000);
 391
 392         req->req.actual += *length;
 393
 394         /* zlp is needed if req->req.zero is set */
 395         if (req->req.zero) {
 396                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 397                         *is_last = 1;
 398                 else
 399                         *is_last = 0;
 400         } else if (req->req.length == req->req.actual)
 401                 *is_last = 1;
 402         else
 403                 *is_last = 0;
 404
 405         /* Fill in the transfer size; set active bit */
 406         temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 407
 408         /* Enable interrupt for the last dtd of a request */
 409         if (*is_last && !req->req.no_interrupt)
 410                 temp |= DTD_IOC;
 411
 412         dtd->size_ioc_sts = temp;
 413
 414         mb();
 415
 416         return dtd;
 417 }
 418
 419 /* generate dTD linked list for a request */
 420 static int req_to_dtd(struct mv_req *req)
 421 {
 422         unsigned count;
 423         int is_last, is_first = 1;
 424         struct mv_dtd *dtd, *last_dtd = NULL;
 425         struct mv_udc *udc;
 426         dma_addr_t dma;
 427
 428         udc = req->ep->udc;
 429
 430         do {
 431                 dtd = build_dtd(req, &count, &dma, &is_last);
 432                 if (dtd == NULL)
 433                         return -ENOMEM;
 434
 435                 if (is_first) {
 436                         is_first = 0;
 437                         req->head = dtd;
 438                 } else {
 439                         last_dtd->dtd_next = dma;
 440                         last_dtd->next_dtd_virt = dtd;
 441                 }
 442                 last_dtd = dtd;
 443                 req->dtd_count++;
 444         } while (!is_last);
 445
 446         /* set terminate bit to 1 for the last dTD */
 447         dtd->dtd_next = DTD_NEXT_TERMINATE;
 448
 449         req->tail = dtd;
 450
 451         return 0;
 452 }
 453
 454 static int mv_ep_enable(struct usb_ep *_ep,
 455                 const struct usb_endpoint_descriptor *desc)
 456 {
 457         struct mv_udc *udc;
 458         struct mv_ep *ep;
 459         struct mv_dqh *dqh;
 460         u16 max = 0;
 461         u32 bit_pos, epctrlx, direction;
 462         unsigned char zlt = 0, ios = 0, mult = 0;
 463         unsigned long flags;
 464
 465         ep = container_of(_ep, struct mv_ep, ep);
 466         udc = ep->udc;
 467
 468         if (!_ep || !desc || ep->desc
 469                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 470                 return -EINVAL;
 471
 472         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 473                 return -ESHUTDOWN;
 474
 475         direction = ep_dir(ep);
 476         max = usb_endpoint_maxp(desc);
 477
 478         /*
 479          * disable HW zero length termination select
 480          * driver handles zero length packet through req->req.zero
 481          */
 482         zlt = 1;
 483
 484         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 485
 486         /* Check if the Endpoint is Primed */
 487         if ((readl(&udc->op_regs->epprime) & bit_pos)
 488                 || (readl(&udc->op_regs->epstatus) & bit_pos)) {
 489                 dev_info(&udc->dev->dev,
 490                         "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
 491                         " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 492                         (unsigned)ep->ep_num, direction ? "SEND" : "RECV",
 493                         (unsigned)readl(&udc->op_regs->epprime),
 494                         (unsigned)readl(&udc->op_regs->epstatus),
 495                         (unsigned)bit_pos);
 496                 goto en_done;
 497         }
 498         /* Set the max packet length, interrupt on Setup and Mult fields */
 499         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 500         case USB_ENDPOINT_XFER_BULK:
 501                 zlt = 1;
 502                 mult = 0;
 503                 break;
 504         case USB_ENDPOINT_XFER_CONTROL:
 505                 ios = 1;
 506         case USB_ENDPOINT_XFER_INT:
 507                 mult = 0;
 508                 break;
 509         case USB_ENDPOINT_XFER_ISOC:
 510                 /* Calculate transactions needed for high bandwidth iso */
 511                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 512                 max = max & 0x7ff;      /* bit 0~10 */
 513                 /* 3 transactions at most */
 514                 if (mult > 3)
 515                         goto en_done;
 516                 break;
 517         default:
 518                 goto en_done;
 519         }
 520
 521         spin_lock_irqsave(&udc->lock, flags);
 522         /* Get the endpoint queue head address */
 523         dqh = ep->dqh;
 524         dqh->max_packet_length = (max << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 525                 | (mult << EP_QUEUE_HEAD_MULT_POS)
 526                 | (zlt ? EP_QUEUE_HEAD_ZLT_SEL : 0)
 527                 | (ios ? EP_QUEUE_HEAD_IOS : 0);
 528         dqh->next_dtd_ptr = 1;
 529         dqh->size_ioc_int_sts = 0;
 530
 531         ep->ep.maxpacket = max;
 532         ep->desc = desc;
 533         ep->stopped = 0;
 534
 535         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 536         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 537         if (direction == EP_DIR_IN) {
 538                 epctrlx &= ~EPCTRL_TX_ALL_MASK;
 539                 epctrlx |= EPCTRL_TX_ENABLE | EPCTRL_TX_DATA_TOGGLE_RST
 540                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 541                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 542         } else {
 543                 epctrlx &= ~EPCTRL_RX_ALL_MASK;
 544                 epctrlx |= EPCTRL_RX_ENABLE | EPCTRL_RX_DATA_TOGGLE_RST
 545                         | ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
 546                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 547         }
 548         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 549
 550         /*
 551          * Implement Guideline (GL# USB-7) The unused endpoint type must
 552          * be programmed to bulk.
 553          */
 554         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 555         if ((epctrlx & EPCTRL_RX_ENABLE) == 0) {
 556                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 557                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 558                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 559         }
 560
 561         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 562         if ((epctrlx & EPCTRL_TX_ENABLE) == 0) {
 563                 epctrlx |= (USB_ENDPOINT_XFER_BULK
 564                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 565                 writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 566         }
 567
 568         spin_unlock_irqrestore(&udc->lock, flags);
 569
 570         return 0;
 571 en_done:
 572         return -EINVAL;
 573 }
 574
 575 static int  mv_ep_disable(struct usb_ep *_ep)
 576 {
 577         struct mv_udc *udc;
 578         struct mv_ep *ep;
 579         struct mv_dqh *dqh;
 580         u32 bit_pos, epctrlx, direction;
 581         unsigned long flags;
 582
 583         ep = container_of(_ep, struct mv_ep, ep);
 584         if ((_ep == NULL) || !ep->desc)
 585                 return -EINVAL;
 586
 587         udc = ep->udc;
 588
 589         /* Get the endpoint queue head address */
 590         dqh = ep->dqh;
 591
 592         spin_lock_irqsave(&udc->lock, flags);
 593
 594         direction = ep_dir(ep);
 595         bit_pos = 1 << ((direction == EP_DIR_OUT ? 0 : 16) + ep->ep_num);
 596
 597         /* Reset the max packet length and the interrupt on Setup */
 598         dqh->max_packet_length = 0;
 599
 600         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 601         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 602         epctrlx &= ~((direction == EP_DIR_IN)
 603                         ? (EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE)
 604                         : (EPCTRL_RX_ENABLE | EPCTRL_RX_TYPE));
 605         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 606
 607         /* nuke all pending requests (does flush) */
 608         nuke(ep, -ESHUTDOWN);
 609
 610         ep->desc = NULL;
 611         ep->ep.desc = NULL;
 612         ep->stopped = 1;
 613
 614         spin_unlock_irqrestore(&udc->lock, flags);
 615
 616         return 0;
 617 }
 618
 619 static struct usb_request *
 620 mv_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 621 {
 622         struct mv_req *req = NULL;
 623
 624         req = kzalloc(sizeof *req, gfp_flags);
 625         if (!req)
 626                 return NULL;
 627
 628         req->req.dma = DMA_ADDR_INVALID;
 629         INIT_LIST_HEAD(&req->queue);
 630
 631         return &req->req;
 632 }
 633
 634 static void mv_free_request(struct usb_ep *_ep, struct usb_request *_req)
 635 {
 636         struct mv_req *req = NULL;
 637
 638         req = container_of(_req, struct mv_req, req);
 639
 640         if (_req)
 641                 kfree(req);
 642 }
 643
 644 static void mv_ep_fifo_flush(struct usb_ep *_ep)
 645 {
 646         struct mv_udc *udc;
 647         u32 bit_pos, direction;
 648         struct mv_ep *ep;
 649         unsigned int loops;
 650
 651         if (!_ep)
 652                 return;
 653
 654         ep = container_of(_ep, struct mv_ep, ep);
 655         if (!ep->desc)
 656                 return;
 657
 658         udc = ep->udc;
 659         direction = ep_dir(ep);
 660
 661         if (ep->ep_num == 0)
 662                 bit_pos = (1 << 16) | 1;
 663         else if (direction == EP_DIR_OUT)
 664                 bit_pos = 1 << ep->ep_num;
 665         else
 666                 bit_pos = 1 << (16 + ep->ep_num);
 667
 668         loops = LOOPS(EPSTATUS_TIMEOUT);
 669         do {
 670                 unsigned int inter_loops;
 671
 672                 if (loops == 0) {
 673                         dev_err(&udc->dev->dev,
 674                                 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
 675                                 (unsigned)readl(&udc->op_regs->epstatus),
 676                                 (unsigned)bit_pos);
 677                         return;
 678                 }
 679                 /* Write 1 to the Flush register */
 680                 writel(bit_pos, &udc->op_regs->epflush);
 681
 682                 /* Wait until flushing completed */
 683                 inter_loops = LOOPS(FLUSH_TIMEOUT);
 684                 while (readl(&udc->op_regs->epflush)) {
 685                         /*
 686                          * ENDPTFLUSH bit should be cleared to indicate this
 687                          * operation is complete
 688                          */
 689                         if (inter_loops == 0) {
 690                                 dev_err(&udc->dev->dev,
 691                                         "TIMEOUT for ENDPTFLUSH=0x%x,"
 692                                         "bit_pos=0x%x\n",
 693                                         (unsigned)readl(&udc->op_regs->epflush),
 694                                         (unsigned)bit_pos);
 695                                 return;
 696                         }
 697                         inter_loops--;
 698                         udelay(LOOPS_USEC);
 699                 }
 700                 loops--;
 701         } while (readl(&udc->op_regs->epstatus) & bit_pos);
 702 }
 703
 704 /* queues (submits) an I/O request to an endpoint */
 705 static int
 706 mv_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 707 {
 708         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 709         struct mv_req *req = container_of(_req, struct mv_req, req);
 710         struct mv_udc *udc = ep->udc;
 711         unsigned long flags;
 712
 713         /* catch various bogus parameters */
 714         if (!_req || !req->req.complete || !req->req.buf
 715                         || !list_empty(&req->queue)) {
 716                 dev_err(&udc->dev->dev, "%s, bad params", __func__);
 717                 return -EINVAL;
 718         }
 719         if (unlikely(!_ep || !ep->desc)) {
 720                 dev_err(&udc->dev->dev, "%s, bad ep", __func__);
 721                 return -EINVAL;
 722         }
 723         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 724                 if (req->req.length > ep->ep.maxpacket)
 725                         return -EMSGSIZE;
 726         }
 727
 728         udc = ep->udc;
 729         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 730                 return -ESHUTDOWN;
 731
 732         req->ep = ep;
 733
 734         /* map virtual address to hardware */
 735         if (req->req.dma == DMA_ADDR_INVALID) {
 736                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 737                                         req->req.buf,
 738                                         req->req.length, ep_dir(ep)
 739                                                 ? DMA_TO_DEVICE
 740                                                 : DMA_FROM_DEVICE);
 741                 req->mapped = 1;
 742         } else {
 743                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 744                                         req->req.dma, req->req.length,
 745                                         ep_dir(ep)
 746                                                 ? DMA_TO_DEVICE
 747                                                 : DMA_FROM_DEVICE);
 748                 req->mapped = 0;
 749         }
 750
 751         req->req.status = -EINPROGRESS;
 752         req->req.actual = 0;
 753         req->dtd_count = 0;
 754
 755         spin_lock_irqsave(&udc->lock, flags);
 756
 757         /* build dtds and push them to device queue */
 758         if (!req_to_dtd(req)) {
 759                 int retval;
 760                 retval = queue_dtd(ep, req);
 761                 if (retval) {
 762                         spin_unlock_irqrestore(&udc->lock, flags);
 763                         return retval;
 764                 }
 765         } else {
 766                 spin_unlock_irqrestore(&udc->lock, flags);
 767                 return -ENOMEM;
 768         }
 769
 770         /* Update ep0 state */
 771         if (ep->ep_num == 0)
 772                 udc->ep0_state = DATA_STATE_XMIT;
 773
 774         /* irq handler advances the queue */
 775         list_add_tail(&req->queue, &ep->queue);
 776         spin_unlock_irqrestore(&udc->lock, flags);
 777
 778         return 0;
 779 }
 780
 781 static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req)
 782 {
 783         struct mv_dqh *dqh = ep->dqh;
 784         u32 bit_pos;
 785
 786         /* Write dQH next pointer and terminate bit to 0 */
 787         dqh->next_dtd_ptr = req->head->td_dma
 788                 & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
 789
 790         /* clear active and halt bit, in case set from a previous error */
 791         dqh->size_ioc_int_sts &= ~(DTD_STATUS_ACTIVE | DTD_STATUS_HALTED);
 792
 793         /* Ensure that updates to the QH will occure before priming. */
 794         wmb();
 795
 796         bit_pos = 1 << (((ep_dir(ep) == EP_DIR_OUT) ? 0 : 16) + ep->ep_num);
 797
 798         /* Prime the Endpoint */
 799         writel(bit_pos, &ep->udc->op_regs->epprime);
 800 }
 801
 802 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 803 static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 804 {
 805         struct mv_ep *ep = container_of(_ep, struct mv_ep, ep);
 806         struct mv_req *req;
 807         struct mv_udc *udc = ep->udc;
 808         unsigned long flags;
 809         int stopped, ret = 0;
 810         u32 epctrlx;
 811
 812         if (!_ep || !_req)
 813                 return -EINVAL;
 814
 815         spin_lock_irqsave(&ep->udc->lock, flags);
 816         stopped = ep->stopped;
 817
 818         /* Stop the ep before we deal with the queue */
 819         ep->stopped = 1;
 820         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 821         if (ep_dir(ep) == EP_DIR_IN)
 822                 epctrlx &= ~EPCTRL_TX_ENABLE;
 823         else
 824                 epctrlx &= ~EPCTRL_RX_ENABLE;
 825         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 826
 827         /* make sure it's actually queued on this endpoint */
 828         list_for_each_entry(req, &ep->queue, queue) {
 829                 if (&req->req == _req)
 830                         break;
 831         }
 832         if (&req->req != _req) {
 833                 ret = -EINVAL;
 834                 goto out;
 835         }
 836
 837         /* The request is in progress, or completed but not dequeued */
 838         if (ep->queue.next == &req->queue) {
 839                 _req->status = -ECONNRESET;
 840                 mv_ep_fifo_flush(_ep);  /* flush current transfer */
 841
 842                 /* The request isn't the last request in this ep queue */
 843                 if (req->queue.next != &ep->queue) {
 844                         struct mv_req *next_req;
 845
 846                         next_req = list_entry(req->queue.next,
 847                                 struct mv_req, queue);
 848
 849                         /* Point the QH to the first TD of next request */
 850                         mv_prime_ep(ep, next_req);
 851                 } else {
 852                         struct mv_dqh *qh;
 853
 854                         qh = ep->dqh;
 855                         qh->next_dtd_ptr = 1;
 856                         qh->size_ioc_int_sts = 0;
 857                 }
 858
 859                 /* The request hasn't been processed, patch up the TD chain */
 860         } else {
 861                 struct mv_req *prev_req;
 862
 863                 prev_req = list_entry(req->queue.prev, struct mv_req, queue);
 864                 writel(readl(&req->tail->dtd_next),
 865                                 &prev_req->tail->dtd_next);
 866
 867         }
 868
 869         done(ep, req, -ECONNRESET);
 870
 871         /* Enable EP */
 872 out:
 873         epctrlx = readl(&udc->op_regs->epctrlx[ep->ep_num]);
 874         if (ep_dir(ep) == EP_DIR_IN)
 875                 epctrlx |= EPCTRL_TX_ENABLE;
 876         else
 877                 epctrlx |= EPCTRL_RX_ENABLE;
 878         writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]);
 879         ep->stopped = stopped;
 880
 881         spin_unlock_irqrestore(&ep->udc->lock, flags);
 882         return ret;
 883 }
 884
 885 static void ep_set_stall(struct mv_udc *udc, u8 ep_num, u8 direction, int stall)
 886 {
 887         u32 epctrlx;
 888
 889         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 890
 891         if (stall) {
 892                 if (direction == EP_DIR_IN)
 893                         epctrlx |= EPCTRL_TX_EP_STALL;
 894                 else
 895                         epctrlx |= EPCTRL_RX_EP_STALL;
 896         } else {
 897                 if (direction == EP_DIR_IN) {
 898                         epctrlx &= ~EPCTRL_TX_EP_STALL;
 899                         epctrlx |= EPCTRL_TX_DATA_TOGGLE_RST;
 900                 } else {
 901                         epctrlx &= ~EPCTRL_RX_EP_STALL;
 902                         epctrlx |= EPCTRL_RX_DATA_TOGGLE_RST;
 903                 }
 904         }
 905         writel(epctrlx, &udc->op_regs->epctrlx[ep_num]);
 906 }
 907
 908 static int ep_is_stall(struct mv_udc *udc, u8 ep_num, u8 direction)
 909 {
 910         u32 epctrlx;
 911
 912         epctrlx = readl(&udc->op_regs->epctrlx[ep_num]);
 913
 914         if (direction == EP_DIR_OUT)
 915                 return (epctrlx & EPCTRL_RX_EP_STALL) ? 1 : 0;
 916         else
 917                 return (epctrlx & EPCTRL_TX_EP_STALL) ? 1 : 0;
 918 }
 919
 920 static int mv_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 921 {
 922         struct mv_ep *ep;
 923         unsigned long flags = 0;
 924         int status = 0;
 925         struct mv_udc *udc;
 926
 927         ep = container_of(_ep, struct mv_ep, ep);
 928         udc = ep->udc;
 929         if (!_ep || !ep->desc) {
 930                 status = -EINVAL;
 931                 goto out;
 932         }
 933
 934         if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 935                 status = -EOPNOTSUPP;
 936                 goto out;
 937         }
 938
 939         /*
 940          * Attempt to halt IN ep will fail if any transfer requests
 941          * are still queue
 942          */
 943         if (halt && (ep_dir(ep) == EP_DIR_IN) && !list_empty(&ep->queue)) {
 944                 status = -EAGAIN;
 945                 goto out;
 946         }
 947
 948         spin_lock_irqsave(&ep->udc->lock, flags);
 949         ep_set_stall(udc, ep->ep_num, ep_dir(ep), halt);
 950         if (halt && wedge)
 951                 ep->wedge = 1;
 952         else if (!halt)
 953                 ep->wedge = 0;
 954         spin_unlock_irqrestore(&ep->udc->lock, flags);
 955
 956         if (ep->ep_num == 0) {
 957                 udc->ep0_state = WAIT_FOR_SETUP;
 958                 udc->ep0_dir = EP_DIR_OUT;
 959         }
 960 out:
 961         return status;
 962 }
 963
 964 static int mv_ep_set_halt(struct usb_ep *_ep, int halt)
 965 {
 966         return mv_ep_set_halt_wedge(_ep, halt, 0);
 967 }
 968
 969 static int mv_ep_set_wedge(struct usb_ep *_ep)
 970 {
 971         return mv_ep_set_halt_wedge(_ep, 1, 1);
 972 }
 973
 974 static struct usb_ep_ops mv_ep_ops = {
 975         .enable         = mv_ep_enable,
 976         .disable        = mv_ep_disable,
 977
 978         .alloc_request  = mv_alloc_request,
 979         .free_request   = mv_free_request,
 980
 981         .queue          = mv_ep_queue,
 982         .dequeue        = mv_ep_dequeue,
 983
 984         .set_wedge      = mv_ep_set_wedge,
 985         .set_halt       = mv_ep_set_halt,
 986         .fifo_flush     = mv_ep_fifo_flush,     /* flush fifo */
 987 };
 988
 989 static void udc_clock_enable(struct mv_udc *udc)
 990 {
 991         unsigned int i;
 992
 993         for (i = 0; i < udc->clknum; i++)
 994                 clk_enable(udc->clk[i]);
 995 }
 996
 997 static void udc_clock_disable(struct mv_udc *udc)
 998 {
 999         unsigned int i;
1000
1001         for (i = 0; i < udc->clknum; i++)
1002                 clk_disable(udc->clk[i]);
1003 }
1004
1005 static void udc_stop(struct mv_udc *udc)
1006 {
1007         u32 tmp;
1008
1009         /* Disable interrupts */
1010         tmp = readl(&udc->op_regs->usbintr);
1011         tmp &= ~(USBINTR_INT_EN | USBINTR_ERR_INT_EN |
1012                 USBINTR_PORT_CHANGE_DETECT_EN | USBINTR_RESET_EN);
1013         writel(tmp, &udc->op_regs->usbintr);
1014
1015         udc->stopped = 1;
1016
1017         /* Reset the Run the bit in the command register to stop VUSB */
1018         tmp = readl(&udc->op_regs->usbcmd);
1019         tmp &= ~USBCMD_RUN_STOP;
1020         writel(tmp, &udc->op_regs->usbcmd);
1021 }
1022
1023 static void udc_start(struct mv_udc *udc)
1024 {
1025         u32 usbintr;
1026
1027         usbintr = USBINTR_INT_EN | USBINTR_ERR_INT_EN
1028                 | USBINTR_PORT_CHANGE_DETECT_EN
1029                 | USBINTR_RESET_EN | USBINTR_DEVICE_SUSPEND;
1030         /* Enable interrupts */
1031         writel(usbintr, &udc->op_regs->usbintr);
1032
1033         udc->stopped = 0;
1034
1035         /* Set the Run bit in the command register */
1036         writel(USBCMD_RUN_STOP, &udc->op_regs->usbcmd);
1037 }
1038
1039 static int udc_reset(struct mv_udc *udc)
1040 {
1041         unsigned int loops;
1042         u32 tmp, portsc;
1043
1044         /* Stop the controller */
1045         tmp = readl(&udc->op_regs->usbcmd);
1046         tmp &= ~USBCMD_RUN_STOP;
1047         writel(tmp, &udc->op_regs->usbcmd);
1048
1049         /* Reset the controller to get default values */
1050         writel(USBCMD_CTRL_RESET, &udc->op_regs->usbcmd);
1051
1052         /* wait for reset to complete */
1053         loops = LOOPS(RESET_TIMEOUT);
1054         while (readl(&udc->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
1055                 if (loops == 0) {
1056                         dev_err(&udc->dev->dev,
1057                                 "Wait for RESET completed TIMEOUT\n");
1058                         return -ETIMEDOUT;
1059                 }
1060                 loops--;
1061                 udelay(LOOPS_USEC);
1062         }
1063
1064         /* set controller to device mode */
1065         tmp = readl(&udc->op_regs->usbmode);
1066         tmp |= USBMODE_CTRL_MODE_DEVICE;
1067
1068         /* turn setup lockout off, require setup tripwire in usbcmd */
1069         tmp |= USBMODE_SETUP_LOCK_OFF | USBMODE_STREAM_DISABLE;
1070
1071         writel(tmp, &udc->op_regs->usbmode);
1072
1073         writel(0x0, &udc->op_regs->epsetupstat);
1074
1075         /* Configure the Endpoint List Address */
1076         writel(udc->ep_dqh_dma & USB_EP_LIST_ADDRESS_MASK,
1077                 &udc->op_regs->eplistaddr);
1078
1079         portsc = readl(&udc->op_regs->portsc[0]);
1080         if (readl(&udc->cap_regs->hcsparams) & HCSPARAMS_PPC)
1081                 portsc &= (~PORTSCX_W1C_BITS | ~PORTSCX_PORT_POWER);
1082
1083         if (udc->force_fs)
1084                 portsc |= PORTSCX_FORCE_FULL_SPEED_CONNECT;
1085         else
1086                 portsc &= (~PORTSCX_FORCE_FULL_SPEED_CONNECT);
1087
1088         writel(portsc, &udc->op_regs->portsc[0]);
1089
1090         tmp = readl(&udc->op_regs->epctrlx[0]);
1091         tmp &= ~(EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL);
1092         writel(tmp, &udc->op_regs->epctrlx[0]);
1093
1094         return 0;
1095 }
1096
1097 static int mv_udc_enable_internal(struct mv_udc *udc)
1098 {
1099         int retval;
1100
1101         if (udc->active)
1102                 return 0;
1103
1104         dev_dbg(&udc->dev->dev, "enable udc\n");
1105         udc_clock_enable(udc);
1106         if (udc->pdata->phy_init) {
1107                 retval = udc->pdata->phy_init(udc->phy_regs);
1108                 if (retval) {
1109                         dev_err(&udc->dev->dev,
1110                                 "init phy error %d\n", retval);
1111                         udc_clock_disable(udc);
1112                         return retval;
1113                 }
1114         }
1115         udc->active = 1;
1116
1117         return 0;
1118 }
1119
1120 static int mv_udc_enable(struct mv_udc *udc)
1121 {
1122         if (udc->clock_gating)
1123                 return mv_udc_enable_internal(udc);
1124
1125         return 0;
1126 }
1127
1128 static void mv_udc_disable_internal(struct mv_udc *udc)
1129 {
1130         if (udc->active) {
1131                 dev_dbg(&udc->dev->dev, "disable udc\n");
1132                 if (udc->pdata->phy_deinit)
1133                         udc->pdata->phy_deinit(udc->phy_regs);
1134                 udc_clock_disable(udc);
1135                 udc->active = 0;
1136         }
1137 }
1138
1139 static void mv_udc_disable(struct mv_udc *udc)
1140 {
1141         if (udc->clock_gating)
1142                 mv_udc_disable_internal(udc);
1143 }
1144
1145 static int mv_udc_get_frame(struct usb_gadget *gadget)
1146 {
1147         struct mv_udc *udc;
1148         u16     retval;
1149
1150         if (!gadget)
1151                 return -ENODEV;
1152
1153         udc = container_of(gadget, struct mv_udc, gadget);
1154
1155         retval = readl(&udc->op_regs->frindex) & USB_FRINDEX_MASKS;
1156
1157         return retval;
1158 }
1159
1160 /* Tries to wake up the host connected to this gadget */
1161 static int mv_udc_wakeup(struct usb_gadget *gadget)
1162 {
1163         struct mv_udc *udc = container_of(gadget, struct mv_udc, gadget);
1164         u32 portsc;
1165
1166         /* Remote wakeup feature not enabled by host */
1167         if (!udc->remote_wakeup)
1168                 return -ENOTSUPP;
1169
1170         portsc = readl(&udc->op_regs->portsc);
1171         /* not suspended? */
1172         if (!(portsc & PORTSCX_PORT_SUSPEND))
1173                 return 0;
1174         /* trigger force resume */
1175         portsc |= PORTSCX_PORT_FORCE_RESUME;
1176         writel(portsc, &udc->op_regs->portsc[0]);
1177         return 0;
1178 }
1179
1180 static int mv_udc_vbus_session(struct usb_gadget *gadget, int is_active)
1181 {
1182         struct mv_udc *udc;
1183         unsigned long flags;
1184         int retval = 0;
1185
1186         udc = container_of(gadget, struct mv_udc, gadget);
1187         spin_lock_irqsave(&udc->lock, flags);
1188
1189         udc->vbus_active = (is_active != 0);
1190
1191         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1192                 __func__, udc->softconnect, udc->vbus_active);
1193
1194         if (udc->driver && udc->softconnect && udc->vbus_active) {
1195                 retval = mv_udc_enable(udc);
1196                 if (retval == 0) {
1197                         /* Clock is disabled, need re-init registers */
1198                         udc_reset(udc);
1199                         ep0_reset(udc);
1200                         udc_start(udc);
1201                 }
1202         } else if (udc->driver && udc->softconnect) {
1203                 /* stop all the transfer in queue*/
1204                 stop_activity(udc, udc->driver);
1205                 udc_stop(udc);
1206                 mv_udc_disable(udc);
1207         }
1208
1209         spin_unlock_irqrestore(&udc->lock, flags);
1210         return retval;
1211 }
1212
1213 static int mv_udc_pullup(struct usb_gadget *gadget, int is_on)
1214 {
1215         struct mv_udc *udc;
1216         unsigned long flags;
1217         int retval = 0;
1218
1219         udc = container_of(gadget, struct mv_udc, gadget);
1220         spin_lock_irqsave(&udc->lock, flags);
1221
1222         udc->softconnect = (is_on != 0);
1223
1224         dev_dbg(&udc->dev->dev, "%s: softconnect %d, vbus_active %d\n",
1225                         __func__, udc->softconnect, udc->vbus_active);
1226
1227         if (udc->driver && udc->softconnect && udc->vbus_active) {
1228                 retval = mv_udc_enable(udc);
1229                 if (retval == 0) {
1230                         /* Clock is disabled, need re-init registers */
1231                         udc_reset(udc);
1232                         ep0_reset(udc);
1233                         udc_start(udc);
1234                 }
1235         } else if (udc->driver && udc->vbus_active) {
1236                 /* stop all the transfer in queue*/
1237                 stop_activity(udc, udc->driver);
1238                 udc_stop(udc);
1239                 mv_udc_disable(udc);
1240         }
1241
1242         spin_unlock_irqrestore(&udc->lock, flags);
1243         return retval;
1244 }
1245
1246 static int mv_udc_start(struct usb_gadget_driver *driver,
1247                 int (*bind)(struct usb_gadget *));
1248 static int mv_udc_stop(struct usb_gadget_driver *driver);
1249 /* device controller usb_gadget_ops structure */
1250 static const struct usb_gadget_ops mv_ops = {
1251
1252         /* returns the current frame number */
1253         .get_frame      = mv_udc_get_frame,
1254
1255         /* tries to wake up the host connected to this gadget */
1256         .wakeup         = mv_udc_wakeup,
1257
1258         /* notify controller that VBUS is powered or not */
1259         .vbus_session   = mv_udc_vbus_session,
1260
1261         /* D+ pullup, software-controlled connect/disconnect to USB host */
1262         .pullup         = mv_udc_pullup,
1263         .start          = mv_udc_start,
1264         .stop           = mv_udc_stop,
1265 };
1266
1267 static int eps_init(struct mv_udc *udc)
1268 {
1269         struct mv_ep    *ep;
1270         char name[14];
1271         int i;
1272
1273         /* initialize ep0 */
1274         ep = &udc->eps[0];
1275         ep->udc = udc;
1276         strncpy(ep->name, "ep0", sizeof(ep->name));
1277         ep->ep.name = ep->name;
1278         ep->ep.ops = &mv_ep_ops;
1279         ep->wedge = 0;
1280         ep->stopped = 0;
1281         ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
1282         ep->ep_num = 0;
1283         ep->desc = &mv_ep0_desc;
1284         INIT_LIST_HEAD(&ep->queue);
1285
1286         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1287
1288         /* initialize other endpoints */
1289         for (i = 2; i < udc->max_eps * 2; i++) {
1290                 ep = &udc->eps[i];
1291                 if (i % 2) {
1292                         snprintf(name, sizeof(name), "ep%din", i / 2);
1293                         ep->direction = EP_DIR_IN;
1294                 } else {
1295                         snprintf(name, sizeof(name), "ep%dout", i / 2);
1296                         ep->direction = EP_DIR_OUT;
1297                 }
1298                 ep->udc = udc;
1299                 strncpy(ep->name, name, sizeof(ep->name));
1300                 ep->ep.name = ep->name;
1301
1302                 ep->ep.ops = &mv_ep_ops;
1303                 ep->stopped = 0;
1304                 ep->ep.maxpacket = (unsigned short) ~0;
1305                 ep->ep_num = i / 2;
1306
1307                 INIT_LIST_HEAD(&ep->queue);
1308                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1309
1310                 ep->dqh = &udc->ep_dqh[i];
1311         }
1312
1313         return 0;
1314 }
1315
1316 /* delete all endpoint requests, called with spinlock held */
1317 static void nuke(struct mv_ep *ep, int status)
1318 {
1319         /* called with spinlock held */
1320         ep->stopped = 1;
1321
1322         /* endpoint fifo flush */
1323         mv_ep_fifo_flush(&ep->ep);
1324
1325         while (!list_empty(&ep->queue)) {
1326                 struct mv_req *req = NULL;
1327                 req = list_entry(ep->queue.next, struct mv_req, queue);
1328                 done(ep, req, status);
1329         }
1330 }
1331
1332 /* stop all USB activities */
1333 static void stop_activity(struct mv_udc *udc, struct usb_gadget_driver *driver)
1334 {
1335         struct mv_ep    *ep;
1336
1337         nuke(&udc->eps[0], -ESHUTDOWN);
1338
1339         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
1340                 nuke(ep, -ESHUTDOWN);
1341         }
1342
1343         /* report disconnect; the driver is already quiesced */
1344         if (driver) {
1345                 spin_unlock(&udc->lock);
1346                 driver->disconnect(&udc->gadget);
1347                 spin_lock(&udc->lock);
1348         }
1349 }
1350
1351 static int mv_udc_start(struct usb_gadget_driver *driver,
1352                 int (*bind)(struct usb_gadget *))
1353 {
1354         struct mv_udc *udc = the_controller;
1355         int retval = 0;
1356         unsigned long flags;
1357
1358         if (!udc)
1359                 return -ENODEV;
1360
1361         if (udc->driver)
1362                 return -EBUSY;
1363
1364         spin_lock_irqsave(&udc->lock, flags);
1365
1366         /* hook up the driver ... */
1367         driver->driver.bus = NULL;
1368         udc->driver = driver;
1369         udc->gadget.dev.driver = &driver->driver;
1370
1371         udc->usb_state = USB_STATE_ATTACHED;
1372         udc->ep0_state = WAIT_FOR_SETUP;
1373         udc->ep0_dir = EP_DIR_OUT;
1374
1375         spin_unlock_irqrestore(&udc->lock, flags);
1376
1377         retval = bind(&udc->gadget);
1378         if (retval) {
1379                 dev_err(&udc->dev->dev, "bind to driver %s --> %d\n",
1380                                 driver->driver.name, retval);
1381                 udc->driver = NULL;
1382                 udc->gadget.dev.driver = NULL;
1383                 return retval;
1384         }
1385
1386         if (udc->transceiver) {
1387                 retval = otg_set_peripheral(udc->transceiver->otg,
1388                                         &udc->gadget);
1389                 if (retval) {
1390                         dev_err(&udc->dev->dev,
1391                                 "unable to register peripheral to otg\n");
1392                         if (driver->unbind) {
1393                                 driver->unbind(&udc->gadget);
1394                                 udc->gadget.dev.driver = NULL;
1395                                 udc->driver = NULL;
1396                         }
1397                         return retval;
1398                 }
1399         }
1400
1401         /* pullup is always on */
1402         mv_udc_pullup(&udc->gadget, 1);
1403
1404         /* When boot with cable attached, there will be no vbus irq occurred */
1405         if (udc->qwork)
1406                 queue_work(udc->qwork, &udc->vbus_work);
1407
1408         return 0;
1409 }
1410
1411 static int mv_udc_stop(struct usb_gadget_driver *driver)
1412 {
1413         struct mv_udc *udc = the_controller;
1414         unsigned long flags;
1415
1416         if (!udc)
1417                 return -ENODEV;
1418
1419         spin_lock_irqsave(&udc->lock, flags);
1420
1421         mv_udc_enable(udc);
1422         udc_stop(udc);
1423
1424         /* stop all usb activities */
1425         udc->gadget.speed = USB_SPEED_UNKNOWN;
1426         stop_activity(udc, driver);
1427         mv_udc_disable(udc);
1428
1429         spin_unlock_irqrestore(&udc->lock, flags);
1430
1431         /* unbind gadget driver */
1432         driver->unbind(&udc->gadget);
1433         udc->gadget.dev.driver = NULL;
1434         udc->driver = NULL;
1435
1436         return 0;
1437 }
1438
1439 static void mv_set_ptc(struct mv_udc *udc, u32 mode)
1440 {
1441         u32 portsc;
1442
1443         portsc = readl(&udc->op_regs->portsc[0]);
1444         portsc |= mode << 16;
1445         writel(portsc, &udc->op_regs->portsc[0]);
1446 }
1447
1448 static void prime_status_complete(struct usb_ep *ep, struct usb_request *_req)
1449 {
1450         struct mv_udc *udc = the_controller;
1451         struct mv_req *req = container_of(_req, struct mv_req, req);
1452         unsigned long flags;
1453
1454         dev_info(&udc->dev->dev, "switch to test mode %d\n", req->test_mode);
1455
1456         spin_lock_irqsave(&udc->lock, flags);
1457         if (req->test_mode) {
1458                 mv_set_ptc(udc, req->test_mode);
1459                 req->test_mode = 0;
1460         }
1461         spin_unlock_irqrestore(&udc->lock, flags);
1462 }
1463
1464 static int
1465 udc_prime_status(struct mv_udc *udc, u8 direction, u16 status, bool empty)
1466 {
1467         int retval = 0;
1468         struct mv_req *req;
1469         struct mv_ep *ep;
1470
1471         ep = &udc->eps[0];
1472         udc->ep0_dir = direction;
1473         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1474
1475         req = udc->status_req;
1476
1477         /* fill in the reqest structure */
1478         if (empty == false) {
1479                 *((u16 *) req->req.buf) = cpu_to_le16(status);
1480                 req->req.length = 2;
1481         } else
1482                 req->req.length = 0;
1483
1484         req->ep = ep;
1485         req->req.status = -EINPROGRESS;
1486         req->req.actual = 0;
1487         if (udc->test_mode) {
1488                 req->req.complete = prime_status_complete;
1489                 req->test_mode = udc->test_mode;
1490                 udc->test_mode = 0;
1491         } else
1492                 req->req.complete = NULL;
1493         req->dtd_count = 0;
1494
1495         if (req->req.dma == DMA_ADDR_INVALID) {
1496                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1497                                 req->req.buf, req->req.length,
1498                                 ep_dir(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1499                 req->mapped = 1;
1500         }
1501
1502         /* prime the data phase */
1503         if (!req_to_dtd(req))
1504                 retval = queue_dtd(ep, req);
1505         else{   /* no mem */
1506                 retval = -ENOMEM;
1507                 goto out;
1508         }
1509
1510         if (retval) {
1511                 dev_err(&udc->dev->dev, "response error on GET_STATUS request\n");
1512                 goto out;
1513         }
1514
1515         list_add_tail(&req->queue, &ep->queue);
1516
1517         return 0;
1518 out:
1519         return retval;
1520 }
1521
1522 static void mv_udc_testmode(struct mv_udc *udc, u16 index)
1523 {
1524         if (index <= TEST_FORCE_EN) {
1525                 udc->test_mode = index;
1526                 if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1527                         ep0_stall(udc);
1528         } else
1529                 dev_err(&udc->dev->dev,
1530                         "This test mode(%d) is not supported\n", index);
1531 }
1532
1533 static void ch9setaddress(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1534 {
1535         udc->dev_addr = (u8)setup->wValue;
1536
1537         /* update usb state */
1538         udc->usb_state = USB_STATE_ADDRESS;
1539
1540         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1541                 ep0_stall(udc);
1542 }
1543
1544 static void ch9getstatus(struct mv_udc *udc, u8 ep_num,
1545         struct usb_ctrlrequest *setup)
1546 {
1547         u16 status = 0;
1548         int retval;
1549
1550         if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1551                 != (USB_DIR_IN | USB_TYPE_STANDARD))
1552                 return;
1553
1554         if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1555                 status = 1 << USB_DEVICE_SELF_POWERED;
1556                 status |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1557         } else if ((setup->bRequestType & USB_RECIP_MASK)
1558                         == USB_RECIP_INTERFACE) {
1559                 /* get interface status */
1560                 status = 0;
1561         } else if ((setup->bRequestType & USB_RECIP_MASK)
1562                         == USB_RECIP_ENDPOINT) {
1563                 u8 ep_num, direction;
1564
1565                 ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1566                 direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1567                                 ? EP_DIR_IN : EP_DIR_OUT;
1568                 status = ep_is_stall(udc, ep_num, direction)
1569                                 << USB_ENDPOINT_HALT;
1570         }
1571
1572         retval = udc_prime_status(udc, EP_DIR_IN, status, false);
1573         if (retval)
1574                 ep0_stall(udc);
1575         else
1576                 udc->ep0_state = DATA_STATE_XMIT;
1577 }
1578
1579 static void ch9clearfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1580 {
1581         u8 ep_num;
1582         u8 direction;
1583         struct mv_ep *ep;
1584
1585         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1586                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1587                 switch (setup->wValue) {
1588                 case USB_DEVICE_REMOTE_WAKEUP:
1589                         udc->remote_wakeup = 0;
1590                         break;
1591                 default:
1592                         goto out;
1593                 }
1594         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1595                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1596                 switch (setup->wValue) {
1597                 case USB_ENDPOINT_HALT:
1598                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1599                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1600                                 ? EP_DIR_IN : EP_DIR_OUT;
1601                         if (setup->wValue != 0 || setup->wLength != 0
1602                                 || ep_num > udc->max_eps)
1603                                 goto out;
1604                         ep = &udc->eps[ep_num * 2 + direction];
1605                         if (ep->wedge == 1)
1606                                 break;
1607                         spin_unlock(&udc->lock);
1608                         ep_set_stall(udc, ep_num, direction, 0);
1609                         spin_lock(&udc->lock);
1610                         break;
1611                 default:
1612                         goto out;
1613                 }
1614         } else
1615                 goto out;
1616
1617         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1618                 ep0_stall(udc);
1619 out:
1620         return;
1621 }
1622
1623 static void ch9setfeature(struct mv_udc *udc, struct usb_ctrlrequest *setup)
1624 {
1625         u8 ep_num;
1626         u8 direction;
1627
1628         if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1629                 == ((USB_TYPE_STANDARD | USB_RECIP_DEVICE))) {
1630                 switch (setup->wValue) {
1631                 case USB_DEVICE_REMOTE_WAKEUP:
1632                         udc->remote_wakeup = 1;
1633                         break;
1634                 case USB_DEVICE_TEST_MODE:
1635                         if (setup->wIndex & 0xFF
1636                                 ||  udc->gadget.speed != USB_SPEED_HIGH)
1637                                 ep0_stall(udc);
1638
1639                         if (udc->usb_state != USB_STATE_CONFIGURED
1640                                 && udc->usb_state != USB_STATE_ADDRESS
1641                                 && udc->usb_state != USB_STATE_DEFAULT)
1642                                 ep0_stall(udc);
1643
1644                         mv_udc_testmode(udc, (setup->wIndex >> 8));
1645                         goto out;
1646                 default:
1647                         goto out;
1648                 }
1649         } else if ((setup->bRequestType & (USB_TYPE_MASK | USB_RECIP_MASK))
1650                 == ((USB_TYPE_STANDARD | USB_RECIP_ENDPOINT))) {
1651                 switch (setup->wValue) {
1652                 case USB_ENDPOINT_HALT:
1653                         ep_num = setup->wIndex & USB_ENDPOINT_NUMBER_MASK;
1654                         direction = (setup->wIndex & USB_ENDPOINT_DIR_MASK)
1655                                 ? EP_DIR_IN : EP_DIR_OUT;
1656                         if (setup->wValue != 0 || setup->wLength != 0
1657                                 || ep_num > udc->max_eps)
1658                                 goto out;
1659                         spin_unlock(&udc->lock);
1660                         ep_set_stall(udc, ep_num, direction, 1);
1661                         spin_lock(&udc->lock);
1662                         break;
1663                 default:
1664                         goto out;
1665                 }
1666         } else
1667                 goto out;
1668
1669         if (udc_prime_status(udc, EP_DIR_IN, 0, true))
1670                 ep0_stall(udc);
1671 out:
1672         return;
1673 }
1674
1675 static void handle_setup_packet(struct mv_udc *udc, u8 ep_num,
1676         struct usb_ctrlrequest *setup)
1677 {
1678         bool delegate = false;
1679
1680         nuke(&udc->eps[ep_num * 2 + EP_DIR_OUT], -ESHUTDOWN);
1681
1682         dev_dbg(&udc->dev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1683                         setup->bRequestType, setup->bRequest,
1684                         setup->wValue, setup->wIndex, setup->wLength);
1685         /* We process some stardard setup requests here */
1686         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1687                 switch (setup->bRequest) {
1688                 case USB_REQ_GET_STATUS:
1689                         ch9getstatus(udc, ep_num, setup);
1690                         break;
1691
1692                 case USB_REQ_SET_ADDRESS:
1693                         ch9setaddress(udc, setup);
1694                         break;
1695
1696                 case USB_REQ_CLEAR_FEATURE:
1697                         ch9clearfeature(udc, setup);
1698                         break;
1699
1700                 case USB_REQ_SET_FEATURE:
1701                         ch9setfeature(udc, setup);
1702                         break;
1703
1704                 default:
1705                         delegate = true;
1706                 }
1707         } else
1708                 delegate = true;
1709
1710         /* delegate USB standard requests to the gadget driver */
1711         if (delegate == true) {
1712                 /* USB requests handled by gadget */
1713                 if (setup->wLength) {
1714                         /* DATA phase from gadget, STATUS phase from udc */
1715                         udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1716                                         ?  EP_DIR_IN : EP_DIR_OUT;
1717                         spin_unlock(&udc->lock);
1718                         if (udc->driver->setup(&udc->gadget,
1719                                 &udc->local_setup_buff) < 0)
1720                                 ep0_stall(udc);
1721                         spin_lock(&udc->lock);
1722                         udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1723                                         ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1724                 } else {
1725                         /* no DATA phase, IN STATUS phase from gadget */
1726                         udc->ep0_dir = EP_DIR_IN;
1727                         spin_unlock(&udc->lock);
1728                         if (udc->driver->setup(&udc->gadget,
1729                                 &udc->local_setup_buff) < 0)
1730                                 ep0_stall(udc);
1731                         spin_lock(&udc->lock);
1732                         udc->ep0_state = WAIT_FOR_OUT_STATUS;
1733                 }
1734         }
1735 }
1736
1737 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1738 static void ep0_req_complete(struct mv_udc *udc,
1739         struct mv_ep *ep0, struct mv_req *req)
1740 {
1741         u32 new_addr;
1742
1743         if (udc->usb_state == USB_STATE_ADDRESS) {
1744                 /* set the new address */
1745                 new_addr = (u32)udc->dev_addr;
1746                 writel(new_addr << USB_DEVICE_ADDRESS_BIT_SHIFT,
1747                         &udc->op_regs->deviceaddr);
1748         }
1749
1750         done(ep0, req, 0);
1751
1752         switch (udc->ep0_state) {
1753         case DATA_STATE_XMIT:
1754                 /* receive status phase */
1755                 if (udc_prime_status(udc, EP_DIR_OUT, 0, true))
1756                         ep0_stall(udc);
1757                 break;
1758         case DATA_STATE_RECV:
1759                 /* send status phase */
1760                 if (udc_prime_status(udc, EP_DIR_IN, 0 , true))
1761                         ep0_stall(udc);
1762                 break;
1763         case WAIT_FOR_OUT_STATUS:
1764                 udc->ep0_state = WAIT_FOR_SETUP;
1765                 break;
1766         case WAIT_FOR_SETUP:
1767                 dev_err(&udc->dev->dev, "unexpect ep0 packets\n");
1768                 break;
1769         default:
1770                 ep0_stall(udc);
1771                 break;
1772         }
1773 }
1774
1775 static void get_setup_data(struct mv_udc *udc, u8 ep_num, u8 *buffer_ptr)
1776 {
1777         u32 temp;
1778         struct mv_dqh *dqh;
1779
1780         dqh = &udc->ep_dqh[ep_num * 2 + EP_DIR_OUT];
1781
1782         /* Clear bit in ENDPTSETUPSTAT */
1783         writel((1 << ep_num), &udc->op_regs->epsetupstat);
1784
1785         /* while a hazard exists when setup package arrives */
1786         do {
1787                 /* Set Setup Tripwire */
1788                 temp = readl(&udc->op_regs->usbcmd);
1789                 writel(temp | USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1790
1791                 /* Copy the setup packet to local buffer */
1792                 memcpy(buffer_ptr, (u8 *) dqh->setup_buffer, 8);
1793         } while (!(readl(&udc->op_regs->usbcmd) & USBCMD_SETUP_TRIPWIRE_SET));
1794
1795         /* Clear Setup Tripwire */
1796         temp = readl(&udc->op_regs->usbcmd);
1797         writel(temp & ~USBCMD_SETUP_TRIPWIRE_SET, &udc->op_regs->usbcmd);
1798 }
1799
1800 static void irq_process_tr_complete(struct mv_udc *udc)
1801 {
1802         u32 tmp, bit_pos;
1803         int i, ep_num = 0, direction = 0;
1804         struct mv_ep    *curr_ep;
1805         struct mv_req *curr_req, *temp_req;
1806         int status;
1807
1808         /*
1809          * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1810          * because the setup packets are to be read ASAP
1811          */
1812
1813         /* Process all Setup packet received interrupts */
1814         tmp = readl(&udc->op_regs->epsetupstat);
1815
1816         if (tmp) {
1817                 for (i = 0; i < udc->max_eps; i++) {
1818                         if (tmp & (1 << i)) {
1819                                 get_setup_data(udc, i,
1820                                         (u8 *)(&udc->local_setup_buff));
1821                                 handle_setup_packet(udc, i,
1822                                         &udc->local_setup_buff);
1823                         }
1824                 }
1825         }
1826
1827         /* Don't clear the endpoint setup status register here.
1828          * It is cleared as a setup packet is read out of the buffer
1829          */
1830
1831         /* Process non-setup transaction complete interrupts */
1832         tmp = readl(&udc->op_regs->epcomplete);
1833
1834         if (!tmp)
1835                 return;
1836
1837         writel(tmp, &udc->op_regs->epcomplete);
1838
1839         for (i = 0; i < udc->max_eps * 2; i++) {
1840                 ep_num = i >> 1;
1841                 direction = i % 2;
1842
1843                 bit_pos = 1 << (ep_num + 16 * direction);
1844
1845                 if (!(bit_pos & tmp))
1846                         continue;
1847
1848                 if (i == 1)
1849                         curr_ep = &udc->eps[0];
1850                 else
1851                         curr_ep = &udc->eps[i];
1852                 /* process the req queue until an uncomplete request */
1853                 list_for_each_entry_safe(curr_req, temp_req,
1854                         &curr_ep->queue, queue) {
1855                         status = process_ep_req(udc, i, curr_req);
1856                         if (status)
1857                                 break;
1858
1859                         /* write back status to req */
1860                         curr_req->req.status = status;
1861
1862                         /* ep0 request completion */
1863                         if (ep_num == 0) {
1864                                 ep0_req_complete(udc, curr_ep, curr_req);
1865                                 break;
1866                         } else {
1867                                 done(curr_ep, curr_req, status);
1868                         }
1869                 }
1870         }
1871 }
1872
1873 void irq_process_reset(struct mv_udc *udc)
1874 {
1875         u32 tmp;
1876         unsigned int loops;
1877
1878         udc->ep0_dir = EP_DIR_OUT;
1879         udc->ep0_state = WAIT_FOR_SETUP;
1880         udc->remote_wakeup = 0;         /* default to 0 on reset */
1881
1882         /* The address bits are past bit 25-31. Set the address */
1883         tmp = readl(&udc->op_regs->deviceaddr);
1884         tmp &= ~(USB_DEVICE_ADDRESS_MASK);
1885         writel(tmp, &udc->op_regs->deviceaddr);
1886
1887         /* Clear all the setup token semaphores */
1888         tmp = readl(&udc->op_regs->epsetupstat);
1889         writel(tmp, &udc->op_regs->epsetupstat);
1890
1891         /* Clear all the endpoint complete status bits */
1892         tmp = readl(&udc->op_regs->epcomplete);
1893         writel(tmp, &udc->op_regs->epcomplete);
1894
1895         /* wait until all endptprime bits cleared */
1896         loops = LOOPS(PRIME_TIMEOUT);
1897         while (readl(&udc->op_regs->epprime) & 0xFFFFFFFF) {
1898                 if (loops == 0) {
1899                         dev_err(&udc->dev->dev,
1900                                 "Timeout for ENDPTPRIME = 0x%x\n",
1901                                 readl(&udc->op_regs->epprime));
1902                         break;
1903                 }
1904                 loops--;
1905                 udelay(LOOPS_USEC);
1906         }
1907
1908         /* Write 1s to the Flush register */
1909         writel((u32)~0, &udc->op_regs->epflush);
1910
1911         if (readl(&udc->op_regs->portsc[0]) & PORTSCX_PORT_RESET) {
1912                 dev_info(&udc->dev->dev, "usb bus reset\n");
1913                 udc->usb_state = USB_STATE_DEFAULT;
1914                 /* reset all the queues, stop all USB activities */
1915                 stop_activity(udc, udc->driver);
1916         } else {
1917                 dev_info(&udc->dev->dev, "USB reset portsc 0x%x\n",
1918                         readl(&udc->op_regs->portsc));
1919
1920                 /*
1921                  * re-initialize
1922                  * controller reset
1923                  */
1924                 udc_reset(udc);
1925
1926                 /* reset all the queues, stop all USB activities */
1927                 stop_activity(udc, udc->driver);
1928
1929                 /* reset ep0 dQH and endptctrl */
1930                 ep0_reset(udc);
1931
1932                 /* enable interrupt and set controller to run state */
1933                 udc_start(udc);
1934
1935                 udc->usb_state = USB_STATE_ATTACHED;
1936         }
1937 }
1938
1939 static void handle_bus_resume(struct mv_udc *udc)
1940 {
1941         udc->usb_state = udc->resume_state;
1942         udc->resume_state = 0;
1943
1944         /* report resume to the driver */
1945         if (udc->driver) {
1946                 if (udc->driver->resume) {
1947                         spin_unlock(&udc->lock);
1948                         udc->driver->resume(&udc->gadget);
1949                         spin_lock(&udc->lock);
1950                 }
1951         }
1952 }
1953
1954 static void irq_process_suspend(struct mv_udc *udc)
1955 {
1956         udc->resume_state = udc->usb_state;
1957         udc->usb_state = USB_STATE_SUSPENDED;
1958
1959         if (udc->driver->suspend) {
1960                 spin_unlock(&udc->lock);
1961                 udc->driver->suspend(&udc->gadget);
1962                 spin_lock(&udc->lock);
1963         }
1964 }
1965
1966 static void irq_process_port_change(struct mv_udc *udc)
1967 {
1968         u32 portsc;
1969
1970         portsc = readl(&udc->op_regs->portsc[0]);
1971         if (!(portsc & PORTSCX_PORT_RESET)) {
1972                 /* Get the speed */
1973                 u32 speed = portsc & PORTSCX_PORT_SPEED_MASK;
1974                 switch (speed) {
1975                 case PORTSCX_PORT_SPEED_HIGH:
1976                         udc->gadget.speed = USB_SPEED_HIGH;
1977                         break;
1978                 case PORTSCX_PORT_SPEED_FULL:
1979                         udc->gadget.speed = USB_SPEED_FULL;
1980                         break;
1981                 case PORTSCX_PORT_SPEED_LOW:
1982                         udc->gadget.speed = USB_SPEED_LOW;
1983                         break;
1984                 default:
1985                         udc->gadget.speed = USB_SPEED_UNKNOWN;
1986                         break;
1987                 }
1988         }
1989
1990         if (portsc & PORTSCX_PORT_SUSPEND) {
1991                 udc->resume_state = udc->usb_state;
1992                 udc->usb_state = USB_STATE_SUSPENDED;
1993                 if (udc->driver->suspend) {
1994                         spin_unlock(&udc->lock);
1995                         udc->driver->suspend(&udc->gadget);
1996                         spin_lock(&udc->lock);
1997                 }
1998         }
1999
2000         if (!(portsc & PORTSCX_PORT_SUSPEND)
2001                 && udc->usb_state == USB_STATE_SUSPENDED) {
2002                 handle_bus_resume(udc);
2003         }
2004
2005         if (!udc->resume_state)
2006                 udc->usb_state = USB_STATE_DEFAULT;
2007 }
2008
2009 static void irq_process_error(struct mv_udc *udc)
2010 {
2011         /* Increment the error count */
2012         udc->errors++;
2013 }
2014
2015 static irqreturn_t mv_udc_irq(int irq, void *dev)
2016 {
2017         struct mv_udc *udc = (struct mv_udc *)dev;
2018         u32 status, intr;
2019
2020         /* Disable ISR when stopped bit is set */
2021         if (udc->stopped)
2022                 return IRQ_NONE;
2023
2024         spin_lock(&udc->lock);
2025
2026         status = readl(&udc->op_regs->usbsts);
2027         intr = readl(&udc->op_regs->usbintr);
2028         status &= intr;
2029
2030         if (status == 0) {
2031                 spin_unlock(&udc->lock);
2032                 return IRQ_NONE;
2033         }
2034
2035         /* Clear all the interrupts occurred */
2036         writel(status, &udc->op_regs->usbsts);
2037
2038         if (status & USBSTS_ERR)
2039                 irq_process_error(udc);
2040
2041         if (status & USBSTS_RESET)
2042                 irq_process_reset(udc);
2043
2044         if (status & USBSTS_PORT_CHANGE)
2045                 irq_process_port_change(udc);
2046
2047         if (status & USBSTS_INT)
2048                 irq_process_tr_complete(udc);
2049
2050         if (status & USBSTS_SUSPEND)
2051                 irq_process_suspend(udc);
2052
2053         spin_unlock(&udc->lock);
2054
2055         return IRQ_HANDLED;
2056 }
2057
2058 static irqreturn_t mv_udc_vbus_irq(int irq, void *dev)
2059 {
2060         struct mv_udc *udc = (struct mv_udc *)dev;
2061
2062         /* polling VBUS and init phy may cause too much time*/
2063         if (udc->qwork)
2064                 queue_work(udc->qwork, &udc->vbus_work);
2065
2066         return IRQ_HANDLED;
2067 }
2068
2069 static void mv_udc_vbus_work(struct work_struct *work)
2070 {
2071         struct mv_udc *udc;
2072         unsigned int vbus;
2073
2074         udc = container_of(work, struct mv_udc, vbus_work);
2075         if (!udc->pdata->vbus)
2076                 return;
2077
2078         vbus = udc->pdata->vbus->poll();
2079         dev_info(&udc->dev->dev, "vbus is %d\n", vbus);
2080
2081         if (vbus == VBUS_HIGH)
2082                 mv_udc_vbus_session(&udc->gadget, 1);
2083         else if (vbus == VBUS_LOW)
2084                 mv_udc_vbus_session(&udc->gadget, 0);
2085 }
2086
2087 /* release device structure */
2088 static void gadget_release(struct device *_dev)
2089 {
2090         struct mv_udc *udc = the_controller;
2091
2092         complete(udc->done);
2093 }
2094
2095 static int __devexit mv_udc_remove(struct platform_device *dev)
2096 {
2097         struct mv_udc *udc = the_controller;
2098         int clk_i;
2099
2100         usb_del_gadget_udc(&udc->gadget);
2101
2102         if (udc->qwork) {
2103                 flush_workqueue(udc->qwork);
2104                 destroy_workqueue(udc->qwork);
2105         }
2106
2107         /*
2108          * If we have transceiver inited,
2109          * then vbus irq will not be requested in udc driver.
2110          */
2111         if (udc->pdata && udc->pdata->vbus
2112                 && udc->clock_gating && udc->transceiver == NULL)
2113                 free_irq(udc->pdata->vbus->irq, &dev->dev);
2114
2115         /* free memory allocated in probe */
2116         if (udc->dtd_pool)
2117                 dma_pool_destroy(udc->dtd_pool);
2118
2119         if (udc->ep_dqh)
2120                 dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2121                         udc->ep_dqh, udc->ep_dqh_dma);
2122
2123         kfree(udc->eps);
2124
2125         if (udc->irq)
2126                 free_irq(udc->irq, &dev->dev);
2127
2128         mv_udc_disable(udc);
2129
2130         if (udc->cap_regs)
2131                 iounmap(udc->cap_regs);
2132
2133         if (udc->phy_regs)
2134                 iounmap(udc->phy_regs);
2135
2136         if (udc->status_req) {
2137                 kfree(udc->status_req->req.buf);
2138                 kfree(udc->status_req);
2139         }
2140
2141         for (clk_i = 0; clk_i <= udc->clknum; clk_i++)
2142                 clk_put(udc->clk[clk_i]);
2143
2144         device_unregister(&udc->gadget.dev);
2145
2146         /* free dev, wait for the release() finished */
2147         wait_for_completion(udc->done);
2148         kfree(udc);
2149
2150         the_controller = NULL;
2151
2152         return 0;
2153 }
2154
2155 static int __devinit mv_udc_probe(struct platform_device *dev)
2156 {
2157         struct mv_usb_platform_data *pdata = dev->dev.platform_data;
2158         struct mv_udc *udc;
2159         int retval = 0;
2160         int clk_i = 0;
2161         struct resource *r;
2162         size_t size;
2163
2164         if (pdata == NULL) {
2165                 dev_err(&dev->dev, "missing platform_data\n");
2166                 return -ENODEV;
2167         }
2168
2169         size = sizeof(*udc) + sizeof(struct clk *) * pdata->clknum;
2170         udc = kzalloc(size, GFP_KERNEL);
2171         if (udc == NULL) {
2172                 dev_err(&dev->dev, "failed to allocate memory for udc\n");
2173                 return -ENOMEM;
2174         }
2175
2176         the_controller = udc;
2177         udc->done = &release_done;
2178         udc->pdata = dev->dev.platform_data;
2179         spin_lock_init(&udc->lock);
2180
2181         udc->dev = dev;
2182
2183 #ifdef CONFIG_USB_OTG_UTILS
2184         if (pdata->mode == MV_USB_MODE_OTG)
2185                 udc->transceiver = usb_get_transceiver();
2186 #endif
2187
2188         udc->clknum = pdata->clknum;
2189         for (clk_i = 0; clk_i < udc->clknum; clk_i++) {
2190                 udc->clk[clk_i] = clk_get(&dev->dev, pdata->clkname[clk_i]);
2191                 if (IS_ERR(udc->clk[clk_i])) {
2192                         retval = PTR_ERR(udc->clk[clk_i]);
2193                         goto err_put_clk;
2194                 }
2195         }
2196
2197         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "capregs");
2198         if (r == NULL) {
2199                 dev_err(&dev->dev, "no I/O memory resource defined\n");
2200                 retval = -ENODEV;
2201                 goto err_put_clk;
2202         }
2203
2204         udc->cap_regs = (struct mv_cap_regs __iomem *)
2205                 ioremap(r->start, resource_size(r));
2206         if (udc->cap_regs == NULL) {
2207                 dev_err(&dev->dev, "failed to map I/O memory\n");
2208                 retval = -EBUSY;
2209                 goto err_put_clk;
2210         }
2211
2212         r = platform_get_resource_byname(udc->dev, IORESOURCE_MEM, "phyregs");
2213         if (r == NULL) {
2214                 dev_err(&dev->dev, "no phy I/O memory resource defined\n");
2215                 retval = -ENODEV;
2216                 goto err_iounmap_capreg;
2217         }
2218
2219         udc->phy_regs = ioremap(r->start, resource_size(r));
2220         if (udc->phy_regs == NULL) {
2221                 dev_err(&dev->dev, "failed to map phy I/O memory\n");
2222                 retval = -EBUSY;
2223                 goto err_iounmap_capreg;
2224         }
2225
2226         /* we will acces controller register, so enable the clk */
2227         retval = mv_udc_enable_internal(udc);
2228         if (retval)
2229                 goto err_iounmap_phyreg;
2230
2231         udc->op_regs =
2232                 (struct mv_op_regs __iomem *)((unsigned long)udc->cap_regs
2233                 + (readl(&udc->cap_regs->caplength_hciversion)
2234                         & CAPLENGTH_MASK));
2235         udc->max_eps = readl(&udc->cap_regs->dccparams) & DCCPARAMS_DEN_MASK;
2236
2237         /*
2238          * some platform will use usb to download image, it may not disconnect
2239          * usb gadget before loading kernel. So first stop udc here.
2240          */
2241         udc_stop(udc);
2242         writel(0xFFFFFFFF, &udc->op_regs->usbsts);
2243
2244         size = udc->max_eps * sizeof(struct mv_dqh) *2;
2245         size = (size + DQH_ALIGNMENT - 1) & ~(DQH_ALIGNMENT - 1);
2246         udc->ep_dqh = dma_alloc_coherent(&dev->dev, size,
2247                                         &udc->ep_dqh_dma, GFP_KERNEL);
2248
2249         if (udc->ep_dqh == NULL) {
2250                 dev_err(&dev->dev, "allocate dQH memory failed\n");
2251                 retval = -ENOMEM;
2252                 goto err_disable_clock;
2253         }
2254         udc->ep_dqh_size = size;
2255
2256         /* create dTD dma_pool resource */
2257         udc->dtd_pool = dma_pool_create("mv_dtd",
2258                         &dev->dev,
2259                         sizeof(struct mv_dtd),
2260                         DTD_ALIGNMENT,
2261                         DMA_BOUNDARY);
2262
2263         if (!udc->dtd_pool) {
2264                 retval = -ENOMEM;
2265                 goto err_free_dma;
2266         }
2267
2268         size = udc->max_eps * sizeof(struct mv_ep) *2;
2269         udc->eps = kzalloc(size, GFP_KERNEL);
2270         if (udc->eps == NULL) {
2271                 dev_err(&dev->dev, "allocate ep memory failed\n");
2272                 retval = -ENOMEM;
2273                 goto err_destroy_dma;
2274         }
2275
2276         /* initialize ep0 status request structure */
2277         udc->status_req = kzalloc(sizeof(struct mv_req), GFP_KERNEL);
2278         if (!udc->status_req) {
2279                 dev_err(&dev->dev, "allocate status_req memory failed\n");
2280                 retval = -ENOMEM;
2281                 goto err_free_eps;
2282         }
2283         INIT_LIST_HEAD(&udc->status_req->queue);
2284
2285         /* allocate a small amount of memory to get valid address */
2286         udc->status_req->req.buf = kzalloc(8, GFP_KERNEL);
2287         udc->status_req->req.dma = DMA_ADDR_INVALID;
2288
2289         udc->resume_state = USB_STATE_NOTATTACHED;
2290         udc->usb_state = USB_STATE_POWERED;
2291         udc->ep0_dir = EP_DIR_OUT;
2292         udc->remote_wakeup = 0;
2293
2294         r = platform_get_resource(udc->dev, IORESOURCE_IRQ, 0);
2295         if (r == NULL) {
2296                 dev_err(&dev->dev, "no IRQ resource defined\n");
2297                 retval = -ENODEV;
2298                 goto err_free_status_req;
2299         }
2300         udc->irq = r->start;
2301         if (request_irq(udc->irq, mv_udc_irq,
2302                 IRQF_SHARED, driver_name, udc)) {
2303                 dev_err(&dev->dev, "Request irq %d for UDC failed\n",
2304                         udc->irq);
2305                 retval = -ENODEV;
2306                 goto err_free_status_req;
2307         }
2308
2309         /* initialize gadget structure */
2310         udc->gadget.ops = &mv_ops;      /* usb_gadget_ops */
2311         udc->gadget.ep0 = &udc->eps[0].ep;      /* gadget ep0 */
2312         INIT_LIST_HEAD(&udc->gadget.ep_list);   /* ep_list */
2313         udc->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
2314         udc->gadget.max_speed = USB_SPEED_HIGH; /* support dual speed */
2315
2316         /* the "gadget" abstracts/virtualizes the controller */
2317         dev_set_name(&udc->gadget.dev, "gadget");
2318         udc->gadget.dev.parent = &dev->dev;
2319         udc->gadget.dev.dma_mask = dev->dev.dma_mask;
2320         udc->gadget.dev.release = gadget_release;
2321         udc->gadget.name = driver_name;         /* gadget name */
2322
2323         retval = device_register(&udc->gadget.dev);
2324         if (retval)
2325                 goto err_free_irq;
2326
2327         eps_init(udc);
2328
2329         /* VBUS detect: we can disable/enable clock on demand.*/
2330         if (udc->transceiver)
2331                 udc->clock_gating = 1;
2332         else if (pdata->vbus) {
2333                 udc->clock_gating = 1;
2334                 retval = request_threaded_irq(pdata->vbus->irq, NULL,
2335                                 mv_udc_vbus_irq, IRQF_ONESHOT, "vbus", udc);
2336                 if (retval) {
2337                         dev_info(&dev->dev,
2338                                 "Can not request irq for VBUS, "
2339                                 "disable clock gating\n");
2340                         udc->clock_gating = 0;
2341                 }
2342
2343                 udc->qwork = create_singlethread_workqueue("mv_udc_queue");
2344                 if (!udc->qwork) {
2345                         dev_err(&dev->dev, "cannot create workqueue\n");
2346                         retval = -ENOMEM;
2347                         goto err_unregister;
2348                 }
2349
2350                 INIT_WORK(&udc->vbus_work, mv_udc_vbus_work);
2351         }
2352
2353         /*
2354          * When clock gating is supported, we can disable clk and phy.
2355          * If not, it means that VBUS detection is not supported, we
2356          * have to enable vbus active all the time to let controller work.
2357          */
2358         if (udc->clock_gating)
2359                 mv_udc_disable_internal(udc);
2360         else
2361                 udc->vbus_active = 1;
2362
2363         retval = usb_add_gadget_udc(&dev->dev, &udc->gadget);
2364         if (retval)
2365                 goto err_unregister;
2366
2367         dev_info(&dev->dev, "successful probe UDC device %s clock gating.\n",
2368                 udc->clock_gating ? "with" : "without");
2369
2370         return 0;
2371
2372 err_unregister:
2373         if (udc->pdata && udc->pdata->vbus
2374                 && udc->clock_gating && udc->transceiver == NULL)
2375                 free_irq(pdata->vbus->irq, &dev->dev);
2376         device_unregister(&udc->gadget.dev);
2377 err_free_irq:
2378         free_irq(udc->irq, &dev->dev);
2379 err_free_status_req:
2380         kfree(udc->status_req->req.buf);
2381         kfree(udc->status_req);
2382 err_free_eps:
2383         kfree(udc->eps);
2384 err_destroy_dma:
2385         dma_pool_destroy(udc->dtd_pool);
2386 err_free_dma:
2387         dma_free_coherent(&dev->dev, udc->ep_dqh_size,
2388                         udc->ep_dqh, udc->ep_dqh_dma);
2389 err_disable_clock:
2390         mv_udc_disable_internal(udc);
2391 err_iounmap_phyreg:
2392         iounmap(udc->phy_regs);
2393 err_iounmap_capreg:
2394         iounmap(udc->cap_regs);
2395 err_put_clk:
2396         for (clk_i--; clk_i >= 0; clk_i--)
2397                 clk_put(udc->clk[clk_i]);
2398         the_controller = NULL;
2399         kfree(udc);
2400         return retval;
2401 }
2402
2403 #ifdef CONFIG_PM
2404 static int mv_udc_suspend(struct device *_dev)
2405 {
2406         struct mv_udc *udc = the_controller;
2407
2408         /* if OTG is enabled, the following will be done in OTG driver*/
2409         if (udc->transceiver)
2410                 return 0;
2411
2412         if (udc->pdata->vbus && udc->pdata->vbus->poll)
2413                 if (udc->pdata->vbus->poll() == VBUS_HIGH) {
2414                         dev_info(&udc->dev->dev, "USB cable is connected!\n");
2415                         return -EAGAIN;
2416                 }
2417
2418         /*
2419          * only cable is unplugged, udc can suspend.
2420          * So do not care about clock_gating == 1.
2421          */
2422         if (!udc->clock_gating) {
2423                 udc_stop(udc);
2424
2425                 spin_lock_irq(&udc->lock);
2426                 /* stop all usb activities */
2427                 stop_activity(udc, udc->driver);
2428                 spin_unlock_irq(&udc->lock);
2429
2430                 mv_udc_disable_internal(udc);
2431         }
2432
2433         return 0;
2434 }
2435
2436 static int mv_udc_resume(struct device *_dev)
2437 {
2438         struct mv_udc *udc = the_controller;
2439         int retval;
2440
2441         /* if OTG is enabled, the following will be done in OTG driver*/
2442         if (udc->transceiver)
2443                 return 0;
2444
2445         if (!udc->clock_gating) {
2446                 retval = mv_udc_enable_internal(udc);
2447                 if (retval)
2448                         return retval;
2449
2450                 if (udc->driver && udc->softconnect) {
2451                         udc_reset(udc);
2452                         ep0_reset(udc);
2453                         udc_start(udc);
2454                 }
2455         }
2456
2457         return 0;
2458 }
2459
2460 static const struct dev_pm_ops mv_udc_pm_ops = {
2461         .suspend        = mv_udc_suspend,
2462         .resume         = mv_udc_resume,
2463 };
2464 #endif
2465
2466 static void mv_udc_shutdown(struct platform_device *dev)
2467 {
2468         struct mv_udc *udc = the_controller;
2469         u32 mode;
2470
2471         /* reset controller mode to IDLE */
2472         mode = readl(&udc->op_regs->usbmode);
2473         mode &= ~3;
2474         writel(mode, &udc->op_regs->usbmode);
2475 }
2476
2477 static struct platform_driver udc_driver = {
2478         .probe          = mv_udc_probe,
2479         .remove         = __exit_p(mv_udc_remove),
2480         .shutdown       = mv_udc_shutdown,
2481         .driver         = {
2482                 .owner  = THIS_MODULE,
2483                 .name   = "mv-udc",
2484 #ifdef CONFIG_PM
2485                 .pm     = &mv_udc_pm_ops,
2486 #endif
2487         },
2488 };
2489
2490 module_platform_driver(udc_driver);
2491 MODULE_ALIAS("platform:mv-udc");
2492 MODULE_DESCRIPTION(DRIVER_DESC);
2493 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2494 MODULE_VERSION(DRIVER_VERSION);
2495 MODULE_LICENSE("GPL");