2 * linux/include/asm-arm/hardware/SA-1111.h
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
6 * This file contains definitions for the SA-1111 Companion Chip.
7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
9 * Macro that calculates real address for registers in the SA-1111
12 #ifndef _ASM_ARCH_SA1111
13 #define _ASM_ARCH_SA1111
15 #include <asm/arch/bitfield.h>
18 * The SA1111 is always located at virtual 0xf4000000, and is always
22 #define SA1111_VBASE 0xf4000000
24 /* Don't use these! */
25 #define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
26 #define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
29 #define _SA1111(x) ((x) + sa1111->resource.start)
33 * 26 bits of the SA-1110 address bus are available to the SA-1111.
34 * Use these when feeding target addresses to the DMA engines.
37 #define SA1111_ADDR_WIDTH (26)
38 #define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
39 #define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
42 * Don't ask the (SAC) DMA engines to move less than this amount.
45 #define SA1111_SAC_DMA_MIN_XFER (0x800)
48 * SA1111 register definitions.
50 #define __CCREG(x) __REGP(SA1111_VBASE + (x))
52 #define sa1111_writel(val,addr) ({ *(volatile unsigned int *)(addr) = (val); })
53 #define sa1111_readl(addr) (*(volatile unsigned int *)(addr))
56 * System Bus Interface (SBI)
59 * SKCR Control Register
60 * SMCR Shared Memory Controller Register
63 #define SA1111_SKCR 0x0000
64 #define SA1111_SMCR 0x0004
65 #define SA1111_SKID 0x0008
67 #define SKCR_PLL_BYPASS (1<<0)
68 #define SKCR_RCLKEN (1<<1)
69 #define SKCR_SLEEP (1<<2)
70 #define SKCR_DOZE (1<<3)
71 #define SKCR_VCO_OFF (1<<4)
72 #define SKCR_SCANTSTEN (1<<5)
73 #define SKCR_CLKTSTEN (1<<6)
74 #define SKCR_RDYEN (1<<7)
75 #define SKCR_SELAC (1<<8)
76 #define SKCR_OPPC (1<<9)
77 #define SKCR_PLLTSTEN (1<<10)
78 #define SKCR_USBIOTSTEN (1<<11)
80 * Don't believe the specs! Take them, throw them outside. Leave them
81 * there for a week. Spit on them. Walk on them. Stamp on them.
82 * Pour gasoline over them and finally burn them. Now think about coding.
83 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
84 * - The Feb 2001 errata (278260-010) says that the previous errata
85 * (278260-009) is wrong, and its bit actually 12, fixed in spec
87 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
88 * - Reality is bit 13, 1 to enable.
91 #define SKCR_OE_EN (1<<13)
93 #define SMCR_DTIM (1<<0)
94 #define SMCR_MBGE (1<<1)
95 #define SMCR_DRAC_0 (1<<2)
96 #define SMCR_DRAC_1 (1<<3)
97 #define SMCR_DRAC_2 (1<<4)
98 #define SMCR_DRAC Fld(3, 2)
99 #define SMCR_CLAT (1<<5)
101 #define SKID_SIREV_MASK (0x000000f0)
102 #define SKID_MTREV_MASK (0x0000000f)
103 #define SKID_ID_MASK (0xffffff00)
104 #define SKID_SA1111_ID (0x690cc200)
110 * SKPCR Power Control Register
111 * SKCDR Clock Divider Register
112 * SKAUD Audio Clock Divider Register
113 * SKPMC PS/2 Mouse Clock Divider Register
114 * SKPTC PS/2 Track Pad Clock Divider Register
115 * SKPEN0 PWM0 Enable Register
116 * SKPWM0 PWM0 Clock Register
117 * SKPEN1 PWM1 Enable Register
118 * SKPWM1 PWM1 Clock Register
120 #define SA1111_SKPCR 0x0200
121 #define SA1111_SKCDR 0x0204
122 #define SA1111_SKAUD 0x0208
123 #define SA1111_SKPMC 0x020c
124 #define SA1111_SKPTC 0x0210
125 #define SA1111_SKPEN0 0x0214
126 #define SA1111_SKPWM0 0x0218
127 #define SA1111_SKPEN1 0x021c
128 #define SA1111_SKPWM1 0x0220
130 #define SKPCR_UCLKEN (1<<0)
131 #define SKPCR_ACCLKEN (1<<1)
132 #define SKPCR_I2SCLKEN (1<<2)
133 #define SKPCR_L3CLKEN (1<<3)
134 #define SKPCR_SCLKEN (1<<4)
135 #define SKPCR_PMCLKEN (1<<5)
136 #define SKPCR_PTCLKEN (1<<6)
137 #define SKPCR_DCLKEN (1<<7)
138 #define SKPCR_PWMCLKEN (1<<8)
141 * USB Host controller
143 #define SA1111_USB 0x0400
146 * Offsets from SA1111_USB_BASE
148 #define SA1111_USB_STATUS 0x0118
149 #define SA1111_USB_RESET 0x011c
150 #define SA1111_USB_IRQTEST 0x0120
152 #define USB_RESET_FORCEIFRESET (1 << 0)
153 #define USB_RESET_FORCEHCRESET (1 << 1)
154 #define USB_RESET_CLKGENRESET (1 << 2)
155 #define USB_RESET_SIMSCALEDOWN (1 << 3)
156 #define USB_RESET_USBINTTEST (1 << 4)
157 #define USB_RESET_SLEEPSTBYEN (1 << 5)
158 #define USB_RESET_PWRSENSELOW (1 << 6)
159 #define USB_RESET_PWRCTRLLOW (1 << 7)
161 #define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
162 #define USB_STATUS_IRQHCIBUFFACC (1 << 8)
163 #define USB_STATUS_NIRQHCIM (1 << 9)
164 #define USB_STATUS_NHCIMFCLR (1 << 10)
165 #define USB_STATUS_USBPWRSENSE (1 << 11)
168 * Serial Audio Controller
171 * SACR0 Serial Audio Common Control Register
172 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
173 * SACR2 Serial Audio AC-link Control Register
174 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
175 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
176 * SASCR Serial Audio Status Clear Register
177 * L3_CAR L3 Control Bus Address Register
178 * L3_CDR L3 Control Bus Data Register
179 * ACCAR AC-link Command Address Register
180 * ACCDR AC-link Command Data Register
181 * ACSAR AC-link Status Address Register
182 * ACSDR AC-link Status Data Register
183 * SADTCS Serial Audio DMA Transmit Control/Status Register
184 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
185 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
186 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
187 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
188 * SADRCS Serial Audio DMA Receive Control/Status Register
189 * SADRSA Serial Audio DMA Receive Buffer Start Address A
190 * SADRCA Serial Audio DMA Receive Buffer Count Register A
191 * SADRSB Serial Audio DMA Receive Buffer Start Address B
192 * SADRCB Serial Audio DMA Receive Buffer Count Register B
193 * SAITR Serial Audio Interrupt Test Register
194 * SADR Serial Audio Data Register (16 x 32-bit)
197 #define _SACR0 _SA1111( 0x0600 )
198 #define _SACR1 _SA1111( 0x0604 )
199 #define _SACR2 _SA1111( 0x0608 )
200 #define _SASR0 _SA1111( 0x060c )
201 #define _SASR1 _SA1111( 0x0610 )
202 #define _SASCR _SA1111( 0x0618 )
203 #define _L3_CAR _SA1111( 0x061c )
204 #define _L3_CDR _SA1111( 0x0620 )
205 #define _ACCAR _SA1111( 0x0624 )
206 #define _ACCDR _SA1111( 0x0628 )
207 #define _ACSAR _SA1111( 0x062c )
208 #define _ACSDR _SA1111( 0x0630 )
209 #define _SADTCS _SA1111( 0x0634 )
210 #define _SADTSA _SA1111( 0x0638 )
211 #define _SADTCA _SA1111( 0x063c )
212 #define _SADTSB _SA1111( 0x0640 )
213 #define _SADTCB _SA1111( 0x0644 )
214 #define _SADRCS _SA1111( 0x0648 )
215 #define _SADRSA _SA1111( 0x064c )
216 #define _SADRCA _SA1111( 0x0650 )
217 #define _SADRSB _SA1111( 0x0654 )
218 #define _SADRCB _SA1111( 0x0658 )
219 #define _SAITR _SA1111( 0x065c )
220 #define _SADR _SA1111( 0x0680 )
224 #define SACR0 __CCREG(0x0600)
225 #define SACR1 __CCREG(0x0604)
226 #define SACR2 __CCREG(0x0608)
227 #define SASR0 __CCREG(0x060c)
228 #define SASR1 __CCREG(0x0610)
229 #define SASCR __CCREG(0x0618)
230 #define L3_CAR __CCREG(0x061c)
231 #define L3_CDR __CCREG(0x0620)
232 #define ACCAR __CCREG(0x0624)
233 #define ACCDR __CCREG(0x0628)
234 #define ACSAR __CCREG(0x062c)
235 #define ACSDR __CCREG(0x0630)
236 #define SADTCS __CCREG(0x0634)
237 #define SADTSA __CCREG(0x0638)
238 #define SADTCA __CCREG(0x063c)
239 #define SADTSB __CCREG(0x0640)
240 #define SADTCB __CCREG(0x0644)
241 #define SADRCS __CCREG(0x0648)
242 #define SADRSA __CCREG(0x064c)
243 #define SADRCA __CCREG(0x0650)
244 #define SADRSB __CCREG(0x0654)
245 #define SADRCB __CCREG(0x0658)
246 #define SAITR __CCREG(0x065c)
247 #define SADR __CCREG(0x0680)
249 #endif /* LANGUAGE == C */
251 #define SACR0_ENB (1<<0)
252 #define SACR0_BCKD (1<<2)
253 #define SACR0_RST (1<<3)
255 #define SACR1_AMSL (1<<0)
256 #define SACR1_L3EN (1<<1)
257 #define SACR1_L3MB (1<<2)
258 #define SACR1_DREC (1<<3)
259 #define SACR1_DRPL (1<<4)
260 #define SACR1_ENLBF (1<<5)
262 #define SACR2_TS3V (1<<0)
263 #define SACR2_TS4V (1<<1)
264 #define SACR2_WKUP (1<<2)
265 #define SACR2_DREC (1<<3)
266 #define SACR2_DRPL (1<<4)
267 #define SACR2_ENLBF (1<<5)
268 #define SACR2_RESET (1<<6)
270 #define SASR0_TNF (1<<0)
271 #define SASR0_RNE (1<<1)
272 #define SASR0_BSY (1<<2)
273 #define SASR0_TFS (1<<3)
274 #define SASR0_RFS (1<<4)
275 #define SASR0_TUR (1<<5)
276 #define SASR0_ROR (1<<6)
277 #define SASR0_L3WD (1<<16)
278 #define SASR0_L3RD (1<<17)
280 #define SASR1_TNF (1<<0)
281 #define SASR1_RNE (1<<1)
282 #define SASR1_BSY (1<<2)
283 #define SASR1_TFS (1<<3)
284 #define SASR1_RFS (1<<4)
285 #define SASR1_TUR (1<<5)
286 #define SASR1_ROR (1<<6)
287 #define SASR1_CADT (1<<16)
288 #define SASR1_SADR (1<<17)
289 #define SASR1_RSTO (1<<18)
290 #define SASR1_CLPM (1<<19)
291 #define SASR1_CRDY (1<<20)
292 #define SASR1_RS3V (1<<21)
293 #define SASR1_RS4V (1<<22)
295 #define SASCR_TUR (1<<5)
296 #define SASCR_ROR (1<<6)
297 #define SASCR_DTS (1<<16)
298 #define SASCR_RDD (1<<17)
299 #define SASCR_STO (1<<18)
301 #define SADTCS_TDEN (1<<0)
302 #define SADTCS_TDIE (1<<1)
303 #define SADTCS_TDBDA (1<<3)
304 #define SADTCS_TDSTA (1<<4)
305 #define SADTCS_TDBDB (1<<5)
306 #define SADTCS_TDSTB (1<<6)
307 #define SADTCS_TBIU (1<<7)
309 #define SADRCS_RDEN (1<<0)
310 #define SADRCS_RDIE (1<<1)
311 #define SADRCS_RDBDA (1<<3)
312 #define SADRCS_RDSTA (1<<4)
313 #define SADRCS_RDBDB (1<<5)
314 #define SADRCS_RDSTB (1<<6)
315 #define SADRCS_RBIU (1<<7)
317 #define SAD_CS_DEN (1<<0)
318 #define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
319 #define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
320 #define SAD_CS_DSTA (1<<4)
321 #define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
322 #define SAD_CS_DSTB (1<<6)
323 #define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
325 #define SAITR_TFS (1<<0)
326 #define SAITR_RFS (1<<1)
327 #define SAITR_TUR (1<<2)
328 #define SAITR_ROR (1<<3)
329 #define SAITR_CADT (1<<4)
330 #define SAITR_SADR (1<<5)
331 #define SAITR_RSTO (1<<6)
332 #define SAITR_TDBDA (1<<8)
333 #define SAITR_TDBDB (1<<9)
334 #define SAITR_RDBDA (1<<10)
335 #define SAITR_RDBDB (1<<11)
338 * General-Purpose I/O Interface
341 * PA_DDR GPIO Block A Data Direction
342 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
343 * PA_SDR GPIO Block A Sleep Direction
344 * PA_SSR GPIO Block A Sleep State
345 * PB_DDR GPIO Block B Data Direction
346 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
347 * PB_SDR GPIO Block B Sleep Direction
348 * PB_SSR GPIO Block B Sleep State
349 * PC_DDR GPIO Block C Data Direction
350 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
351 * PC_SDR GPIO Block C Sleep Direction
352 * PC_SSR GPIO Block C Sleep State
355 #define _PA_DDR _SA1111( 0x1000 )
356 #define _PA_DRR _SA1111( 0x1004 )
357 #define _PA_DWR _SA1111( 0x1004 )
358 #define _PA_SDR _SA1111( 0x1008 )
359 #define _PA_SSR _SA1111( 0x100c )
360 #define _PB_DDR _SA1111( 0x1010 )
361 #define _PB_DRR _SA1111( 0x1014 )
362 #define _PB_DWR _SA1111( 0x1014 )
363 #define _PB_SDR _SA1111( 0x1018 )
364 #define _PB_SSR _SA1111( 0x101c )
365 #define _PC_DDR _SA1111( 0x1020 )
366 #define _PC_DRR _SA1111( 0x1024 )
367 #define _PC_DWR _SA1111( 0x1024 )
368 #define _PC_SDR _SA1111( 0x1028 )
369 #define _PC_SSR _SA1111( 0x102c )
373 #define PA_DDR __CCREG(0x1000)
374 #define PA_DRR __CCREG(0x1004)
375 #define PA_DWR __CCREG(0x1004)
376 #define PA_SDR __CCREG(0x1008)
377 #define PA_SSR __CCREG(0x100c)
378 #define PB_DDR __CCREG(0x1010)
379 #define PB_DRR __CCREG(0x1014)
380 #define PB_DWR __CCREG(0x1014)
381 #define PB_SDR __CCREG(0x1018)
382 #define PB_SSR __CCREG(0x101c)
383 #define PC_DDR __CCREG(0x1020)
384 #define PC_DRR __CCREG(0x1024)
385 #define PC_DWR __CCREG(0x1024)
386 #define PC_SDR __CCREG(0x1028)
387 #define PC_SSR __CCREG(0x102c)
389 #endif /* LANGUAGE == C */
392 * Interrupt Controller
395 * INTTEST0 Test register 0
396 * INTTEST1 Test register 1
397 * INTEN0 Interrupt Enable register 0
398 * INTEN1 Interrupt Enable register 1
399 * INTPOL0 Interrupt Polarity selection 0
400 * INTPOL1 Interrupt Polarity selection 1
401 * INTTSTSEL Interrupt source selection
402 * INTSTATCLR0 Interrupt Status/Clear 0
403 * INTSTATCLR1 Interrupt Status/Clear 1
404 * INTSET0 Interrupt source set 0
405 * INTSET1 Interrupt source set 1
406 * WAKE_EN0 Wake-up source enable 0
407 * WAKE_EN1 Wake-up source enable 1
408 * WAKE_POL0 Wake-up polarity selection 0
409 * WAKE_POL1 Wake-up polarity selection 1
411 #define SA1111_INTC 0x1600
414 * These are offsets from the above base.
416 #define SA1111_INTTEST0 0x0000
417 #define SA1111_INTTEST1 0x0004
418 #define SA1111_INTEN0 0x0008
419 #define SA1111_INTEN1 0x000c
420 #define SA1111_INTPOL0 0x0010
421 #define SA1111_INTPOL1 0x0014
422 #define SA1111_INTTSTSEL 0x0018
423 #define SA1111_INTSTATCLR0 0x001c
424 #define SA1111_INTSTATCLR1 0x0020
425 #define SA1111_INTSET0 0x0024
426 #define SA1111_INTSET1 0x0028
427 #define SA1111_WAKEEN0 0x002c
428 #define SA1111_WAKEEN1 0x0030
429 #define SA1111_WAKEPOL0 0x0034
430 #define SA1111_WAKEPOL1 0x0038
432 #define INTTEST0 __CCREG(SA1111_INTC + SA1111_INTTEST0)
433 #define INTTEST1 __CCREG(SA1111_INTC + SA1111_INTTEST1)
434 #define INTEN0 __CCREG(SA1111_INTC + SA1111_INTEN0)
435 #define INTEN1 __CCREG(SA1111_INTC + SA1111_INTEN1)
436 #define INTPOL0 __CCREG(SA1111_INTC + SA1111_INTPOL0)
437 #define INTPOL1 __CCREG(SA1111_INTC + SA1111_INTPOL1)
438 #define INTTSTSEL __CCREG(SA1111_INTC + SA1111_INTTSTSEL)
439 #define INTSTATCLR0 __CCREG(SA1111_INTC + SA1111_INTSTATCLR0)
440 #define INTSTATCLR1 __CCREG(SA1111_INTC + SA1111_INTSTATCLR1)
441 #define INTSET0 __CCREG(SA1111_INTC + SA1111_INTSET0)
442 #define INTSET1 __CCREG(SA1111_INTC + SA1111_INTSET1)
443 #define WAKE_EN0 __CCREG(SA1111_INTC + SA1111_WAKEEN0)
444 #define WAKE_EN1 __CCREG(SA1111_INTC + SA1111_WAKEEN1)
445 #define WAKE_POL0 __CCREG(SA1111_INTC + SA1111_WAKEPOL0)
446 #define WAKE_POL1 __CCREG(SA1111_INTC + SA1111_WAKEPOL1)
449 * PS/2 Trackpad and Mouse Interfaces
452 * PS2CR Control Register
453 * PS2STAT Status Register
454 * PS2DATA Transmit/Receive Data register
455 * PS2CLKDIV Clock Division Register
456 * PS2PRECNT Clock Precount Register
457 * PS2TEST1 Test register 1
458 * PS2TEST2 Test register 2
459 * PS2TEST3 Test register 3
460 * PS2TEST4 Test register 4
463 #define SA1111_KBD 0x0a00
464 #define SA1111_MSE 0x0c00
467 * These are offsets from the above bases.
469 #define SA1111_PS2CR 0x0000
470 #define SA1111_PS2STAT 0x0004
471 #define SA1111_PS2DATA 0x0008
472 #define SA1111_PS2CLKDIV 0x000c
473 #define SA1111_PS2PRECNT 0x0010
475 #define PS2CR_ENA 0x08
476 #define PS2CR_FKD 0x02
477 #define PS2CR_FKC 0x01
479 #define PS2STAT_STP 0x0100
480 #define PS2STAT_TXE 0x0080
481 #define PS2STAT_TXB 0x0040
482 #define PS2STAT_RXF 0x0020
483 #define PS2STAT_RXB 0x0010
484 #define PS2STAT_ENA 0x0008
485 #define PS2STAT_RXP 0x0004
486 #define PS2STAT_KBD 0x0002
487 #define PS2STAT_KBC 0x0001
493 * PCSR Status Register
494 * PCCR Control Register
495 * PCSSR Sleep State Register
498 #define SA1111_PCMCIA 0x1600
501 * These are offsets from the above base.
503 #define SA1111_PCCR 0x0000
504 #define SA1111_PCSSR 0x0004
505 #define SA1111_PCSR 0x0008
507 #define PCSR_S0_READY (1<<0)
508 #define PCSR_S1_READY (1<<1)
509 #define PCSR_S0_DETECT (1<<2)
510 #define PCSR_S1_DETECT (1<<3)
511 #define PCSR_S0_VS1 (1<<4)
512 #define PCSR_S0_VS2 (1<<5)
513 #define PCSR_S1_VS1 (1<<6)
514 #define PCSR_S1_VS2 (1<<7)
515 #define PCSR_S0_WP (1<<8)
516 #define PCSR_S1_WP (1<<9)
517 #define PCSR_S0_BVD1 (1<<10)
518 #define PCSR_S0_BVD2 (1<<11)
519 #define PCSR_S1_BVD1 (1<<12)
520 #define PCSR_S1_BVD2 (1<<13)
522 #define PCCR_S0_RST (1<<0)
523 #define PCCR_S1_RST (1<<1)
524 #define PCCR_S0_FLT (1<<2)
525 #define PCCR_S1_FLT (1<<3)
526 #define PCCR_S0_PWAITEN (1<<4)
527 #define PCCR_S1_PWAITEN (1<<5)
528 #define PCCR_S0_PSE (1<<6)
529 #define PCCR_S1_PSE (1<<7)
531 #define PCSSR_S0_SLEEP (1<<0)
532 #define PCSSR_S1_SLEEP (1<<1)
537 extern struct bus_type sa1111_bus_type;
539 #define SA1111_DEVID_SBI 0
540 #define SA1111_DEVID_SK 1
541 #define SA1111_DEVID_USB 2
542 #define SA1111_DEVID_SAC 3
543 #define SA1111_DEVID_SSP 4
544 #define SA1111_DEVID_PS2 5
545 #define SA1111_DEVID_GPIO 6
546 #define SA1111_DEVID_INT 7
547 #define SA1111_DEVID_PCMCIA 8
554 unsigned int skpcr_mask;
559 #define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
561 struct sa1111_driver {
562 struct device_driver drv;
566 #define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
568 #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
571 * Probe for a SA1111 chip.
573 extern int sa1111_init(unsigned long phys, unsigned int irq);
576 * These frob the SKPCR register.
578 void sa1111_enable_device(struct sa1111_dev *);
579 void sa1111_disable_device(struct sa1111_dev *);
581 unsigned int sa1111_pll_clock(struct sa1111_dev *);
583 #define SA1111_AUDIO_ACLINK 0
584 #define SA1111_AUDIO_I2S 1
586 void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
587 int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
588 int sa1111_get_audio_rate(struct sa1111_dev *sadev);
590 int sa1111_check_dma_bug(dma_addr_t addr);
592 #endif /* _ASM_ARCH_SA1111 */