arch/arm/mach-integrator/core.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/memblock.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/termios.h>
  21 #include <linux/amba/bus.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/io.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/platform.h>
  28 #include <mach/cm.h>
  29 #include <mach/irqs.h>
  30
  31 #include <asm/leds.h>
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/time.h>
  34 #include <asm/pgtable.h>
  35
  36 static struct amba_pl010_data integrator_uart_data;
  37
  38 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
  39 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
  40 #define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
  41 #define KMI0_IRQ                { IRQ_KMIINT0 }
  42 #define KMI1_IRQ                { IRQ_KMIINT1 }
  43
  44 static AMBA_APB_DEVICE(rtc, "mb:15", 0,
  45         INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
  46
  47 static AMBA_APB_DEVICE(uart0, "mb:16", 0,
  48         INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
  49
  50 static AMBA_APB_DEVICE(uart1, "mb:17", 0,
  51         INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
  52
  53 static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
  54 static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
  55
  56 static struct amba_device *amba_devs[] __initdata = {
  57         &rtc_device,
  58         &uart0_device,
  59         &uart1_device,
  60         &kmi0_device,
  61         &kmi1_device,
  62 };
  63
  64 /*
  65  * These are fixed clocks.
  66  */
  67 static struct clk clk24mhz = {
  68         .rate   = 24000000,
  69 };
  70
  71 static struct clk uartclk = {
  72         .rate   = 14745600,
  73 };
  74
  75 static struct clk dummy_apb_pclk;
  76
  77 static struct clk_lookup lookups[] = {
  78         {       /* Bus clock */
  79                 .con_id         = "apb_pclk",
  80                 .clk            = &dummy_apb_pclk,
  81         }, {
  82                 /* Integrator/AP timer frequency */
  83                 .dev_id         = "ap_timer",
  84                 .clk            = &clk24mhz,
  85         }, {    /* UART0 */
  86                 .dev_id         = "mb:16",
  87                 .clk            = &uartclk,
  88         }, {    /* UART1 */
  89                 .dev_id         = "mb:17",
  90                 .clk            = &uartclk,
  91         }, {    /* KMI0 */
  92                 .dev_id         = "mb:18",
  93                 .clk            = &clk24mhz,
  94         }, {    /* KMI1 */
  95                 .dev_id         = "mb:19",
  96                 .clk            = &clk24mhz,
  97         }, {    /* MMCI - IntegratorCP */
  98                 .dev_id         = "mb:1c",
  99                 .clk            = &uartclk,
 100         }
 101 };
 102
 103 void __init integrator_init_early(void)
 104 {
 105         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 106 }
 107
 108 static int __init integrator_init(void)
 109 {
 110         int i;
 111
 112         /*
 113          * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
 114          * hard-code them. The Integator/CP and forward have proper cell IDs.
 115          * Else we leave them undefined to the bus driver can autoprobe them.
 116          */
 117         if (machine_is_integrator()) {
 118                 rtc_device.periphid     = 0x00041030;
 119                 uart0_device.periphid   = 0x00041010;
 120                 uart1_device.periphid   = 0x00041010;
 121                 kmi0_device.periphid    = 0x00041050;
 122                 kmi1_device.periphid    = 0x00041050;
 123         }
 124
 125         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 126                 struct amba_device *d = amba_devs[i];
 127                 amba_device_register(d, &iomem_resource);
 128         }
 129
 130         return 0;
 131 }
 132
 133 arch_initcall(integrator_init);
 134
 135 /*
 136  * On the Integrator platform, the port RTS and DTR are provided by
 137  * bits in the following SC_CTRLS register bits:
 138  *        RTS  DTR
 139  *  UART0  7    6
 140  *  UART1  5    4
 141  */
 142 #define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
 143 #define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
 144
 145 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 146 {
 147         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 148
 149         if (dev == &uart0_device) {
 150                 rts_mask = 1 << 4;
 151                 dtr_mask = 1 << 5;
 152         } else {
 153                 rts_mask = 1 << 6;
 154                 dtr_mask = 1 << 7;
 155         }
 156
 157         if (mctrl & TIOCM_RTS)
 158                 ctrlc |= rts_mask;
 159         else
 160                 ctrls |= rts_mask;
 161
 162         if (mctrl & TIOCM_DTR)
 163                 ctrlc |= dtr_mask;
 164         else
 165                 ctrls |= dtr_mask;
 166
 167         __raw_writel(ctrls, SC_CTRLS);
 168         __raw_writel(ctrlc, SC_CTRLC);
 169 }
 170
 171 static struct amba_pl010_data integrator_uart_data = {
 172         .set_mctrl = integrator_uart_set_mctrl,
 173 };
 174
 175 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 176
 177 static DEFINE_RAW_SPINLOCK(cm_lock);
 178
 179 /**
 180  * cm_control - update the CM_CTRL register.
 181  * @mask: bits to change
 182  * @set: bits to set
 183  */
 184 void cm_control(u32 mask, u32 set)
 185 {
 186         unsigned long flags;
 187         u32 val;
 188
 189         raw_spin_lock_irqsave(&cm_lock, flags);
 190         val = readl(CM_CTRL) & ~mask;
 191         writel(val | set, CM_CTRL);
 192         raw_spin_unlock_irqrestore(&cm_lock, flags);
 193 }
 194
 195 EXPORT_SYMBOL(cm_control);
 196
 197 /*
 198  * We need to stop things allocating the low memory; ideally we need a
 199  * better implementation of GFP_DMA which does not assume that DMA-able
 200  * memory starts at zero.
 201  */
 202 void __init integrator_reserve(void)
 203 {
 204         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 205 }
 206
 207 /*
 208  * To reset, we hit the on-board reset register in the system FPGA
 209  */
 210 void integrator_restart(char mode, const char *cmd)
 211 {
 212         cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 213 }