2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <asm/setup.h>
28 const char *pci_power_names[] = {
29 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
31 EXPORT_SYMBOL_GPL(pci_power_names);
33 int isa_dma_bridge_buggy;
34 EXPORT_SYMBOL(isa_dma_bridge_buggy);
37 EXPORT_SYMBOL(pci_pci_problems);
39 unsigned int pci_pm_d3_delay;
41 static void pci_pme_list_scan(struct work_struct *work);
43 static LIST_HEAD(pci_pme_list);
44 static DEFINE_MUTEX(pci_pme_list_mutex);
45 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
47 struct pci_pme_device {
48 struct list_head list;
52 #define PME_TIMEOUT 1000 /* How long between PME checks */
54 static void pci_dev_d3_sleep(struct pci_dev *dev)
56 unsigned int delay = dev->d3_delay;
58 if (delay < pci_pm_d3_delay)
59 delay = pci_pm_d3_delay;
64 #ifdef CONFIG_PCI_DOMAINS
65 int pci_domains_supported = 1;
68 #define DEFAULT_CARDBUS_IO_SIZE (256)
69 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
70 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
71 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
72 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
74 #define DEFAULT_HOTPLUG_IO_SIZE (256)
75 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
76 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
77 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
78 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
80 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
83 * The default CLS is used if arch didn't set CLS explicitly and not
84 * all pci devices agree on the same value. Arch can override either
85 * the dfl or actual value as it sees fit. Don't forget this is
86 * measured in 32-bit words, not bytes.
88 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
89 u8 pci_cache_line_size;
92 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
93 * @bus: pointer to PCI bus structure to search
95 * Given a PCI bus, returns the highest PCI bus number present in the set
96 * including the given PCI bus and its list of child PCI buses.
98 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
100 struct list_head *tmp;
101 unsigned char max, n;
103 max = bus->subordinate;
104 list_for_each(tmp, &bus->children) {
105 n = pci_bus_max_busnr(pci_bus_b(tmp));
111 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
113 #ifdef CONFIG_HAS_IOMEM
114 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
117 * Make sure the BAR is actually a memory resource, not an IO resource
119 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
123 return ioremap_nocache(pci_resource_start(pdev, bar),
124 pci_resource_len(pdev, bar));
126 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
131 * pci_max_busnr - returns maximum PCI bus number
133 * Returns the highest PCI bus number present in the system global list of
136 unsigned char __devinit
139 struct pci_bus *bus = NULL;
140 unsigned char max, n;
143 while ((bus = pci_find_next_bus(bus)) != NULL) {
144 n = pci_bus_max_busnr(bus);
153 #define PCI_FIND_CAP_TTL 48
155 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
156 u8 pos, int cap, int *ttl)
161 pci_bus_read_config_byte(bus, devfn, pos, &pos);
165 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
171 pos += PCI_CAP_LIST_NEXT;
176 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
179 int ttl = PCI_FIND_CAP_TTL;
181 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
184 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
186 return __pci_find_next_cap(dev->bus, dev->devfn,
187 pos + PCI_CAP_LIST_NEXT, cap);
189 EXPORT_SYMBOL_GPL(pci_find_next_capability);
191 static int __pci_bus_find_cap_start(struct pci_bus *bus,
192 unsigned int devfn, u8 hdr_type)
196 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
197 if (!(status & PCI_STATUS_CAP_LIST))
201 case PCI_HEADER_TYPE_NORMAL:
202 case PCI_HEADER_TYPE_BRIDGE:
203 return PCI_CAPABILITY_LIST;
204 case PCI_HEADER_TYPE_CARDBUS:
205 return PCI_CB_CAPABILITY_LIST;
214 * pci_find_capability - query for devices' capabilities
215 * @dev: PCI device to query
216 * @cap: capability code
218 * Tell if a device supports a given PCI capability.
219 * Returns the address of the requested capability structure within the
220 * device's PCI configuration space or 0 in case the device does not
221 * support it. Possible values for @cap:
223 * %PCI_CAP_ID_PM Power Management
224 * %PCI_CAP_ID_AGP Accelerated Graphics Port
225 * %PCI_CAP_ID_VPD Vital Product Data
226 * %PCI_CAP_ID_SLOTID Slot Identification
227 * %PCI_CAP_ID_MSI Message Signalled Interrupts
228 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
229 * %PCI_CAP_ID_PCIX PCI-X
230 * %PCI_CAP_ID_EXP PCI Express
232 int pci_find_capability(struct pci_dev *dev, int cap)
236 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
238 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
244 * pci_bus_find_capability - query for devices' capabilities
245 * @bus: the PCI bus to query
246 * @devfn: PCI device to query
247 * @cap: capability code
249 * Like pci_find_capability() but works for pci devices that do not have a
250 * pci_dev structure set up yet.
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
256 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
261 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
263 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
265 pos = __pci_find_next_cap(bus, devfn, pos, cap);
271 * pci_find_ext_capability - Find an extended capability
272 * @dev: PCI device to query
273 * @cap: capability code
275 * Returns the address of the requested extended capability structure
276 * within the device's PCI configuration space or 0 if the device does
277 * not support it. Possible values for @cap:
279 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
280 * %PCI_EXT_CAP_ID_VC Virtual Channel
281 * %PCI_EXT_CAP_ID_DSN Device Serial Number
282 * %PCI_EXT_CAP_ID_PWR Power Budgeting
284 int pci_find_ext_capability(struct pci_dev *dev, int cap)
288 int pos = PCI_CFG_SPACE_SIZE;
290 /* minimum 8 bytes per capability */
291 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
293 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
296 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
300 * If we have no capabilities, this is indicated by cap ID,
301 * cap version and next pointer all being 0.
307 if (PCI_EXT_CAP_ID(header) == cap)
310 pos = PCI_EXT_CAP_NEXT(header);
311 if (pos < PCI_CFG_SPACE_SIZE)
314 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
320 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
323 * pci_bus_find_ext_capability - find an extended capability
324 * @bus: the PCI bus to query
325 * @devfn: PCI device to query
326 * @cap: capability code
328 * Like pci_find_ext_capability() but works for pci devices that do not have a
329 * pci_dev structure set up yet.
331 * Returns the address of the requested capability structure within the
332 * device's PCI configuration space or 0 in case the device does not
335 int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
340 int pos = PCI_CFG_SPACE_SIZE;
342 /* minimum 8 bytes per capability */
343 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
345 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
347 if (header == 0xffffffff || header == 0)
351 if (PCI_EXT_CAP_ID(header) == cap)
354 pos = PCI_EXT_CAP_NEXT(header);
355 if (pos < PCI_CFG_SPACE_SIZE)
358 if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
365 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
367 int rc, ttl = PCI_FIND_CAP_TTL;
370 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
371 mask = HT_3BIT_CAP_MASK;
373 mask = HT_5BIT_CAP_MASK;
375 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
376 PCI_CAP_ID_HT, &ttl);
378 rc = pci_read_config_byte(dev, pos + 3, &cap);
379 if (rc != PCIBIOS_SUCCESSFUL)
382 if ((cap & mask) == ht_cap)
385 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
386 pos + PCI_CAP_LIST_NEXT,
387 PCI_CAP_ID_HT, &ttl);
393 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
394 * @dev: PCI device to query
395 * @pos: Position from which to continue searching
396 * @ht_cap: Hypertransport capability code
398 * To be used in conjunction with pci_find_ht_capability() to search for
399 * all capabilities matching @ht_cap. @pos should always be a value returned
400 * from pci_find_ht_capability().
402 * NB. To be 100% safe against broken PCI devices, the caller should take
403 * steps to avoid an infinite loop.
405 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
407 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
409 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
412 * pci_find_ht_capability - query a device's Hypertransport capabilities
413 * @dev: PCI device to query
414 * @ht_cap: Hypertransport capability code
416 * Tell if a device supports a given Hypertransport capability.
417 * Returns an address within the device's PCI configuration space
418 * or 0 in case the device does not support the request capability.
419 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
420 * which has a Hypertransport capability matching @ht_cap.
422 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
426 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
428 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
432 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
435 * pci_find_parent_resource - return resource region of parent bus of given region
436 * @dev: PCI device structure contains resources to be searched
437 * @res: child resource record for which parent is sought
439 * For given resource region of given device, return the resource
440 * region of parent bus the given region is contained in or where
441 * it should be allocated from.
444 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
446 const struct pci_bus *bus = dev->bus;
448 struct resource *best = NULL, *r;
450 pci_bus_for_each_resource(bus, r, i) {
453 if (res->start && !(res->start >= r->start && res->end <= r->end))
454 continue; /* Not contained */
455 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
456 continue; /* Wrong type */
457 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
458 return r; /* Exact match */
459 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
460 if (r->flags & IORESOURCE_PREFETCH)
462 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
479 EXPORT_SYMBOL_GPL(pci_restore_bars);
482 pci_restore_bars(struct pci_dev *dev)
486 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
487 pci_update_resource(dev, i);
490 static struct pci_platform_pm_ops *pci_platform_pm;
492 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
494 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
495 || !ops->sleep_wake || !ops->can_wakeup)
497 pci_platform_pm = ops;
501 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
503 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
506 static inline int platform_pci_set_power_state(struct pci_dev *dev,
509 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
512 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
514 return pci_platform_pm ?
515 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
518 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
520 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
523 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
525 return pci_platform_pm ?
526 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
529 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
531 return pci_platform_pm ?
532 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
536 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
538 * @dev: PCI device to handle.
539 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
542 * -EINVAL if the requested state is invalid.
543 * -EIO if device does not support PCI PM or its PM capabilities register has a
544 * wrong version, or device doesn't support the requested state.
545 * 0 if device already is in the requested state.
546 * 0 if device's power state has been successfully changed.
548 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
551 bool need_restore = false;
553 /* Check if we're already there */
554 if (dev->current_state == state)
560 if (state < PCI_D0 || state > PCI_D3hot)
563 /* Validate current state:
564 * Can enter D0 from any state, but if we can only go deeper
565 * to sleep if we're already in a low power state
567 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
568 && dev->current_state > state) {
569 dev_err(&dev->dev, "invalid power transition "
570 "(from state %d to %d)\n", dev->current_state, state);
574 /* check if this device supports the desired state */
575 if ((state == PCI_D1 && !dev->d1_support)
576 || (state == PCI_D2 && !dev->d2_support))
579 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
581 /* If we're (effectively) in D3, force entire word to 0.
582 * This doesn't affect PME_Status, disables PME_En, and
583 * sets PowerState to 0.
585 switch (dev->current_state) {
589 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
594 case PCI_UNKNOWN: /* Boot-up */
595 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
596 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
598 /* Fall-through: force to D0 */
604 /* enter specified state */
605 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
607 /* Mandatory power management transition delays */
608 /* see PCI PM 1.1 5.6.1 table 18 */
609 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
610 pci_dev_d3_sleep(dev);
611 else if (state == PCI_D2 || dev->current_state == PCI_D2)
612 udelay(PCI_PM_D2_DELAY);
614 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
615 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
616 if (dev->current_state != state && printk_ratelimit())
617 dev_info(&dev->dev, "Refused to change power state, "
618 "currently in D%d\n", dev->current_state);
620 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
621 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
622 * from D3hot to D0 _may_ perform an internal reset, thereby
623 * going to "D0 Uninitialized" rather than "D0 Initialized".
624 * For example, at least some versions of the 3c905B and the
625 * 3c556B exhibit this behaviour.
627 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
628 * devices in a D3hot state at boot. Consequently, we need to
629 * restore at least the BARs so that the device will be
630 * accessible to its driver.
633 pci_restore_bars(dev);
636 pcie_aspm_pm_state_change(dev->bus->self);
642 * pci_update_current_state - Read PCI power state of given device from its
643 * PCI PM registers and cache it
644 * @dev: PCI device to handle.
645 * @state: State to cache in case the device doesn't have the PM capability
647 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
652 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
653 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
655 dev->current_state = state;
660 * pci_platform_power_transition - Use platform to change device power state
661 * @dev: PCI device to handle.
662 * @state: State to put the device into.
664 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
668 if (platform_pci_power_manageable(dev)) {
669 error = platform_pci_set_power_state(dev, state);
671 pci_update_current_state(dev, state);
672 /* Fall back to PCI_D0 if native PM is not supported */
674 dev->current_state = PCI_D0;
677 /* Fall back to PCI_D0 if native PM is not supported */
679 dev->current_state = PCI_D0;
686 * __pci_start_power_transition - Start power transition of a PCI device
687 * @dev: PCI device to handle.
688 * @state: State to put the device into.
690 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
693 pci_platform_power_transition(dev, PCI_D0);
697 * __pci_complete_power_transition - Complete power transition of a PCI device
698 * @dev: PCI device to handle.
699 * @state: State to put the device into.
701 * This function should not be called directly by device drivers.
703 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
705 return state >= PCI_D0 ?
706 pci_platform_power_transition(dev, state) : -EINVAL;
708 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
711 * pci_set_power_state - Set the power state of a PCI device
712 * @dev: PCI device to handle.
713 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
715 * Transition a device to a new power state, using the platform firmware and/or
716 * the device's PCI PM registers.
719 * -EINVAL if the requested state is invalid.
720 * -EIO if device does not support PCI PM or its PM capabilities register has a
721 * wrong version, or device doesn't support the requested state.
722 * 0 if device already is in the requested state.
723 * 0 if device's power state has been successfully changed.
725 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
729 /* bound the state we're entering */
730 if (state > PCI_D3hot)
732 else if (state < PCI_D0)
734 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
736 * If the device or the parent bridge do not support PCI PM,
737 * ignore the request if we're doing anything other than putting
738 * it into D0 (which would only happen on boot).
742 __pci_start_power_transition(dev, state);
744 /* This device is quirked not to be put into D3, so
745 don't put it in D3 */
746 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
749 error = pci_raw_set_power_state(dev, state);
751 if (!__pci_complete_power_transition(dev, state))
754 * When aspm_policy is "powersave" this call ensures
755 * that ASPM is configured.
757 if (!error && dev->bus->self)
758 pcie_aspm_powersave_config_link(dev->bus->self);
764 * pci_choose_state - Choose the power state of a PCI device
765 * @dev: PCI device to be suspended
766 * @state: target sleep state for the whole system. This is the value
767 * that is passed to suspend() function.
769 * Returns PCI power state suitable for given device and given system
773 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
777 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
780 ret = platform_pci_choose_state(dev);
781 if (ret != PCI_POWER_ERROR)
784 switch (state.event) {
787 case PM_EVENT_FREEZE:
788 case PM_EVENT_PRETHAW:
789 /* REVISIT both freeze and pre-thaw "should" use D0 */
790 case PM_EVENT_SUSPEND:
791 case PM_EVENT_HIBERNATE:
794 dev_info(&dev->dev, "unrecognized suspend event %d\n",
801 EXPORT_SYMBOL(pci_choose_state);
803 #define PCI_EXP_SAVE_REGS 7
805 #define pcie_cap_has_devctl(type, flags) 1
806 #define pcie_cap_has_lnkctl(type, flags) \
807 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
808 (type == PCI_EXP_TYPE_ROOT_PORT || \
809 type == PCI_EXP_TYPE_ENDPOINT || \
810 type == PCI_EXP_TYPE_LEG_END))
811 #define pcie_cap_has_sltctl(type, flags) \
812 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
813 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
814 (type == PCI_EXP_TYPE_DOWNSTREAM && \
815 (flags & PCI_EXP_FLAGS_SLOT))))
816 #define pcie_cap_has_rtctl(type, flags) \
817 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
818 (type == PCI_EXP_TYPE_ROOT_PORT || \
819 type == PCI_EXP_TYPE_RC_EC))
820 #define pcie_cap_has_devctl2(type, flags) \
821 ((flags & PCI_EXP_FLAGS_VERS) > 1)
822 #define pcie_cap_has_lnkctl2(type, flags) \
823 ((flags & PCI_EXP_FLAGS_VERS) > 1)
824 #define pcie_cap_has_sltctl2(type, flags) \
825 ((flags & PCI_EXP_FLAGS_VERS) > 1)
827 static int pci_save_pcie_state(struct pci_dev *dev)
830 struct pci_cap_saved_state *save_state;
834 pos = pci_pcie_cap(dev);
838 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
840 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
843 cap = (u16 *)&save_state->cap.data[0];
845 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
847 if (pcie_cap_has_devctl(dev->pcie_type, flags))
848 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
849 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
850 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
851 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
852 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
853 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
854 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
855 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
856 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
857 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
858 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
859 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
860 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
865 static void pci_restore_pcie_state(struct pci_dev *dev)
868 struct pci_cap_saved_state *save_state;
872 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
873 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
874 if (!save_state || pos <= 0)
876 cap = (u16 *)&save_state->cap.data[0];
878 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
880 if (pcie_cap_has_devctl(dev->pcie_type, flags))
881 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
882 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
883 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
884 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
885 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
886 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
887 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
888 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
889 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
890 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
891 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
892 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
893 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
897 static int pci_save_pcix_state(struct pci_dev *dev)
900 struct pci_cap_saved_state *save_state;
902 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
906 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
908 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
912 pci_read_config_word(dev, pos + PCI_X_CMD,
913 (u16 *)save_state->cap.data);
918 static void pci_restore_pcix_state(struct pci_dev *dev)
921 struct pci_cap_saved_state *save_state;
924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
925 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
926 if (!save_state || pos <= 0)
928 cap = (u16 *)&save_state->cap.data[0];
930 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
935 * pci_save_state - save the PCI configuration space of a device before suspending
936 * @dev: - PCI device that we're dealing with
939 pci_save_state(struct pci_dev *dev)
942 /* XXX: 100% dword access ok here? */
943 for (i = 0; i < 16; i++)
944 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
945 dev->state_saved = true;
946 if ((i = pci_save_pcie_state(dev)) != 0)
948 if ((i = pci_save_pcix_state(dev)) != 0)
954 * pci_restore_state - Restore the saved state of a PCI device
955 * @dev: - PCI device that we're dealing with
957 void pci_restore_state(struct pci_dev *dev)
962 if (!dev->state_saved)
965 /* PCI Express register must be restored first */
966 pci_restore_pcie_state(dev);
969 * The Base Address register should be programmed before the command
972 for (i = 15; i >= 0; i--) {
973 pci_read_config_dword(dev, i * 4, &val);
974 if (val != dev->saved_config_space[i]) {
975 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
976 "space at offset %#x (was %#x, writing %#x)\n",
977 i, val, (int)dev->saved_config_space[i]);
978 pci_write_config_dword(dev,i * 4,
979 dev->saved_config_space[i]);
982 pci_restore_pcix_state(dev);
983 pci_restore_msi_state(dev);
984 pci_restore_iov_state(dev);
986 dev->state_saved = false;
989 struct pci_saved_state {
990 u32 config_space[16];
991 struct pci_cap_saved_data cap[0];
995 * pci_store_saved_state - Allocate and return an opaque struct containing
996 * the device saved state.
997 * @dev: PCI device that we're dealing with
999 * Rerturn NULL if no state or error.
1001 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1003 struct pci_saved_state *state;
1004 struct pci_cap_saved_state *tmp;
1005 struct pci_cap_saved_data *cap;
1006 struct hlist_node *pos;
1009 if (!dev->state_saved)
1012 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1014 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
1015 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1017 state = kzalloc(size, GFP_KERNEL);
1021 memcpy(state->config_space, dev->saved_config_space,
1022 sizeof(state->config_space));
1025 hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
1026 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1027 memcpy(cap, &tmp->cap, len);
1028 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1030 /* Empty cap_save terminates list */
1034 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1037 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1038 * @dev: PCI device that we're dealing with
1039 * @state: Saved state returned from pci_store_saved_state()
1041 int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1043 struct pci_cap_saved_data *cap;
1045 dev->state_saved = false;
1050 memcpy(dev->saved_config_space, state->config_space,
1051 sizeof(state->config_space));
1055 struct pci_cap_saved_state *tmp;
1057 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1058 if (!tmp || tmp->cap.size != cap->size)
1061 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1062 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1063 sizeof(struct pci_cap_saved_data) + cap->size);
1066 dev->state_saved = true;
1069 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1072 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1073 * and free the memory allocated for it.
1074 * @dev: PCI device that we're dealing with
1075 * @state: Pointer to saved state returned from pci_store_saved_state()
1077 int pci_load_and_free_saved_state(struct pci_dev *dev,
1078 struct pci_saved_state **state)
1080 int ret = pci_load_saved_state(dev, *state);
1085 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1087 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1091 err = pci_set_power_state(dev, PCI_D0);
1092 if (err < 0 && err != -EIO)
1094 err = pcibios_enable_device(dev, bars);
1097 pci_fixup_device(pci_fixup_enable, dev);
1103 * pci_reenable_device - Resume abandoned device
1104 * @dev: PCI device to be resumed
1106 * Note this function is a backend of pci_default_resume and is not supposed
1107 * to be called by normal code, write proper resume handler and use it instead.
1109 int pci_reenable_device(struct pci_dev *dev)
1111 if (pci_is_enabled(dev))
1112 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1116 static int __pci_enable_device_flags(struct pci_dev *dev,
1117 resource_size_t flags)
1123 * Power state could be unknown at this point, either due to a fresh
1124 * boot or a device removal call. So get the current power state
1125 * so that things like MSI message writing will behave as expected
1126 * (e.g. if the device really is in D0 at enable time).
1130 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1131 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1134 if (atomic_add_return(1, &dev->enable_cnt) > 1)
1135 return 0; /* already enabled */
1137 /* only skip sriov related */
1138 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1139 if (dev->resource[i].flags & flags)
1141 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1142 if (dev->resource[i].flags & flags)
1145 err = do_pci_enable_device(dev, bars);
1147 atomic_dec(&dev->enable_cnt);
1152 * pci_enable_device_io - Initialize a device for use with IO space
1153 * @dev: PCI device to be initialized
1155 * Initialize device before it's used by a driver. Ask low-level code
1156 * to enable I/O resources. Wake up the device if it was suspended.
1157 * Beware, this function can fail.
1159 int pci_enable_device_io(struct pci_dev *dev)
1161 return __pci_enable_device_flags(dev, IORESOURCE_IO);
1165 * pci_enable_device_mem - Initialize a device for use with Memory space
1166 * @dev: PCI device to be initialized
1168 * Initialize device before it's used by a driver. Ask low-level code
1169 * to enable Memory resources. Wake up the device if it was suspended.
1170 * Beware, this function can fail.
1172 int pci_enable_device_mem(struct pci_dev *dev)
1174 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
1178 * pci_enable_device - Initialize device before it's used by a driver.
1179 * @dev: PCI device to be initialized
1181 * Initialize device before it's used by a driver. Ask low-level code
1182 * to enable I/O and memory. Wake up the device if it was suspended.
1183 * Beware, this function can fail.
1185 * Note we don't actually enable the device many times if we call
1186 * this function repeatedly (we just increment the count).
1188 int pci_enable_device(struct pci_dev *dev)
1190 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1194 * Managed PCI resources. This manages device on/off, intx/msi/msix
1195 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1196 * there's no need to track it separately. pci_devres is initialized
1197 * when a device is enabled using managed PCI device enable interface.
1200 unsigned int enabled:1;
1201 unsigned int pinned:1;
1202 unsigned int orig_intx:1;
1203 unsigned int restore_intx:1;
1207 static void pcim_release(struct device *gendev, void *res)
1209 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1210 struct pci_devres *this = res;
1213 if (dev->msi_enabled)
1214 pci_disable_msi(dev);
1215 if (dev->msix_enabled)
1216 pci_disable_msix(dev);
1218 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1219 if (this->region_mask & (1 << i))
1220 pci_release_region(dev, i);
1222 if (this->restore_intx)
1223 pci_intx(dev, this->orig_intx);
1225 if (this->enabled && !this->pinned)
1226 pci_disable_device(dev);
1229 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1231 struct pci_devres *dr, *new_dr;
1233 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1237 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1240 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1243 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1245 if (pci_is_managed(pdev))
1246 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1251 * pcim_enable_device - Managed pci_enable_device()
1252 * @pdev: PCI device to be initialized
1254 * Managed pci_enable_device().
1256 int pcim_enable_device(struct pci_dev *pdev)
1258 struct pci_devres *dr;
1261 dr = get_pci_dr(pdev);
1267 rc = pci_enable_device(pdev);
1269 pdev->is_managed = 1;
1276 * pcim_pin_device - Pin managed PCI device
1277 * @pdev: PCI device to pin
1279 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1280 * driver detach. @pdev must have been enabled with
1281 * pcim_enable_device().
1283 void pcim_pin_device(struct pci_dev *pdev)
1285 struct pci_devres *dr;
1287 dr = find_pci_dr(pdev);
1288 WARN_ON(!dr || !dr->enabled);
1294 * pcibios_disable_device - disable arch specific PCI resources for device dev
1295 * @dev: the PCI device to disable
1297 * Disables architecture specific PCI resources for the device. This
1298 * is the default implementation. Architecture implementations can
1301 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1303 static void do_pci_disable_device(struct pci_dev *dev)
1307 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1308 if (pci_command & PCI_COMMAND_MASTER) {
1309 pci_command &= ~PCI_COMMAND_MASTER;
1310 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1313 pcibios_disable_device(dev);
1317 * pci_disable_enabled_device - Disable device without updating enable_cnt
1318 * @dev: PCI device to disable
1320 * NOTE: This function is a backend of PCI power management routines and is
1321 * not supposed to be called drivers.
1323 void pci_disable_enabled_device(struct pci_dev *dev)
1325 if (pci_is_enabled(dev))
1326 do_pci_disable_device(dev);
1330 * pci_disable_device - Disable PCI device after use
1331 * @dev: PCI device to be disabled
1333 * Signal to the system that the PCI device is not in use by the system
1334 * anymore. This only involves disabling PCI bus-mastering, if active.
1336 * Note we don't actually disable the device until all callers of
1337 * pci_enable_device() have called pci_disable_device().
1340 pci_disable_device(struct pci_dev *dev)
1342 struct pci_devres *dr;
1344 dr = find_pci_dr(dev);
1348 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1351 do_pci_disable_device(dev);
1353 dev->is_busmaster = 0;
1357 * pcibios_set_pcie_reset_state - set reset state for device dev
1358 * @dev: the PCIe device reset
1359 * @state: Reset state to enter into
1362 * Sets the PCIe reset state for the device. This is the default
1363 * implementation. Architecture implementations can override this.
1365 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1366 enum pcie_reset_state state)
1372 * pci_set_pcie_reset_state - set reset state for device dev
1373 * @dev: the PCIe device reset
1374 * @state: Reset state to enter into
1377 * Sets the PCI reset state for the device.
1379 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1381 return pcibios_set_pcie_reset_state(dev, state);
1385 * pci_check_pme_status - Check if given device has generated PME.
1386 * @dev: Device to check.
1388 * Check the PME status of the device and if set, clear it and clear PME enable
1389 * (if set). Return 'true' if PME status and PME enable were both set or
1390 * 'false' otherwise.
1392 bool pci_check_pme_status(struct pci_dev *dev)
1401 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1402 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1403 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1406 /* Clear PME status. */
1407 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1408 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1409 /* Disable PME to avoid interrupt flood. */
1410 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1414 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1420 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1421 * @dev: Device to handle.
1422 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1424 * Check if @dev has generated PME and queue a resume request for it in that
1427 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1429 if (pme_poll_reset && dev->pme_poll)
1430 dev->pme_poll = false;
1432 if (pci_check_pme_status(dev)) {
1433 pci_wakeup_event(dev);
1434 pm_request_resume(&dev->dev);
1440 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1441 * @bus: Top bus of the subtree to walk.
1443 void pci_pme_wakeup_bus(struct pci_bus *bus)
1446 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1450 * pci_pme_capable - check the capability of PCI device to generate PME#
1451 * @dev: PCI device to handle.
1452 * @state: PCI state from which device will issue PME#.
1454 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1459 return !!(dev->pme_support & (1 << state));
1462 static void pci_pme_list_scan(struct work_struct *work)
1464 struct pci_pme_device *pme_dev, *n;
1466 mutex_lock(&pci_pme_list_mutex);
1467 if (!list_empty(&pci_pme_list)) {
1468 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1469 if (pme_dev->dev->pme_poll) {
1470 pci_pme_wakeup(pme_dev->dev, NULL);
1472 list_del(&pme_dev->list);
1476 if (!list_empty(&pci_pme_list))
1477 schedule_delayed_work(&pci_pme_work,
1478 msecs_to_jiffies(PME_TIMEOUT));
1480 mutex_unlock(&pci_pme_list_mutex);
1484 * pci_pme_active - enable or disable PCI device's PME# function
1485 * @dev: PCI device to handle.
1486 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1488 * The caller must verify that the device is capable of generating PME# before
1489 * calling this function with @enable equal to 'true'.
1491 void pci_pme_active(struct pci_dev *dev, bool enable)
1498 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1499 /* Clear PME_Status by writing 1 to it and enable PME# */
1500 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1502 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1504 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1506 /* PCI (as opposed to PCIe) PME requires that the device have
1507 its PME# line hooked up correctly. Not all hardware vendors
1508 do this, so the PME never gets delivered and the device
1509 remains asleep. The easiest way around this is to
1510 periodically walk the list of suspended devices and check
1511 whether any have their PME flag set. The assumption is that
1512 we'll wake up often enough anyway that this won't be a huge
1513 hit, and the power savings from the devices will still be a
1516 if (dev->pme_poll) {
1517 struct pci_pme_device *pme_dev;
1519 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1524 mutex_lock(&pci_pme_list_mutex);
1525 list_add(&pme_dev->list, &pci_pme_list);
1526 if (list_is_singular(&pci_pme_list))
1527 schedule_delayed_work(&pci_pme_work,
1528 msecs_to_jiffies(PME_TIMEOUT));
1529 mutex_unlock(&pci_pme_list_mutex);
1531 mutex_lock(&pci_pme_list_mutex);
1532 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1533 if (pme_dev->dev == dev) {
1534 list_del(&pme_dev->list);
1539 mutex_unlock(&pci_pme_list_mutex);
1544 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n",
1545 enable ? "enabled" : "disabled");
1549 * __pci_enable_wake - enable PCI device as wakeup event source
1550 * @dev: PCI device affected
1551 * @state: PCI state from which device will issue wakeup events
1552 * @runtime: True if the events are to be generated at run time
1553 * @enable: True to enable event generation; false to disable
1555 * This enables the device as a wakeup event source, or disables it.
1556 * When such events involves platform-specific hooks, those hooks are
1557 * called automatically by this routine.
1559 * Devices with legacy power management (no standard PCI PM capabilities)
1560 * always require such platform hooks.
1563 * 0 is returned on success
1564 * -EINVAL is returned if device is not supposed to wake up the system
1565 * Error code depending on the platform is returned if both the platform and
1566 * the native mechanism fail to enable the generation of wake-up events
1568 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1569 bool runtime, bool enable)
1573 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1576 /* Don't do the same thing twice in a row for one device. */
1577 if (!!enable == !!dev->wakeup_prepared)
1581 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1582 * Anderson we should be doing PME# wake enable followed by ACPI wake
1583 * enable. To disable wake-up we call the platform first, for symmetry.
1589 if (pci_pme_capable(dev, state))
1590 pci_pme_active(dev, true);
1593 error = runtime ? platform_pci_run_wake(dev, true) :
1594 platform_pci_sleep_wake(dev, true);
1598 dev->wakeup_prepared = true;
1601 platform_pci_run_wake(dev, false);
1603 platform_pci_sleep_wake(dev, false);
1604 pci_pme_active(dev, false);
1605 dev->wakeup_prepared = false;
1610 EXPORT_SYMBOL(__pci_enable_wake);
1613 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1614 * @dev: PCI device to prepare
1615 * @enable: True to enable wake-up event generation; false to disable
1617 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1618 * and this function allows them to set that up cleanly - pci_enable_wake()
1619 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1620 * ordering constraints.
1622 * This function only returns error code if the device is not capable of
1623 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1624 * enable wake-up power for it.
1626 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1628 return pci_pme_capable(dev, PCI_D3cold) ?
1629 pci_enable_wake(dev, PCI_D3cold, enable) :
1630 pci_enable_wake(dev, PCI_D3hot, enable);
1634 * pci_target_state - find an appropriate low power state for a given PCI dev
1637 * Use underlying platform code to find a supported low power state for @dev.
1638 * If the platform can't manage @dev, return the deepest state from which it
1639 * can generate wake events, based on any available PME info.
1641 pci_power_t pci_target_state(struct pci_dev *dev)
1643 pci_power_t target_state = PCI_D3hot;
1645 if (platform_pci_power_manageable(dev)) {
1647 * Call the platform to choose the target state of the device
1648 * and enable wake-up from this state if supported.
1650 pci_power_t state = platform_pci_choose_state(dev);
1653 case PCI_POWER_ERROR:
1658 if (pci_no_d1d2(dev))
1661 target_state = state;
1663 } else if (!dev->pm_cap) {
1664 target_state = PCI_D0;
1665 } else if (device_may_wakeup(&dev->dev)) {
1667 * Find the deepest state from which the device can generate
1668 * wake-up events, make it the target state and enable device
1671 if (dev->pme_support) {
1673 && !(dev->pme_support & (1 << target_state)))
1678 return target_state;
1682 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1683 * @dev: Device to handle.
1685 * Choose the power state appropriate for the device depending on whether
1686 * it can wake up the system and/or is power manageable by the platform
1687 * (PCI_D3hot is the default) and put the device into that state.
1689 int pci_prepare_to_sleep(struct pci_dev *dev)
1691 pci_power_t target_state = pci_target_state(dev);
1694 if (target_state == PCI_POWER_ERROR)
1697 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1699 error = pci_set_power_state(dev, target_state);
1702 pci_enable_wake(dev, target_state, false);
1708 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1709 * @dev: Device to handle.
1711 * Disable device's system wake-up capability and put it into D0.
1713 int pci_back_from_sleep(struct pci_dev *dev)
1715 pci_enable_wake(dev, PCI_D0, false);
1716 return pci_set_power_state(dev, PCI_D0);
1720 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1721 * @dev: PCI device being suspended.
1723 * Prepare @dev to generate wake-up events at run time and put it into a low
1726 int pci_finish_runtime_suspend(struct pci_dev *dev)
1728 pci_power_t target_state = pci_target_state(dev);
1731 if (target_state == PCI_POWER_ERROR)
1734 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1736 error = pci_set_power_state(dev, target_state);
1739 __pci_enable_wake(dev, target_state, true, false);
1745 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1746 * @dev: Device to check.
1748 * Return true if the device itself is cabable of generating wake-up events
1749 * (through the platform or using the native PCIe PME) or if the device supports
1750 * PME and one of its upstream bridges can generate wake-up events.
1752 bool pci_dev_run_wake(struct pci_dev *dev)
1754 struct pci_bus *bus = dev->bus;
1756 if (device_run_wake(&dev->dev))
1759 if (!dev->pme_support)
1762 while (bus->parent) {
1763 struct pci_dev *bridge = bus->self;
1765 if (device_run_wake(&bridge->dev))
1771 /* We have reached the root bus. */
1773 return device_run_wake(bus->bridge);
1777 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1780 * pci_pm_init - Initialize PM functions of given PCI device
1781 * @dev: PCI device to handle.
1783 void pci_pm_init(struct pci_dev *dev)
1788 pm_runtime_forbid(&dev->dev);
1789 device_enable_async_suspend(&dev->dev);
1790 dev->wakeup_prepared = false;
1794 /* find PCI PM capability in list */
1795 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1798 /* Check device's ability to generate PME# */
1799 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1801 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1802 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1803 pmc & PCI_PM_CAP_VER_MASK);
1808 dev->d3_delay = PCI_PM_D3_WAIT;
1810 dev->d1_support = false;
1811 dev->d2_support = false;
1812 if (!pci_no_d1d2(dev)) {
1813 if (pmc & PCI_PM_CAP_D1)
1814 dev->d1_support = true;
1815 if (pmc & PCI_PM_CAP_D2)
1816 dev->d2_support = true;
1818 if (dev->d1_support || dev->d2_support)
1819 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1820 dev->d1_support ? " D1" : "",
1821 dev->d2_support ? " D2" : "");
1824 pmc &= PCI_PM_CAP_PME_MASK;
1826 dev_printk(KERN_DEBUG, &dev->dev,
1827 "PME# supported from%s%s%s%s%s\n",
1828 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1829 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1830 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1831 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1832 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1833 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1834 dev->pme_poll = true;
1836 * Make device's PM flags reflect the wake-up capability, but
1837 * let the user space enable it to wake up the system as needed.
1839 device_set_wakeup_capable(&dev->dev, true);
1840 /* Disable the PME# generation functionality */
1841 pci_pme_active(dev, false);
1843 dev->pme_support = 0;
1848 * platform_pci_wakeup_init - init platform wakeup if present
1851 * Some devices don't have PCI PM caps but can still generate wakeup
1852 * events through platform methods (like ACPI events). If @dev supports
1853 * platform wakeup events, set the device flag to indicate as much. This
1854 * may be redundant if the device also supports PCI PM caps, but double
1855 * initialization should be safe in that case.
1857 void platform_pci_wakeup_init(struct pci_dev *dev)
1859 if (!platform_pci_can_wakeup(dev))
1862 device_set_wakeup_capable(&dev->dev, true);
1863 platform_pci_sleep_wake(dev, false);
1867 * pci_add_save_buffer - allocate buffer for saving given capability registers
1868 * @dev: the PCI device
1869 * @cap: the capability to allocate the buffer for
1870 * @size: requested size of the buffer
1872 static int pci_add_cap_save_buffer(
1873 struct pci_dev *dev, char cap, unsigned int size)
1876 struct pci_cap_saved_state *save_state;
1878 pos = pci_find_capability(dev, cap);
1882 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1886 save_state->cap.cap_nr = cap;
1887 save_state->cap.size = size;
1888 pci_add_saved_cap(dev, save_state);
1894 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1895 * @dev: the PCI device
1897 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1901 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1902 PCI_EXP_SAVE_REGS * sizeof(u16));
1905 "unable to preallocate PCI Express save buffer\n");
1907 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1910 "unable to preallocate PCI-X save buffer\n");
1914 * pci_enable_ari - enable ARI forwarding if hardware support it
1915 * @dev: the PCI device
1917 void pci_enable_ari(struct pci_dev *dev)
1922 struct pci_dev *bridge;
1924 if (!pci_is_pcie(dev) || dev->devfn)
1927 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1931 bridge = dev->bus->self;
1932 if (!bridge || !pci_is_pcie(bridge))
1935 pos = pci_pcie_cap(bridge);
1939 /* ARI is a PCIe v2 feature */
1940 pci_read_config_word(bridge, pos + PCI_EXP_FLAGS, &flags);
1941 if ((flags & PCI_EXP_FLAGS_VERS) < 2)
1944 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1945 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1948 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1949 ctrl |= PCI_EXP_DEVCTL2_ARI;
1950 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1952 bridge->ari_enabled = 1;
1956 * pci_enable_ido - enable ID-based ordering on a device
1957 * @dev: the PCI device
1958 * @type: which types of IDO to enable
1960 * Enable ID-based ordering on @dev. @type can contain the bits
1961 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
1962 * which types of transactions are allowed to be re-ordered.
1964 void pci_enable_ido(struct pci_dev *dev, unsigned long type)
1969 pos = pci_pcie_cap(dev);
1973 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
1974 if (type & PCI_EXP_IDO_REQUEST)
1975 ctrl |= PCI_EXP_IDO_REQ_EN;
1976 if (type & PCI_EXP_IDO_COMPLETION)
1977 ctrl |= PCI_EXP_IDO_CMP_EN;
1978 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
1980 EXPORT_SYMBOL(pci_enable_ido);
1983 * pci_disable_ido - disable ID-based ordering on a device
1984 * @dev: the PCI device
1985 * @type: which types of IDO to disable
1987 void pci_disable_ido(struct pci_dev *dev, unsigned long type)
1992 if (!pci_is_pcie(dev))
1995 pos = pci_pcie_cap(dev);
1999 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2000 if (type & PCI_EXP_IDO_REQUEST)
2001 ctrl &= ~PCI_EXP_IDO_REQ_EN;
2002 if (type & PCI_EXP_IDO_COMPLETION)
2003 ctrl &= ~PCI_EXP_IDO_CMP_EN;
2004 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2006 EXPORT_SYMBOL(pci_disable_ido);
2009 * pci_enable_obff - enable optimized buffer flush/fill
2011 * @type: type of signaling to use
2013 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2014 * signaling if possible, falling back to message signaling only if
2015 * WAKE# isn't supported. @type should indicate whether the PCIe link
2016 * be brought out of L0s or L1 to send the message. It should be either
2017 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2019 * If your device can benefit from receiving all messages, even at the
2020 * power cost of bringing the link back up from a low power state, use
2021 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2025 * Zero on success, appropriate error number on failure.
2027 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2034 if (!pci_is_pcie(dev))
2037 pos = pci_pcie_cap(dev);
2041 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2042 if (!(cap & PCI_EXP_OBFF_MASK))
2043 return -ENOTSUPP; /* no OBFF support at all */
2045 /* Make sure the topology supports OBFF as well */
2047 ret = pci_enable_obff(dev->bus->self, type);
2052 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2053 if (cap & PCI_EXP_OBFF_WAKE)
2054 ctrl |= PCI_EXP_OBFF_WAKE_EN;
2057 case PCI_EXP_OBFF_SIGNAL_L0:
2058 if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
2059 ctrl |= PCI_EXP_OBFF_MSGA_EN;
2061 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
2062 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2063 ctrl |= PCI_EXP_OBFF_MSGB_EN;
2066 WARN(1, "bad OBFF signal type\n");
2070 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2074 EXPORT_SYMBOL(pci_enable_obff);
2077 * pci_disable_obff - disable optimized buffer flush/fill
2080 * Disable OBFF on @dev.
2082 void pci_disable_obff(struct pci_dev *dev)
2087 if (!pci_is_pcie(dev))
2090 pos = pci_pcie_cap(dev);
2094 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2095 ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
2096 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2098 EXPORT_SYMBOL(pci_disable_obff);
2101 * pci_ltr_supported - check whether a device supports LTR
2105 * True if @dev supports latency tolerance reporting, false otherwise.
2107 bool pci_ltr_supported(struct pci_dev *dev)
2112 if (!pci_is_pcie(dev))
2115 pos = pci_pcie_cap(dev);
2119 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
2121 return cap & PCI_EXP_DEVCAP2_LTR;
2123 EXPORT_SYMBOL(pci_ltr_supported);
2126 * pci_enable_ltr - enable latency tolerance reporting
2129 * Enable LTR on @dev if possible, which means enabling it first on
2133 * Zero on success, errno on failure.
2135 int pci_enable_ltr(struct pci_dev *dev)
2141 if (!pci_ltr_supported(dev))
2144 pos = pci_pcie_cap(dev);
2148 /* Only primary function can enable/disable LTR */
2149 if (PCI_FUNC(dev->devfn) != 0)
2152 /* Enable upstream ports first */
2154 ret = pci_enable_ltr(dev->bus->self);
2159 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2160 ctrl |= PCI_EXP_LTR_EN;
2161 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2165 EXPORT_SYMBOL(pci_enable_ltr);
2168 * pci_disable_ltr - disable latency tolerance reporting
2171 void pci_disable_ltr(struct pci_dev *dev)
2176 if (!pci_ltr_supported(dev))
2179 pos = pci_pcie_cap(dev);
2183 /* Only primary function can enable/disable LTR */
2184 if (PCI_FUNC(dev->devfn) != 0)
2187 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
2188 ctrl &= ~PCI_EXP_LTR_EN;
2189 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
2191 EXPORT_SYMBOL(pci_disable_ltr);
2193 static int __pci_ltr_scale(int *val)
2197 while (*val > 1023) {
2198 *val = (*val + 31) / 32;
2205 * pci_set_ltr - set LTR latency values
2207 * @snoop_lat_ns: snoop latency in nanoseconds
2208 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2210 * Figure out the scale and set the LTR values accordingly.
2212 int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2214 int pos, ret, snoop_scale, nosnoop_scale;
2217 if (!pci_ltr_supported(dev))
2220 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2221 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2223 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2224 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2227 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2228 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2231 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2235 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2236 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2240 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2241 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2247 EXPORT_SYMBOL(pci_set_ltr);
2249 static int pci_acs_enable;
2252 * pci_request_acs - ask for ACS to be enabled if supported
2254 void pci_request_acs(void)
2260 * pci_enable_acs - enable ACS if hardware support it
2261 * @dev: the PCI device
2263 void pci_enable_acs(struct pci_dev *dev)
2269 if (!pci_acs_enable)
2272 if (!pci_is_pcie(dev))
2275 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2279 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2280 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2282 /* Source Validation */
2283 ctrl |= (cap & PCI_ACS_SV);
2285 /* P2P Request Redirect */
2286 ctrl |= (cap & PCI_ACS_RR);
2288 /* P2P Completion Redirect */
2289 ctrl |= (cap & PCI_ACS_CR);
2291 /* Upstream Forwarding */
2292 ctrl |= (cap & PCI_ACS_UF);
2294 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2298 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2299 * @dev: the PCI device
2300 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2302 * Perform INTx swizzling for a device behind one level of bridge. This is
2303 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2304 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2305 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2306 * the PCI Express Base Specification, Revision 2.1)
2308 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
2312 if (pci_ari_enabled(dev->bus))
2315 slot = PCI_SLOT(dev->devfn);
2317 return (((pin - 1) + slot) % 4) + 1;
2321 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2329 while (!pci_is_root_bus(dev->bus)) {
2330 pin = pci_swizzle_interrupt_pin(dev, pin);
2331 dev = dev->bus->self;
2338 * pci_common_swizzle - swizzle INTx all the way to root bridge
2339 * @dev: the PCI device
2340 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2342 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2343 * bridges all the way up to a PCI root bus.
2345 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2349 while (!pci_is_root_bus(dev->bus)) {
2350 pin = pci_swizzle_interrupt_pin(dev, pin);
2351 dev = dev->bus->self;
2354 return PCI_SLOT(dev->devfn);
2358 * pci_release_region - Release a PCI bar
2359 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2360 * @bar: BAR to release
2362 * Releases the PCI I/O and memory resources previously reserved by a
2363 * successful call to pci_request_region. Call this function only
2364 * after all use of the PCI regions has ceased.
2366 void pci_release_region(struct pci_dev *pdev, int bar)
2368 struct pci_devres *dr;
2370 if (pci_resource_len(pdev, bar) == 0)
2372 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2373 release_region(pci_resource_start(pdev, bar),
2374 pci_resource_len(pdev, bar));
2375 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2376 release_mem_region(pci_resource_start(pdev, bar),
2377 pci_resource_len(pdev, bar));
2379 dr = find_pci_dr(pdev);
2381 dr->region_mask &= ~(1 << bar);
2385 * __pci_request_region - Reserved PCI I/O and memory resource
2386 * @pdev: PCI device whose resources are to be reserved
2387 * @bar: BAR to be reserved
2388 * @res_name: Name to be associated with resource.
2389 * @exclusive: whether the region access is exclusive or not
2391 * Mark the PCI region associated with PCI device @pdev BR @bar as
2392 * being reserved by owner @res_name. Do not access any
2393 * address inside the PCI regions unless this call returns
2396 * If @exclusive is set, then the region is marked so that userspace
2397 * is explicitly not allowed to map the resource via /dev/mem or
2398 * sysfs MMIO access.
2400 * Returns 0 on success, or %EBUSY on error. A warning
2401 * message is also printed on failure.
2403 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2406 struct pci_devres *dr;
2408 if (pci_resource_len(pdev, bar) == 0)
2411 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2412 if (!request_region(pci_resource_start(pdev, bar),
2413 pci_resource_len(pdev, bar), res_name))
2416 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2417 if (!__request_mem_region(pci_resource_start(pdev, bar),
2418 pci_resource_len(pdev, bar), res_name,
2423 dr = find_pci_dr(pdev);
2425 dr->region_mask |= 1 << bar;
2430 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2431 &pdev->resource[bar]);
2436 * pci_request_region - Reserve PCI I/O and memory resource
2437 * @pdev: PCI device whose resources are to be reserved
2438 * @bar: BAR to be reserved
2439 * @res_name: Name to be associated with resource
2441 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2442 * being reserved by owner @res_name. Do not access any
2443 * address inside the PCI regions unless this call returns
2446 * Returns 0 on success, or %EBUSY on error. A warning
2447 * message is also printed on failure.
2449 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2451 return __pci_request_region(pdev, bar, res_name, 0);
2455 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2456 * @pdev: PCI device whose resources are to be reserved
2457 * @bar: BAR to be reserved
2458 * @res_name: Name to be associated with resource.
2460 * Mark the PCI region associated with PCI device @pdev BR @bar as
2461 * being reserved by owner @res_name. Do not access any
2462 * address inside the PCI regions unless this call returns
2465 * Returns 0 on success, or %EBUSY on error. A warning
2466 * message is also printed on failure.
2468 * The key difference that _exclusive makes it that userspace is
2469 * explicitly not allowed to map the resource via /dev/mem or
2472 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2474 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2477 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2478 * @pdev: PCI device whose resources were previously reserved
2479 * @bars: Bitmask of BARs to be released
2481 * Release selected PCI I/O and memory resources previously reserved.
2482 * Call this function only after all use of the PCI regions has ceased.
2484 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2488 for (i = 0; i < 6; i++)
2489 if (bars & (1 << i))
2490 pci_release_region(pdev, i);
2493 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2494 const char *res_name, int excl)
2498 for (i = 0; i < 6; i++)
2499 if (bars & (1 << i))
2500 if (__pci_request_region(pdev, i, res_name, excl))
2506 if (bars & (1 << i))
2507 pci_release_region(pdev, i);
2514 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2515 * @pdev: PCI device whose resources are to be reserved
2516 * @bars: Bitmask of BARs to be requested
2517 * @res_name: Name to be associated with resource
2519 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2520 const char *res_name)
2522 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2525 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2526 int bars, const char *res_name)
2528 return __pci_request_selected_regions(pdev, bars, res_name,
2529 IORESOURCE_EXCLUSIVE);
2533 * pci_release_regions - Release reserved PCI I/O and memory resources
2534 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2536 * Releases all PCI I/O and memory resources previously reserved by a
2537 * successful call to pci_request_regions. Call this function only
2538 * after all use of the PCI regions has ceased.
2541 void pci_release_regions(struct pci_dev *pdev)
2543 pci_release_selected_regions(pdev, (1 << 6) - 1);
2547 * pci_request_regions - Reserved PCI I/O and memory resources
2548 * @pdev: PCI device whose resources are to be reserved
2549 * @res_name: Name to be associated with resource.
2551 * Mark all PCI regions associated with PCI device @pdev as
2552 * being reserved by owner @res_name. Do not access any
2553 * address inside the PCI regions unless this call returns
2556 * Returns 0 on success, or %EBUSY on error. A warning
2557 * message is also printed on failure.
2559 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2561 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2565 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2566 * @pdev: PCI device whose resources are to be reserved
2567 * @res_name: Name to be associated with resource.
2569 * Mark all PCI regions associated with PCI device @pdev as
2570 * being reserved by owner @res_name. Do not access any
2571 * address inside the PCI regions unless this call returns
2574 * pci_request_regions_exclusive() will mark the region so that
2575 * /dev/mem and the sysfs MMIO access will not be allowed.
2577 * Returns 0 on success, or %EBUSY on error. A warning
2578 * message is also printed on failure.
2580 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2582 return pci_request_selected_regions_exclusive(pdev,
2583 ((1 << 6) - 1), res_name);
2586 static void __pci_set_master(struct pci_dev *dev, bool enable)
2590 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2592 cmd = old_cmd | PCI_COMMAND_MASTER;
2594 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2595 if (cmd != old_cmd) {
2596 dev_dbg(&dev->dev, "%s bus mastering\n",
2597 enable ? "enabling" : "disabling");
2598 pci_write_config_word(dev, PCI_COMMAND, cmd);
2600 dev->is_busmaster = enable;
2604 * pci_set_master - enables bus-mastering for device dev
2605 * @dev: the PCI device to enable
2607 * Enables bus-mastering on the device and calls pcibios_set_master()
2608 * to do the needed arch specific settings.
2610 void pci_set_master(struct pci_dev *dev)
2612 __pci_set_master(dev, true);
2613 pcibios_set_master(dev);
2617 * pci_clear_master - disables bus-mastering for device dev
2618 * @dev: the PCI device to disable
2620 void pci_clear_master(struct pci_dev *dev)
2622 __pci_set_master(dev, false);
2626 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2627 * @dev: the PCI device for which MWI is to be enabled
2629 * Helper function for pci_set_mwi.
2630 * Originally copied from drivers/net/acenic.c.
2631 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2633 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2635 int pci_set_cacheline_size(struct pci_dev *dev)
2639 if (!pci_cache_line_size)
2642 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2643 equal to or multiple of the right value. */
2644 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2645 if (cacheline_size >= pci_cache_line_size &&
2646 (cacheline_size % pci_cache_line_size) == 0)
2649 /* Write the correct value. */
2650 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2652 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2653 if (cacheline_size == pci_cache_line_size)
2656 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2657 "supported\n", pci_cache_line_size << 2);
2661 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2663 #ifdef PCI_DISABLE_MWI
2664 int pci_set_mwi(struct pci_dev *dev)
2669 int pci_try_set_mwi(struct pci_dev *dev)
2674 void pci_clear_mwi(struct pci_dev *dev)
2681 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2682 * @dev: the PCI device for which MWI is enabled
2684 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2686 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2689 pci_set_mwi(struct pci_dev *dev)
2694 rc = pci_set_cacheline_size(dev);
2698 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2699 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2700 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2701 cmd |= PCI_COMMAND_INVALIDATE;
2702 pci_write_config_word(dev, PCI_COMMAND, cmd);
2709 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2710 * @dev: the PCI device for which MWI is enabled
2712 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2713 * Callers are not required to check the return value.
2715 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2717 int pci_try_set_mwi(struct pci_dev *dev)
2719 int rc = pci_set_mwi(dev);
2724 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2725 * @dev: the PCI device to disable
2727 * Disables PCI Memory-Write-Invalidate transaction on the device
2730 pci_clear_mwi(struct pci_dev *dev)
2734 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2735 if (cmd & PCI_COMMAND_INVALIDATE) {
2736 cmd &= ~PCI_COMMAND_INVALIDATE;
2737 pci_write_config_word(dev, PCI_COMMAND, cmd);
2740 #endif /* ! PCI_DISABLE_MWI */
2743 * pci_intx - enables/disables PCI INTx for device dev
2744 * @pdev: the PCI device to operate on
2745 * @enable: boolean: whether to enable or disable PCI INTx
2747 * Enables/disables PCI INTx for device dev
2750 pci_intx(struct pci_dev *pdev, int enable)
2752 u16 pci_command, new;
2754 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2757 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2759 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2762 if (new != pci_command) {
2763 struct pci_devres *dr;
2765 pci_write_config_word(pdev, PCI_COMMAND, new);
2767 dr = find_pci_dr(pdev);
2768 if (dr && !dr->restore_intx) {
2769 dr->restore_intx = 1;
2770 dr->orig_intx = !enable;
2776 * pci_msi_off - disables any msi or msix capabilities
2777 * @dev: the PCI device to operate on
2779 * If you want to use msi see pci_enable_msi and friends.
2780 * This is a lower level primitive that allows us to disable
2781 * msi operation at the device level.
2783 void pci_msi_off(struct pci_dev *dev)
2788 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2790 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2791 control &= ~PCI_MSI_FLAGS_ENABLE;
2792 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2794 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2796 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2797 control &= ~PCI_MSIX_FLAGS_ENABLE;
2798 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2801 EXPORT_SYMBOL_GPL(pci_msi_off);
2803 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2805 return dma_set_max_seg_size(&dev->dev, size);
2807 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2809 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2811 return dma_set_seg_boundary(&dev->dev, mask);
2813 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2815 static int pcie_flr(struct pci_dev *dev, int probe)
2820 u16 status, control;
2822 pos = pci_pcie_cap(dev);
2826 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2827 if (!(cap & PCI_EXP_DEVCAP_FLR))
2833 /* Wait for Transaction Pending bit clean */
2834 for (i = 0; i < 4; i++) {
2836 msleep((1 << (i - 1)) * 100);
2838 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2839 if (!(status & PCI_EXP_DEVSTA_TRPND))
2843 dev_err(&dev->dev, "transaction is not cleared; "
2844 "proceeding with reset anyway\n");
2847 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
2848 control |= PCI_EXP_DEVCTL_BCR_FLR;
2849 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control);
2856 static int pci_af_flr(struct pci_dev *dev, int probe)
2863 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2867 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2868 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2874 /* Wait for Transaction Pending bit clean */
2875 for (i = 0; i < 4; i++) {
2877 msleep((1 << (i - 1)) * 100);
2879 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2880 if (!(status & PCI_AF_STATUS_TP))
2884 dev_err(&dev->dev, "transaction is not cleared; "
2885 "proceeding with reset anyway\n");
2888 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2895 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
2896 * @dev: Device to reset.
2897 * @probe: If set, only check if the device can be reset this way.
2899 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
2900 * unset, it will be reinitialized internally when going from PCI_D3hot to
2901 * PCI_D0. If that's the case and the device is not in a low-power state
2902 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
2904 * NOTE: This causes the caller to sleep for twice the device power transition
2905 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
2906 * by devault (i.e. unless the @dev's d3_delay field has a different value).
2907 * Moreover, only devices in D0 can be reset by this function.
2909 static int pci_pm_reset(struct pci_dev *dev, int probe)
2916 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2917 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2923 if (dev->current_state != PCI_D0)
2926 csr &= ~PCI_PM_CTRL_STATE_MASK;
2928 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2929 pci_dev_d3_sleep(dev);
2931 csr &= ~PCI_PM_CTRL_STATE_MASK;
2933 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2934 pci_dev_d3_sleep(dev);
2939 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2942 struct pci_dev *pdev;
2944 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2947 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2954 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2955 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2956 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2959 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2960 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2966 static int pci_dev_reset(struct pci_dev *dev, int probe)
2973 pci_block_user_cfg_access(dev);
2974 /* block PM suspend, driver probe, etc. */
2975 device_lock(&dev->dev);
2978 rc = pci_dev_specific_reset(dev, probe);
2982 rc = pcie_flr(dev, probe);
2986 rc = pci_af_flr(dev, probe);
2990 rc = pci_pm_reset(dev, probe);
2994 rc = pci_parent_bus_reset(dev, probe);
2997 device_unlock(&dev->dev);
2998 pci_unblock_user_cfg_access(dev);
3005 * __pci_reset_function - reset a PCI device function
3006 * @dev: PCI device to reset
3008 * Some devices allow an individual function to be reset without affecting
3009 * other functions in the same device. The PCI device must be responsive
3010 * to PCI config space in order to use this function.
3012 * The device function is presumed to be unused when this function is called.
3013 * Resetting the device will make the contents of PCI configuration space
3014 * random, so any caller of this must be prepared to reinitialise the
3015 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3018 * Returns 0 if the device function was successfully reset or negative if the
3019 * device doesn't support resetting a single function.
3021 int __pci_reset_function(struct pci_dev *dev)
3023 return pci_dev_reset(dev, 0);
3025 EXPORT_SYMBOL_GPL(__pci_reset_function);
3028 * pci_probe_reset_function - check whether the device can be safely reset
3029 * @dev: PCI device to reset
3031 * Some devices allow an individual function to be reset without affecting
3032 * other functions in the same device. The PCI device must be responsive
3033 * to PCI config space in order to use this function.
3035 * Returns 0 if the device function can be reset or negative if the
3036 * device doesn't support resetting a single function.
3038 int pci_probe_reset_function(struct pci_dev *dev)
3040 return pci_dev_reset(dev, 1);
3044 * pci_reset_function - quiesce and reset a PCI device function
3045 * @dev: PCI device to reset
3047 * Some devices allow an individual function to be reset without affecting
3048 * other functions in the same device. The PCI device must be responsive
3049 * to PCI config space in order to use this function.
3051 * This function does not just reset the PCI portion of a device, but
3052 * clears all the state associated with the device. This function differs
3053 * from __pci_reset_function in that it saves and restores device state
3056 * Returns 0 if the device function was successfully reset or negative if the
3057 * device doesn't support resetting a single function.
3059 int pci_reset_function(struct pci_dev *dev)
3063 rc = pci_dev_reset(dev, 1);
3067 pci_save_state(dev);
3070 * both INTx and MSI are disabled after the Interrupt Disable bit
3071 * is set and the Bus Master bit is cleared.
3073 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3075 rc = pci_dev_reset(dev, 0);
3077 pci_restore_state(dev);
3081 EXPORT_SYMBOL_GPL(pci_reset_function);
3084 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3085 * @dev: PCI device to query
3087 * Returns mmrbc: maximum designed memory read count in bytes
3088 * or appropriate error value.
3090 int pcix_get_max_mmrbc(struct pci_dev *dev)
3095 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3099 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3102 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3104 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3107 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3108 * @dev: PCI device to query
3110 * Returns mmrbc: maximum memory read count in bytes
3111 * or appropriate error value.
3113 int pcix_get_mmrbc(struct pci_dev *dev)
3118 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3122 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3125 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3127 EXPORT_SYMBOL(pcix_get_mmrbc);
3130 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3131 * @dev: PCI device to query
3132 * @mmrbc: maximum memory read count in bytes
3133 * valid values are 512, 1024, 2048, 4096
3135 * If possible sets maximum memory read byte count, some bridges have erratas
3136 * that prevent this.
3138 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3144 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3147 v = ffs(mmrbc) - 10;
3149 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3153 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3156 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3159 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3162 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3164 if (v > o && dev->bus &&
3165 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3168 cmd &= ~PCI_X_CMD_MAX_READ;
3170 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3175 EXPORT_SYMBOL(pcix_set_mmrbc);
3178 * pcie_get_readrq - get PCI Express read request size
3179 * @dev: PCI device to query
3181 * Returns maximum memory read request in bytes
3182 * or appropriate error value.
3184 int pcie_get_readrq(struct pci_dev *dev)
3189 cap = pci_pcie_cap(dev);
3193 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3195 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3199 EXPORT_SYMBOL(pcie_get_readrq);
3202 * pcie_set_readrq - set PCI Express maximum memory read request
3203 * @dev: PCI device to query
3204 * @rq: maximum memory read count in bytes
3205 * valid values are 128, 256, 512, 1024, 2048, 4096
3207 * If possible sets maximum memory read request in bytes
3209 int pcie_set_readrq(struct pci_dev *dev, int rq)
3211 int cap, err = -EINVAL;
3214 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3217 cap = pci_pcie_cap(dev);
3221 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3225 * If using the "performance" PCIe config, we clamp the
3226 * read rq size to the max packet size to prevent the
3227 * host bridge generating requests larger than we can
3230 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3231 int mps = pcie_get_mps(dev);
3239 v = (ffs(rq) - 8) << 12;
3241 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
3242 ctl &= ~PCI_EXP_DEVCTL_READRQ;
3244 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3250 EXPORT_SYMBOL(pcie_set_readrq);
3253 * pcie_get_mps - get PCI Express maximum payload size
3254 * @dev: PCI device to query
3256 * Returns maximum payload size in bytes
3257 * or appropriate error value.
3259 int pcie_get_mps(struct pci_dev *dev)
3264 cap = pci_pcie_cap(dev);
3268 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3270 ret = 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3276 * pcie_set_mps - set PCI Express maximum payload size
3277 * @dev: PCI device to query
3278 * @mps: maximum payload size in bytes
3279 * valid values are 128, 256, 512, 1024, 2048, 4096
3281 * If possible sets maximum payload size
3283 int pcie_set_mps(struct pci_dev *dev, int mps)
3285 int cap, err = -EINVAL;
3288 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3292 if (v > dev->pcie_mpss)
3296 cap = pci_pcie_cap(dev);
3300 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
3304 if ((ctl & PCI_EXP_DEVCTL_PAYLOAD) != v) {
3305 ctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
3307 err = pci_write_config_word(dev, cap + PCI_EXP_DEVCTL, ctl);
3314 * pci_select_bars - Make BAR mask from the type of resource
3315 * @dev: the PCI device for which BAR mask is made
3316 * @flags: resource type mask to be selected
3318 * This helper routine makes bar mask from the type of resource.
3320 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
3323 for (i = 0; i < PCI_NUM_RESOURCES; i++)
3324 if (pci_resource_flags(dev, i) & flags)
3330 * pci_resource_bar - get position of the BAR associated with a resource
3331 * @dev: the PCI device
3332 * @resno: the resource number
3333 * @type: the BAR type to be filled in
3335 * Returns BAR position in config space, or 0 if the BAR is invalid.
3337 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
3341 if (resno < PCI_ROM_RESOURCE) {
3342 *type = pci_bar_unknown;
3343 return PCI_BASE_ADDRESS_0 + 4 * resno;
3344 } else if (resno == PCI_ROM_RESOURCE) {
3345 *type = pci_bar_mem32;
3346 return dev->rom_base_reg;
3347 } else if (resno < PCI_BRIDGE_RESOURCES) {
3348 /* device specific resource */
3349 reg = pci_iov_resource_bar(dev, resno, type);
3354 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
3358 /* Some architectures require additional programming to enable VGA */
3359 static arch_set_vga_state_t arch_set_vga_state;
3361 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
3363 arch_set_vga_state = func; /* NULL disables */
3366 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
3367 unsigned int command_bits, u32 flags)
3369 if (arch_set_vga_state)
3370 return arch_set_vga_state(dev, decode, command_bits,
3376 * pci_set_vga_state - set VGA decode state on device and parents if requested
3377 * @dev: the PCI device
3378 * @decode: true = enable decoding, false = disable decoding
3379 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
3380 * @flags: traverse ancestors and change bridges
3381 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
3383 int pci_set_vga_state(struct pci_dev *dev, bool decode,
3384 unsigned int command_bits, u32 flags)
3386 struct pci_bus *bus;
3387 struct pci_dev *bridge;
3391 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
3393 /* ARCH specific VGA enables */
3394 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
3398 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
3399 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3401 cmd |= command_bits;
3403 cmd &= ~command_bits;
3404 pci_write_config_word(dev, PCI_COMMAND, cmd);
3407 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
3414 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
3417 cmd |= PCI_BRIDGE_CTL_VGA;
3419 cmd &= ~PCI_BRIDGE_CTL_VGA;
3420 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
3428 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
3429 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
3430 static DEFINE_SPINLOCK(resource_alignment_lock);
3433 * pci_specified_resource_alignment - get resource alignment specified by user.
3434 * @dev: the PCI device to get
3436 * RETURNS: Resource alignment if it is specified.
3437 * Zero if it is not specified.
3439 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
3441 int seg, bus, slot, func, align_order, count;
3442 resource_size_t align = 0;
3445 spin_lock(&resource_alignment_lock);
3446 p = resource_alignment_param;
3449 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
3455 if (sscanf(p, "%x:%x:%x.%x%n",
3456 &seg, &bus, &slot, &func, &count) != 4) {
3458 if (sscanf(p, "%x:%x.%x%n",
3459 &bus, &slot, &func, &count) != 3) {
3460 /* Invalid format */
3461 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
3467 if (seg == pci_domain_nr(dev->bus) &&
3468 bus == dev->bus->number &&
3469 slot == PCI_SLOT(dev->devfn) &&
3470 func == PCI_FUNC(dev->devfn)) {
3471 if (align_order == -1) {
3474 align = 1 << align_order;
3479 if (*p != ';' && *p != ',') {
3480 /* End of param or invalid format */
3485 spin_unlock(&resource_alignment_lock);
3490 * pci_is_reassigndev - check if specified PCI is target device to reassign
3491 * @dev: the PCI device to check
3493 * RETURNS: non-zero for PCI device is a target device to reassign,
3496 int pci_is_reassigndev(struct pci_dev *dev)
3498 #ifdef CONFIG_PCI_GUESTDEV
3501 result = pci_is_guestdev_to_reassign(dev);
3504 #endif /* CONFIG_PCI_GUESTDEV */
3505 return (pci_specified_resource_alignment(dev) != 0);
3508 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
3510 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
3511 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
3512 spin_lock(&resource_alignment_lock);
3513 strncpy(resource_alignment_param, buf, count);
3514 resource_alignment_param[count] = '\0';
3515 spin_unlock(&resource_alignment_lock);
3519 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
3522 spin_lock(&resource_alignment_lock);
3523 count = snprintf(buf, size, "%s", resource_alignment_param);
3524 spin_unlock(&resource_alignment_lock);
3528 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
3530 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
3533 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
3534 const char *buf, size_t count)
3536 return pci_set_resource_alignment_param(buf, count);
3539 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
3540 pci_resource_alignment_store);
3542 static int __init pci_resource_alignment_sysfs_init(void)
3544 return bus_create_file(&pci_bus_type,
3545 &bus_attr_resource_alignment);
3548 late_initcall(pci_resource_alignment_sysfs_init);
3550 static void __devinit pci_no_domains(void)
3552 #ifdef CONFIG_PCI_DOMAINS
3553 pci_domains_supported = 0;
3558 * pci_ext_cfg_enabled - can we access extended PCI config space?
3559 * @dev: The PCI device of the root bridge.
3561 * Returns 1 if we can access PCI extended config space (offsets
3562 * greater than 0xff). This is the default implementation. Architecture
3563 * implementations can override this.
3565 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
3570 void __weak pci_fixup_cardbus(struct pci_bus *bus)
3573 EXPORT_SYMBOL(pci_fixup_cardbus);
3575 static int __init pci_setup(char *str)
3578 char *k = strchr(str, ',');
3581 if (*str && (str = pcibios_setup(str)) && *str) {
3582 if (!strcmp(str, "nomsi")) {
3584 } else if (!strcmp(str, "noaer")) {
3586 } else if (!strncmp(str, "realloc", 7)) {
3588 } else if (!strcmp(str, "nodomains")) {
3590 } else if (!strncmp(str, "cbiosize=", 9)) {
3591 pci_cardbus_io_size = memparse(str + 9, &str);
3592 } else if (!strncmp(str, "cbmemsize=", 10)) {
3593 pci_cardbus_mem_size = memparse(str + 10, &str);
3594 } else if (!strncmp(str, "resource_alignment=", 19)) {
3595 pci_set_resource_alignment_param(str + 19,
3597 } else if (!strncmp(str, "ecrc=", 5)) {
3598 pcie_ecrc_get_policy(str + 5);
3599 } else if (!strncmp(str, "hpiosize=", 9)) {
3600 pci_hotplug_io_size = memparse(str + 9, &str);
3601 } else if (!strncmp(str, "hpmemsize=", 10)) {
3602 pci_hotplug_mem_size = memparse(str + 10, &str);
3603 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
3604 pcie_bus_config = PCIE_BUS_TUNE_OFF;
3605 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
3606 pcie_bus_config = PCIE_BUS_SAFE;
3607 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
3608 pcie_bus_config = PCIE_BUS_PERFORMANCE;
3609 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
3610 pcie_bus_config = PCIE_BUS_PEER2PEER;
3612 printk(KERN_ERR "PCI: Unknown option `%s'\n",
3620 early_param("pci", pci_setup);
3622 EXPORT_SYMBOL(pci_reenable_device);
3623 EXPORT_SYMBOL(pci_enable_device_io);
3624 EXPORT_SYMBOL(pci_enable_device_mem);
3625 EXPORT_SYMBOL(pci_enable_device);
3626 EXPORT_SYMBOL(pcim_enable_device);
3627 EXPORT_SYMBOL(pcim_pin_device);
3628 EXPORT_SYMBOL(pci_disable_device);
3629 EXPORT_SYMBOL(pci_find_capability);
3630 EXPORT_SYMBOL(pci_bus_find_capability);
3631 EXPORT_SYMBOL(pci_release_regions);
3632 EXPORT_SYMBOL(pci_request_regions);
3633 EXPORT_SYMBOL(pci_request_regions_exclusive);
3634 EXPORT_SYMBOL(pci_release_region);
3635 EXPORT_SYMBOL(pci_request_region);
3636 EXPORT_SYMBOL(pci_request_region_exclusive);
3637 EXPORT_SYMBOL(pci_release_selected_regions);
3638 EXPORT_SYMBOL(pci_request_selected_regions);
3639 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3640 EXPORT_SYMBOL(pci_set_master);
3641 EXPORT_SYMBOL(pci_clear_master);
3642 EXPORT_SYMBOL(pci_set_mwi);
3643 EXPORT_SYMBOL(pci_try_set_mwi);
3644 EXPORT_SYMBOL(pci_clear_mwi);
3645 EXPORT_SYMBOL_GPL(pci_intx);
3646 EXPORT_SYMBOL(pci_assign_resource);
3647 EXPORT_SYMBOL(pci_find_parent_resource);
3648 EXPORT_SYMBOL(pci_select_bars);
3650 EXPORT_SYMBOL(pci_set_power_state);
3651 EXPORT_SYMBOL(pci_save_state);
3652 EXPORT_SYMBOL(pci_restore_state);
3653 EXPORT_SYMBOL(pci_pme_capable);
3654 EXPORT_SYMBOL(pci_pme_active);
3655 EXPORT_SYMBOL(pci_wake_from_d3);
3656 EXPORT_SYMBOL(pci_target_state);
3657 EXPORT_SYMBOL(pci_prepare_to_sleep);
3658 EXPORT_SYMBOL(pci_back_from_sleep);
3659 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);