2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2001-2003 Silicon Graphics, Inc. All rights reserved.
9 #include <linux/types.h>
10 #include <asm/sn/sgi.h>
11 #include <asm/sn/iograph.h>
12 #include <asm/sn/pci/pciio.h>
13 #include <asm/sn/pci/pcibr.h>
14 #include <asm/sn/pci/pcibr_private.h>
15 #include <asm/sn/pci/pci_defs.h>
17 void pcibr_rrb_alloc_init(pcibr_soft_t, int, int, int);
18 void pcibr_rrb_alloc_more(pcibr_soft_t, int, int, int);
20 int pcibr_wrb_flush(vertex_hdl_t);
21 int pcibr_rrb_alloc(vertex_hdl_t, int *, int *);
22 int pcibr_rrb_check(vertex_hdl_t, int *, int *, int *, int *);
23 int pcibr_alloc_all_rrbs(vertex_hdl_t, int, int, int, int,
24 int, int, int, int, int);
25 void pcibr_rrb_flush(vertex_hdl_t);
26 int pcibr_slot_initial_rrb_alloc(vertex_hdl_t,pciio_slot_t);
28 void pcibr_rrb_debug(char *, pcibr_soft_t);
34 * All the do_pcibr_rrb_ routines manipulate the Read Response Buffer (rrb)
35 * registers within the Bridge. Two 32 registers (b_rrb_map[2] also known
36 * as the b_even_resp & b_odd_resp registers) are used to allocate the 16
37 * rrbs to devices. The b_even_resp register represents even num devices,
38 * and b_odd_resp represent odd number devices. Each rrb is represented by
39 * 4-bits within a register.
40 * BRIDGE & XBRIDGE: 1 enable bit, 1 virtual channel bit, 2 device bits
41 * PIC: 1 enable bit, 2 virtual channel bits, 1 device bit
42 * PIC has 4 devices per bus, and 4 virtual channels (1 normal & 3 virtual)
43 * per device. BRIDGE & XBRIDGE have 8 devices per bus and 2 virtual
44 * channels (1 normal & 1 virtual) per device. See the BRIDGE and PIC ASIC
45 * Programmers Reference guides for more information.
48 #define RRB_MASK (0xf) /* mask a single rrb within reg */
49 #define RRB_SIZE (4) /* sizeof rrb within reg (bits) */
51 #define RRB_ENABLE_BIT (0x8) /* [BRIDGE | PIC]_RRB_EN */
52 #define NUM_PDEV_BITS (1)
53 #define NUMBER_VCHANNELS (4)
54 #define SLOT_2_PDEV(slot) ((slot) >> 1)
55 #define SLOT_2_RRB_REG(slot) ((slot) & 0x1)
57 #define RRB_VALID(rrb) (0x00010000 << (rrb))
58 #define RRB_INUSE(rrb) (0x00000001 << (rrb))
59 #define RRB_CLEAR(rrb) (0x00000001 << (rrb))
61 /* validate that the slot and virtual channel are valid */
62 #define VALIDATE_SLOT_n_VCHAN(s, v) \
63 (((((s) != PCIIO_SLOT_NONE) && ((s) <= (pciio_slot_t)3)) && \
64 (((v) >= 0) && ((v) <= 3))) ? 1 : 0)
67 * Count how many RRBs are marked valid for the specified PCI slot
68 * and virtual channel. Return the count.
71 do_pcibr_rrb_count_valid(pcibr_soft_t pcibr_soft,
76 uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
79 if (!VALIDATE_SLOT_n_VCHAN(slot, vchan)) {
80 printk(KERN_WARNING "do_pcibr_rrb_count_valid() invalid slot/vchan [%d/%d]\n", slot, vchan);
84 enable_bit = RRB_ENABLE_BIT;
85 vchan_bits = vchan << NUM_PDEV_BITS;
86 pdev_bits = SLOT_2_PDEV(slot);
87 rrb_bits = enable_bit | vchan_bits | pdev_bits;
89 tmp = pcireg_rrb_get(pcibr_soft, SLOT_2_RRB_REG(slot));
91 for (rrb_index = 0; rrb_index < 8; rrb_index++) {
92 if ((tmp & RRB_MASK) == rrb_bits)
94 tmp = (tmp >> RRB_SIZE);
101 * Count how many RRBs are available to be allocated to the specified
102 * slot. Return the count.
105 do_pcibr_rrb_count_avail(pcibr_soft_t pcibr_soft,
110 int rrb_index, cnt=0;
112 if (!VALIDATE_SLOT_n_VCHAN(slot, 0)) {
113 printk(KERN_WARNING "do_pcibr_rrb_count_avail() invalid slot/vchan");
117 enable_bit = RRB_ENABLE_BIT;
119 tmp = pcireg_rrb_get(pcibr_soft, SLOT_2_RRB_REG(slot));
121 for (rrb_index = 0; rrb_index < 8; rrb_index++) {
122 if ((tmp & enable_bit) != enable_bit)
124 tmp = (tmp >> RRB_SIZE);
131 * Allocate some additional RRBs for the specified slot and the specified
132 * virtual channel. Returns -1 if there were insufficient free RRBs to
133 * satisfy the request, or 0 if the request was fulfilled.
135 * Note that if a request can be partially filled, it will be, even if
139 do_pcibr_rrb_alloc(pcibr_soft_t pcibr_soft,
144 uint64_t reg, tmp = 0;
145 uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
148 if (!VALIDATE_SLOT_n_VCHAN(slot, vchan)) {
149 printk(KERN_WARNING "do_pcibr_rrb_alloc() invalid slot/vchan");
153 enable_bit = RRB_ENABLE_BIT;
154 vchan_bits = vchan << NUM_PDEV_BITS;
155 pdev_bits = SLOT_2_PDEV(slot);
156 rrb_bits = enable_bit | vchan_bits | pdev_bits;
158 reg = tmp = pcireg_rrb_get(pcibr_soft, SLOT_2_RRB_REG(slot));
160 for (rrb_index = 0; ((rrb_index < 8) && (more > 0)); rrb_index++) {
161 if ((tmp & enable_bit) != enable_bit) {
162 /* clear the rrb and OR in the new rrb into 'reg' */
163 reg = reg & ~(RRB_MASK << (RRB_SIZE * rrb_index));
164 reg = reg | (rrb_bits << (RRB_SIZE * rrb_index));
167 tmp = (tmp >> RRB_SIZE);
170 pcireg_rrb_set(pcibr_soft, SLOT_2_RRB_REG(slot), reg);
171 return (more ? -1 : 0);
175 * Wait for the the specified rrb to have no outstanding XIO pkts
176 * and for all data to be drained. Mark the rrb as no longer being
180 do_pcibr_rrb_clear(pcibr_soft_t pcibr_soft, int rrb)
184 /* bridge_lock must be held; this RRB must be disabled. */
186 /* wait until RRB has no outstanduing XIO packets. */
187 status = pcireg_rrb_status_get(pcibr_soft);
188 while (status & RRB_INUSE(rrb)) {
189 status = pcireg_rrb_status_get(pcibr_soft);
192 /* if the RRB has data, drain it. */
193 if (status & RRB_VALID(rrb)) {
194 pcireg_rrb_clear_set(pcibr_soft, RRB_CLEAR(rrb));
196 /* wait until RRB is no longer valid. */
197 status = pcireg_rrb_status_get(pcibr_soft);
198 while (status & RRB_VALID(rrb)) {
199 status = pcireg_rrb_status_get(pcibr_soft);
206 * Release some of the RRBs that have been allocated for the specified
207 * slot. Returns zero for success, or negative if it was unable to free
210 * Note that if a request can be partially fulfilled, it will be, even
211 * if we return failure.
214 do_pcibr_rrb_free(pcibr_soft_t pcibr_soft,
219 uint64_t reg, tmp = 0, clr = 0;
220 uint16_t enable_bit, vchan_bits, pdev_bits, rrb_bits;
223 if (!VALIDATE_SLOT_n_VCHAN(slot, vchan)) {
224 printk(KERN_WARNING "do_pcibr_rrb_free() invalid slot/vchan");
228 enable_bit = RRB_ENABLE_BIT;
229 vchan_bits = vchan << NUM_PDEV_BITS;
230 pdev_bits = SLOT_2_PDEV(slot);
231 rrb_bits = enable_bit | vchan_bits | pdev_bits;
233 reg = tmp = pcireg_rrb_get(pcibr_soft, SLOT_2_RRB_REG(slot));
235 for (rrb_index = 0; ((rrb_index < 8) && (less > 0)); rrb_index++) {
236 if ((tmp & RRB_MASK) == rrb_bits) {
238 * the old do_pcibr_rrb_free() code only clears the enable bit
239 * but I say we should clear the whole rrb (ie):
240 * reg = reg & ~(RRB_MASK << (RRB_SIZE * rrb_index));
241 * But to be compatible with old code we'll only clear enable.
243 reg = reg & ~(RRB_ENABLE_BIT << (RRB_SIZE * rrb_index));
244 clr = clr | (enable_bit << (RRB_SIZE * rrb_index));
247 tmp = (tmp >> RRB_SIZE);
250 pcireg_rrb_set(pcibr_soft, SLOT_2_RRB_REG(slot), reg);
252 /* call do_pcibr_rrb_clear() for all the rrbs we've freed */
253 for (rrb_index = 0; rrb_index < 8; rrb_index++) {
254 int evn_odd = SLOT_2_RRB_REG(slot);
255 if (clr & (enable_bit << (RRB_SIZE * rrb_index)))
256 do_pcibr_rrb_clear(pcibr_soft, (2 * rrb_index) + evn_odd);
259 return (less ? -1 : 0);
263 * Flush the specified rrb by calling do_pcibr_rrb_clear(). This
264 * routine is just a wrapper to make sure the rrb is disabled
265 * before calling do_pcibr_rrb_clear().
268 do_pcibr_rrb_flush(pcibr_soft_t pcibr_soft, int rrbn)
271 int shft = (RRB_SIZE * (rrbn >> 1));
272 uint64_t ebit = RRB_ENABLE_BIT << shft;
274 rrbv = pcireg_rrb_get(pcibr_soft, (rrbn & 1));
276 pcireg_rrb_set(pcibr_soft, (rrbn & 1), (rrbv & ~ebit));
279 do_pcibr_rrb_clear(pcibr_soft, rrbn);
282 pcireg_rrb_set(pcibr_soft, (rrbn & 1), rrbv);
287 * free all the rrbs (both the normal and virtual channels) for the
291 do_pcibr_rrb_free_all(pcibr_soft_t pcibr_soft,
295 int vchan_total = NUMBER_VCHANNELS;
297 /* pretend we own all 8 rrbs and just ignore the return value */
298 for (vchan = 0; vchan < vchan_total; vchan++) {
299 do_pcibr_rrb_free(pcibr_soft, slot, vchan, 8);
300 pcibr_soft->bs_rrb_valid[slot][vchan] = 0;
306 * Initialize a slot with a given number of RRBs. (this routine
307 * will also give back RRBs if the slot has more than we want).
310 pcibr_rrb_alloc_init(pcibr_soft_t pcibr_soft,
315 int had = pcibr_soft->bs_rrb_valid[slot][vchan];
319 for (added = 0; have < init_rrbs; ++added, ++have) {
320 if (pcibr_soft->bs_rrb_res[slot] > 0)
321 pcibr_soft->bs_rrb_res[slot]--;
322 else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
323 pcibr_soft->bs_rrb_avail[slot & 1]--;
326 if (do_pcibr_rrb_alloc(pcibr_soft, slot, vchan, 1) < 0)
329 pcibr_soft->bs_rrb_valid[slot][vchan]++;
332 /* Free any extra RRBs that the slot may have allocated to it */
333 while (have > init_rrbs) {
334 pcibr_soft->bs_rrb_avail[slot & 1]++;
335 pcibr_soft->bs_rrb_valid[slot][vchan]--;
336 do_pcibr_rrb_free(pcibr_soft, slot, vchan, 1);
341 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
342 "pcibr_rrb_alloc_init: had %d, added/removed %d, "
343 "(of requested %d) RRBs "
344 "to slot %d, vchan %d\n", had, added, init_rrbs,
345 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vchan));
347 pcibr_rrb_debug("pcibr_rrb_alloc_init", pcibr_soft);
352 * Allocate more RRBs to a given slot (if the RRBs are available).
355 pcibr_rrb_alloc_more(pcibr_soft_t pcibr_soft,
362 for (added = 0; added < more_rrbs; ++added) {
363 if (pcibr_soft->bs_rrb_res[slot] > 0)
364 pcibr_soft->bs_rrb_res[slot]--;
365 else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
366 pcibr_soft->bs_rrb_avail[slot & 1]--;
369 if (do_pcibr_rrb_alloc(pcibr_soft, slot, vchan, 1) < 0)
372 pcibr_soft->bs_rrb_valid[slot][vchan]++;
375 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
376 "pcibr_rrb_alloc_more: added %d (of %d requested) RRBs "
377 "to slot %d, vchan %d\n", added, more_rrbs,
378 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot), vchan));
380 pcibr_rrb_debug("pcibr_rrb_alloc_more", pcibr_soft);
385 * Flush all the rrb's assigned to the specified connection point.
388 pcibr_rrb_flush(vertex_hdl_t pconn_vhdl)
390 pciio_info_t pciio_info = pciio_info_get(pconn_vhdl);
391 pcibr_soft_t pcibr_soft = (pcibr_soft_t)pciio_info_mfast_get(pciio_info);
392 pciio_slot_t slot = PCIBR_INFO_SLOT_GET_INT(pciio_info);
395 uint16_t enable_bit, pdev_bits, rrb_bits, rrb_mask;
399 enable_bit = RRB_ENABLE_BIT;
400 pdev_bits = SLOT_2_PDEV(slot);
401 rrb_bits = enable_bit | pdev_bits;
402 rrb_mask = enable_bit | ((NUM_PDEV_BITS << 1) - 1);
404 tmp = pcireg_rrb_get(pcibr_soft, SLOT_2_RRB_REG(slot));
406 s = pcibr_lock(pcibr_soft);
407 for (rrb_index = 0; rrb_index < 8; rrb_index++) {
408 int evn_odd = SLOT_2_RRB_REG(slot);
409 if ((tmp & rrb_mask) == rrb_bits)
410 do_pcibr_rrb_flush(pcibr_soft, (2 * rrb_index) + evn_odd);
411 tmp = (tmp >> RRB_SIZE);
413 pcibr_unlock(pcibr_soft, s);
418 * Device driver interface to flush the write buffers for a specified
419 * device hanging off the bridge.
422 pcibr_wrb_flush(vertex_hdl_t pconn_vhdl)
424 pciio_info_t pciio_info = pciio_info_get(pconn_vhdl);
425 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info);
426 pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
428 pcireg_wrb_flush_get(pcibr_soft, pciio_slot);
434 * Device driver interface to request RRBs for a specified device
435 * hanging off a Bridge. The driver requests the total number of
436 * RRBs it would like for the normal channel (vchan0) and for the
437 * "virtual channel" (vchan1). The actual number allocated to each
438 * channel is returned.
440 * If we cannot allocate at least one RRB to a channel that needs
441 * at least one, return -1 (failure). Otherwise, satisfy the request
442 * as best we can and return 0.
445 pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
449 pciio_info_t pciio_info = pciio_info_get(pconn_vhdl);
450 pciio_slot_t pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info);
451 pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
468 * TBD: temper request with admin info about RRB allocation,
469 * and according to demand from other devices on this Bridge.
471 * One way of doing this would be to allocate two RRBs
472 * for each device on the bus, before any drivers start
473 * asking for extras. This has the weakness that one
474 * driver might not give back an "extra" RRB until after
475 * another driver has already failed to get one that
479 s = pcibr_lock(pcibr_soft);
481 vchan_total = NUMBER_VCHANNELS;
483 /* Save the boot-time RRB configuration for this slot */
484 if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot][VCHAN0] < 0) {
485 for (vchan = 0; vchan < vchan_total; vchan++)
486 pcibr_soft->bs_rrb_valid_dflt[pciio_slot][vchan] =
487 pcibr_soft->bs_rrb_valid[pciio_slot][vchan];
488 pcibr_soft->bs_rrb_res_dflt[pciio_slot] =
489 pcibr_soft->bs_rrb_res[pciio_slot];
493 /* How many RRBs do we own? */
494 orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0];
495 orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1];
497 /* How many RRBs do we want? */
498 desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
499 desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
501 /* How many RRBs are free? */
502 avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
503 + pcibr_soft->bs_rrb_res[pciio_slot];
505 /* Figure desired deltas */
506 delta_vchan0 = desired_vchan0 - orig_vchan0;
507 delta_vchan1 = desired_vchan1 - orig_vchan1;
509 /* Trim back deltas to something
510 * that we can actually meet, by
511 * decreasing the ending allocation
512 * for whichever channel wants
513 * more RRBs. If both want the same
514 * number, cut the second channel.
515 * NOTE: do not change the allocation for
516 * a channel that was passed as NULL.
518 while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
521 ((orig_vchan0 + delta_vchan0) >
522 (orig_vchan1 + delta_vchan1))))
528 /* Figure final RRB allocations
530 final_vchan0 = orig_vchan0 + delta_vchan0;
531 final_vchan1 = orig_vchan1 + delta_vchan1;
533 /* If either channel wants RRBs but our actions
534 * would leave it with none, declare an error,
535 * but DO NOT change any RRB allocations.
537 if ((desired_vchan0 && !final_vchan0) ||
538 (desired_vchan1 && !final_vchan1)) {
544 /* Commit the allocations: free, then alloc.
546 if (delta_vchan0 < 0)
547 do_pcibr_rrb_free(pcibr_soft, pciio_slot, VCHAN0, -delta_vchan0);
548 if (delta_vchan1 < 0)
549 do_pcibr_rrb_free(pcibr_soft, pciio_slot, VCHAN1, -delta_vchan1);
551 if (delta_vchan0 > 0)
552 do_pcibr_rrb_alloc(pcibr_soft, pciio_slot, VCHAN0, delta_vchan0);
553 if (delta_vchan1 > 0)
554 do_pcibr_rrb_alloc(pcibr_soft, pciio_slot, VCHAN1, delta_vchan1);
556 /* Return final values to caller.
559 *count_vchan0 = final_vchan0;
561 *count_vchan1 = final_vchan1;
563 /* prevent automatic changes to this slot's RRBs
565 pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
567 /* Track the actual allocations, release
568 * any further reservations, and update the
569 * number of available RRBs.
572 pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0] = final_vchan0;
573 pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1] = final_vchan1;
574 pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
575 pcibr_soft->bs_rrb_avail[pciio_slot & 1]
576 + pcibr_soft->bs_rrb_res[pciio_slot]
579 pcibr_soft->bs_rrb_res[pciio_slot] = 0;
582 * Reserve enough RRBs so this slot's RRB configuration can be
583 * reset to its boot-time default following a hot-plug shut-down
585 res_rrbs = (pcibr_soft->bs_rrb_res_dflt[pciio_slot] -
586 pcibr_soft->bs_rrb_res[pciio_slot]);
587 for (vchan = 0; vchan < vchan_total; vchan++) {
588 res_rrbs += (pcibr_soft->bs_rrb_valid_dflt[pciio_slot][vchan] -
589 pcibr_soft->bs_rrb_valid[pciio_slot][vchan]);
593 pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs;
594 pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
595 pcibr_soft->bs_rrb_avail[pciio_slot & 1]
599 pcibr_rrb_debug("pcibr_rrb_alloc", pcibr_soft);
604 pcibr_unlock(pcibr_soft, s);
610 * Device driver interface to check the current state
611 * of the RRB allocations.
613 * pconn_vhdl is your PCI connection point (specifies which
614 * PCI bus and which slot).
616 * count_vchan0 points to where to return the number of RRBs
617 * assigned to the primary DMA channel, used by all DMA
618 * that does not explicitly ask for the alternate virtual
621 * count_vchan1 points to where to return the number of RRBs
622 * assigned to the secondary DMA channel, used when
623 * PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
625 * count_reserved points to where to return the number of RRBs
626 * that have been automatically reserved for your device at
627 * startup, but which have not been assigned to a
628 * channel. RRBs must be assigned to a channel to be used;
629 * this can be done either with an explicit pcibr_rrb_alloc
630 * call, or automatically by the infrastructure when a DMA
631 * translation is constructed. Any call to pcibr_rrb_alloc
632 * will release any unassigned reserved RRBs back to the
635 * count_pool points to where to return the number of RRBs
636 * that are currently unassigned and unreserved. This
637 * number can (and will) change as other drivers make calls
638 * to pcibr_rrb_alloc, or automatically allocate RRBs for
639 * DMA beyond their initial reservation.
641 * NULL may be passed for any of the return value pointers
642 * the caller is not interested in.
644 * The return value is "0" if all went well, or "-1" if
645 * there is a problem. Additionally, if the wrong vertex
646 * is passed in, one of the subsidiary support functions
647 * could panic with a "bad pciio fingerprint."
651 pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
657 pciio_info_t pciio_info;
658 pciio_slot_t pciio_slot;
659 pcibr_soft_t pcibr_soft;
663 if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
664 (pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
665 ((pciio_slot = PCIBR_INFO_SLOT_GET_INT(pciio_info)) < PCIBR_NUM_SLOTS(pcibr_soft))) {
667 s = pcibr_lock(pcibr_soft);
671 pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN0];
675 pcibr_soft->bs_rrb_valid[pciio_slot][VCHAN1];
679 pcibr_soft->bs_rrb_res[pciio_slot];
683 pcibr_soft->bs_rrb_avail[pciio_slot & 1];
687 pcibr_unlock(pcibr_soft, s);
693 * pcibr_slot_initial_rrb_alloc
694 * Allocate a default number of rrbs for this slot on
695 * the two channels. This is dictated by the rrb allocation
696 * strategy routine defined per platform.
700 pcibr_slot_initial_rrb_alloc(vertex_hdl_t pcibr_vhdl,
703 pcibr_soft_t pcibr_soft;
704 pcibr_info_h pcibr_infoh;
705 pcibr_info_t pcibr_info;
710 pcibr_soft = pcibr_soft_get(pcibr_vhdl);
715 if (!PCIBR_VALID_SLOT(pcibr_soft, slot))
718 /* How many RRBs are on this slot? */
719 vchan_total = NUMBER_VCHANNELS;
720 for (vchan = 0; vchan < vchan_total; vchan++)
721 chan[vchan] = do_pcibr_rrb_count_valid(pcibr_soft, slot, vchan);
723 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_vhdl,
724 "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d+%d+%d\n",
725 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
726 chan[VCHAN0], chan[VCHAN1], chan[VCHAN2], chan[VCHAN3]));
728 /* Do we really need any?
730 pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
731 pcibr_info = pcibr_infoh[0];
733 * PIC BRINGUP WAR (PV# 856866, 859504, 861476, 861478):
734 * Don't free RRBs we allocated to device[2|3]--vchan3 as
735 * a WAR to those PVs mentioned above. In pcibr_attach2
736 * we allocate RRB0,8,1,9 to device[2|3]--vchan3.
738 if (PCIBR_WAR_ENABLED(PV856866, pcibr_soft) &&
739 (slot == 2 || slot == 3) &&
740 (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
741 !pcibr_soft->bs_slot[slot].has_host) {
743 for (vchan = 0; vchan < 2; vchan++) {
744 do_pcibr_rrb_free(pcibr_soft, slot, vchan, 8);
745 pcibr_soft->bs_rrb_valid[slot][vchan] = 0;
748 pcibr_soft->bs_rrb_valid[slot][3] = chan[3];
753 if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
754 !pcibr_soft->bs_slot[slot].has_host) {
755 do_pcibr_rrb_free_all(pcibr_soft, slot);
757 /* Reserve RRBs for this empty slot for hot-plug */
758 for (vchan = 0; vchan < vchan_total; vchan++)
759 pcibr_soft->bs_rrb_valid[slot][vchan] = 0;
764 for (vchan = 0; vchan < vchan_total; vchan++)
765 pcibr_soft->bs_rrb_valid[slot][vchan] = chan[vchan];
773 * Assign an equal total number of RRBs to all candidate slots,
774 * where the total is the sum of the number of RRBs assigned to
775 * the normal channel, the number of RRBs assigned to the virtual
776 * channels, and the number of RRBs assigned as reserved.
778 * A candidate slot is any existing (populated or empty) slot.
779 * Empty SN1 slots need RRBs to support hot-plug operations.
783 pcibr_initial_rrb(vertex_hdl_t pcibr_vhdl,
784 pciio_slot_t first, pciio_slot_t last)
786 pcibr_soft_t pcibr_soft = pcibr_soft_get(pcibr_vhdl);
795 have[0][0] = have[0][1] = have[0][2] = 0;
796 have[1][0] = have[1][1] = have[1][2] = 0;
799 vchan_total = NUMBER_VCHANNELS;
801 for (slot = pcibr_soft->bs_min_slot;
802 slot < PCIBR_NUM_SLOTS(pcibr_soft); ++slot) {
803 /* Initial RRB management; give back RRBs in all non-existent slots */
804 pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
806 /* Base calculations only on existing slots */
807 if ((slot >= first) && (slot <= last)) {
809 for (vchan = 0; vchan < vchan_total; vchan++)
810 rrb_total += pcibr_soft->bs_rrb_valid[slot][vchan];
813 have[slot & 1][rrb_total]++;
817 /* Initialize even/odd slot available RRB counts */
818 pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(pcibr_soft, 0);
819 pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(pcibr_soft, 1);
822 * Calculate reserved RRBs for slots based on current RRB usage
824 for (eo = 0; eo < 2; eo++) {
825 if ((3 * have[eo][0] + 2 * have[eo][1] + have[eo][2]) <= pcibr_soft->bs_rrb_avail[eo])
827 else if ((2 * have[eo][0] + have[eo][1]) <= pcibr_soft->bs_rrb_avail[eo])
829 else if (have[eo][0] <= pcibr_soft->bs_rrb_avail[eo])
836 /* Assign reserved RRBs to existing slots */
837 for (slot = first; slot <= last; ++slot) {
840 if (pcibr_soft->bs_unused_slot & (1 << slot))
844 for (vchan = 0; vchan < vchan_total; vchan++)
845 rrb_total += pcibr_soft->bs_rrb_valid[slot][vchan];
847 r = res[slot & 1] - (rrb_total);
850 pcibr_soft->bs_rrb_res[slot] = r;
851 pcibr_soft->bs_rrb_avail[slot & 1] -= r;
855 pcibr_rrb_debug("pcibr_initial_rrb", pcibr_soft);
862 * Dump the pcibr_soft_t RRB state variable
865 pcibr_rrb_debug(char *calling_func, pcibr_soft_t pcibr_soft)
869 if (pcibr_debug_mask & PCIBR_DEBUG_RRB) {
870 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
871 "%s: rrbs available, even=%d, odd=%d\n", calling_func,
872 pcibr_soft->bs_rrb_avail[0], pcibr_soft->bs_rrb_avail[1]));
874 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
875 "\tslot\tvchan0\tvchan1\tvchan2\tvchan3\treserved\n"));
877 for (slot=0; slot < PCIBR_NUM_SLOTS(pcibr_soft); slot++) {
878 PCIBR_DEBUG_ALWAYS((PCIBR_DEBUG_RRB, pcibr_soft->bs_vhdl,
879 "\t %d\t %d\t %d\t %d\t %d\t %d\n",
880 PCIBR_DEVICE_TO_SLOT(pcibr_soft, slot),
881 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN0],
882 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN1],
883 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN2],
884 0xFFF & pcibr_soft->bs_rrb_valid[slot][VCHAN3],
885 pcibr_soft->bs_rrb_res[slot]));