2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
22 * Register definitions for Galileo 64120 system controller.
28 #define MSK(n) ((1 << (n)) - 1)
30 /************************************************************************
31 * Register offset addresses
32 ************************************************************************/
34 #define GT_CPU_OFS 0x000
36 #define GT_CPU_OFS 0x000
37 #define GT_SCS10LD_OFS 0x008
38 #define GT_SCS10HD_OFS 0x010
39 #define GT_SCS32LD_OFS 0x018
40 #define GT_SCS32HD_OFS 0x020
41 #define GT_CS20LD_OFS 0x028
42 #define GT_CS20HD_OFS 0x030
43 #define GT_CS3BOOTLD_OFS 0x038
44 #define GT_CS3BOOTHD_OFS 0x040
45 #define GT_PCI0IOLD_OFS 0x048
46 #define GT_PCI0IOHD_OFS 0x050
47 #define GT_PCI0M0LD_OFS 0x058
48 #define GT_PCI0M0HD_OFS 0x060
49 #define GT_ISD_OFS 0x068
50 #define GT_PCI0M1LD_OFS 0x080
51 #define GT_PCI0M1HD_OFS 0x088
52 #define GT_PCI1IOLD_OFS 0x090
53 #define GT_PCI1IOHD_OFS 0x098
54 #define GT_PCI1M0LD_OFS 0x0a0
55 #define GT_PCI1M0HD_OFS 0x0a8
56 #define GT_PCI1M1LD_OFS 0x0b0
57 #define GT_PCI1M1HD_OFS 0x0b8
59 #define GT_SCS0LD_OFS 0x400
60 #define GT_SCS0HD_OFS 0x404
61 #define GT_SCS1LD_OFS 0x408
62 #define GT_SCS1HD_OFS 0x40c
63 #define GT_SCS2LD_OFS 0x410
64 #define GT_SCS2HD_OFS 0x414
65 #define GT_SCS3LD_OFS 0x418
66 #define GT_SCS3HD_OFS 0x41c
67 #define GT_CS0LD_OFS 0x420
68 #define GT_CS0HD_OFS 0x424
69 #define GT_CS1LD_OFS 0x428
70 #define GT_CS1HD_OFS 0x42c
71 #define GT_CS2LD_OFS 0x430
72 #define GT_CS2HD_OFS 0x434
73 #define GT_CS3LD_OFS 0x438
74 #define GT_CS3HD_OFS 0x43c
75 #define GT_BOOTLD_OFS 0x440
76 #define GT_BOOTHD_OFS 0x444
78 #define GT_SDRAM_B0_OFS 0x44c
79 #define GT_SDRAM_CFG_OFS 0x448
80 #define GT_SDRAM_B2_OFS 0x454
81 #define GT_SDRAM_OPMODE_OFS 0x474
82 #define GT_SDRAM_BM_OFS 0x478
83 #define GT_SDRAM_ADDRDECODE_OFS 0x47c
85 #define GT_PCI0_CMD_OFS 0xc00
86 #define GT_PCI0_TOR_OFS 0xc04
87 #define GT_PCI0_BS_SCS10_OFS 0xc08
88 #define GT_PCI0_BS_SCS32_OFS 0xc0c
89 #define GT_INTRCAUSE_OFS 0xc18
90 #define GT_PCI0_IACK_OFS 0xc34
91 #define GT_PCI0_BARE_OFS 0xc3c
92 #define GT_PCI0_CFGADDR_OFS 0xcf8
93 #define GT_PCI0_CFGDATA_OFS 0xcfc
98 /************************************************************************
100 ************************************************************************/
102 #define GT_CPU_ENDIAN_SHF 12
103 #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
104 #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
105 #define GT_CPU_WR_SHF 16
106 #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
107 #define GT_CPU_WR_BIT GT_CPU_WR_MSK
108 #define GT_CPU_WR_DXDXDXDX 0
109 #define GT_CPU_WR_DDDD 1
112 #define GT_CFGADDR_CFGEN_SHF 31
113 #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
114 #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
116 #define GT_CFGADDR_BUSNUM_SHF 16
117 #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
119 #define GT_CFGADDR_DEVNUM_SHF 11
120 #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
122 #define GT_CFGADDR_FUNCNUM_SHF 8
123 #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
125 #define GT_CFGADDR_REGNUM_SHF 2
126 #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
129 #define GT_SDRAM_BM_ORDER_SHF 2
130 #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
131 #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
132 #define GT_SDRAM_BM_ORDER_SUB 1
133 #define GT_SDRAM_BM_ORDER_LIN 0
135 #define GT_SDRAM_BM_RSVD_ALL1 0xFFB
138 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
139 #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
140 #define GT_SDRAM_ADDRDECODE_ADDR_0 0
141 #define GT_SDRAM_ADDRDECODE_ADDR_1 1
142 #define GT_SDRAM_ADDRDECODE_ADDR_2 2
143 #define GT_SDRAM_ADDRDECODE_ADDR_3 3
144 #define GT_SDRAM_ADDRDECODE_ADDR_4 4
145 #define GT_SDRAM_ADDRDECODE_ADDR_5 5
146 #define GT_SDRAM_ADDRDECODE_ADDR_6 6
147 #define GT_SDRAM_ADDRDECODE_ADDR_7 7
150 #define GT_SDRAM_B0_CASLAT_SHF 0
151 #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
152 #define GT_SDRAM_B0_CASLAT_2 1
153 #define GT_SDRAM_B0_CASLAT_3 2
155 #define GT_SDRAM_B0_FTDIS_SHF 2
156 #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
157 #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
159 #define GT_SDRAM_B0_SRASPRCHG_SHF 3
160 #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
161 #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
162 #define GT_SDRAM_B0_SRASPRCHG_2 0
163 #define GT_SDRAM_B0_SRASPRCHG_3 1
165 #define GT_SDRAM_B0_B0COMPAB_SHF 4
166 #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
167 #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
169 #define GT_SDRAM_B0_64BITINT_SHF 5
170 #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
171 #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
172 #define GT_SDRAM_B0_64BITINT_2 0
173 #define GT_SDRAM_B0_64BITINT_4 1
175 #define GT_SDRAM_B0_BW_SHF 6
176 #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
177 #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
178 #define GT_SDRAM_B0_BW_32 0
179 #define GT_SDRAM_B0_BW_64 1
181 #define GT_SDRAM_B0_BLODD_SHF 7
182 #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
183 #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
185 #define GT_SDRAM_B0_PAR_SHF 8
186 #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
187 #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
189 #define GT_SDRAM_B0_BYPASS_SHF 9
190 #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
191 #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
193 #define GT_SDRAM_B0_SRAS2SCAS_SHF 10
194 #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
195 #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
196 #define GT_SDRAM_B0_SRAS2SCAS_2 0
197 #define GT_SDRAM_B0_SRAS2SCAS_3 1
199 #define GT_SDRAM_B0_SIZE_SHF 11
200 #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
201 #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
202 #define GT_SDRAM_B0_SIZE_16M 0
203 #define GT_SDRAM_B0_SIZE_64M 1
205 #define GT_SDRAM_B0_EXTPAR_SHF 12
206 #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
207 #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
209 #define GT_SDRAM_B0_BLEN_SHF 13
210 #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
211 #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
212 #define GT_SDRAM_B0_BLEN_8 0
213 #define GT_SDRAM_B0_BLEN_4 1
216 #define GT_SDRAM_CFG_REFINT_SHF 0
217 #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
219 #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
220 #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
221 #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
223 #define GT_SDRAM_CFG_RMW_SHF 15
224 #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
225 #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
227 #define GT_SDRAM_CFG_NONSTAGREF_SHF 16
228 #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
229 #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
231 #define GT_SDRAM_CFG_DUPCNTL_SHF 19
232 #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
233 #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
235 #define GT_SDRAM_CFG_DUPBA_SHF 20
236 #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
237 #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
239 #define GT_SDRAM_CFG_DUPEOT0_SHF 21
240 #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
241 #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
243 #define GT_SDRAM_CFG_DUPEOT1_SHF 22
244 #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
245 #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
247 #define GT_SDRAM_OPMODE_OP_SHF 0
248 #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
249 #define GT_SDRAM_OPMODE_OP_NORMAL 0
250 #define GT_SDRAM_OPMODE_OP_NOP 1
251 #define GT_SDRAM_OPMODE_OP_PRCHG 2
252 #define GT_SDRAM_OPMODE_OP_MODE 3
253 #define GT_SDRAM_OPMODE_OP_CBR 4
256 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
257 #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
258 #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
260 #define GT_PCI0_BARE_SWSCS32DIS_SHF 1
261 #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
262 #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
264 #define GT_PCI0_BARE_SWSCS10DIS_SHF 2
265 #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
266 #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
268 #define GT_PCI0_BARE_INTIODIS_SHF 3
269 #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
270 #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
272 #define GT_PCI0_BARE_INTMEMDIS_SHF 4
273 #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
274 #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
276 #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
277 #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
278 #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
280 #define GT_PCI0_BARE_CS20DIS_SHF 6
281 #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
282 #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
284 #define GT_PCI0_BARE_SCS32DIS_SHF 7
285 #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
286 #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
288 #define GT_PCI0_BARE_SCS10DIS_SHF 8
289 #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
290 #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
293 #define GT_INTRCAUSE_MASABORT0_SHF 18
294 #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
295 #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
297 #define GT_INTRCAUSE_TARABORT0_SHF 19
298 #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
299 #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
302 #define GT_PCI0_CFGADDR_REGNUM_SHF 2
303 #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
304 #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
305 #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
306 #define GT_PCI0_CFGADDR_DEVNUM_SHF 11
307 #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
308 #define GT_PCI0_CFGADDR_BUSNUM_SHF 16
309 #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
310 #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
311 #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
312 #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
314 #define GT_PCI0_CMD_MBYTESWAP_SHF 0
315 #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
316 #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
317 #define GT_PCI0_CMD_MWORDSWAP_SHF 10
318 #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
319 #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
320 #define GT_PCI0_CMD_SBYTESWAP_SHF 16
321 #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
322 #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
323 #define GT_PCI0_CMD_SWORDSWAP_SHF 11
324 #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
325 #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
328 /************************************************************************
330 ************************************************************************/
332 #define GT_DEF_BASE 0x14000000
333 #define GT_DEF_PCI0_MEM0_BASE 0x12000000
334 #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
335 #define GT_LATTIM_MIN 6 /* Minimum lat */
337 #endif /* #ifndef GT64120_H */