2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
13 #include <linux/config.h>
14 #include <asm/addrspace.h>
16 #include <asm/byteorder.h>
18 #ifdef CONFIG_DECSTATION
19 #include <asm/dec/io.h>
22 #ifdef CONFIG_MIPS_ATLAS
23 #include <asm/mips-boards/io.h>
26 #ifdef CONFIG_MIPS_MALTA
27 #include <asm/mips-boards/io.h>
30 #ifdef CONFIG_MIPS_SEAD
31 #include <asm/mips-boards/io.h>
34 #ifdef CONFIG_SGI_IP22
35 #include <asm/sgi/io.h>
38 #ifdef CONFIG_SGI_IP27
39 #include <asm/sn/io.h>
42 #ifdef CONFIG_SGI_IP32
43 #include <asm/ip32/io.h>
46 #ifdef CONFIG_SIBYTE_SB1xxx_SOC
47 #include <asm/sibyte/io.h>
50 #ifdef CONFIG_SNI_RM200_PCI
54 #ifdef CONFIG_SGI_IP27
55 extern unsigned long bus_to_baddr[256];
57 #define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr))
58 #define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number])
60 #define bus_to_baddr(bus, addr) (addr)
61 #define baddr_to_bus(bus, addr) (addr)
65 * Slowdown I/O port space accesses for antique hardware.
67 #undef CONF_SLOWDOWN_IO
70 * Sane hardware offers swapping of I/O space accesses in hardware; less
71 * sane hardware forces software to fiddle with this ...
73 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
75 #define __ioswab8(x) (x)
77 #ifdef CONFIG_SGI_IP22
79 * IP22 seems braindead enough to swap 16bits values in hardware, but
80 * not 32bits. Go figure... Can't tell without documentation.
82 #define __ioswab16(x) (x)
84 #define __ioswab16(x) swab16(x)
86 #define __ioswab32(x) swab32(x)
90 #define __ioswab8(x) (x)
91 #define __ioswab16(x) (x)
92 #define __ioswab32(x) (x)
97 * Change "struct page" to physical address.
99 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
102 * ioremap - map bus memory into CPU space
103 * @offset: bus address of the memory
104 * @size: size of the resource to map
106 * ioremap performs a platform specific sequence of operations to
107 * make bus memory CPU accessible via the readb/readw/readl/writeb/
108 * writew/writel functions and the other mmio helpers. The returned
109 * address is not guaranteed to be usable directly as a virtual
112 static inline void * ioremap(unsigned long offset, unsigned long size)
114 return (void *) (IO_SPACE_BASE | offset);
118 * ioremap_nocache - map bus memory into CPU space
119 * @offset: bus address of the memory
120 * @size: size of the resource to map
122 * ioremap_nocache performs a platform specific sequence of operations to
123 * make bus memory CPU accessible via the readb/readw/readl/writeb/
124 * writew/writel functions and the other mmio helpers. The returned
125 * address is not guaranteed to be usable directly as a virtual
128 * This version of ioremap ensures that the memory is marked uncachable
129 * on the CPU as well as honouring existing caching rules from things like
130 * the PCI bus. Note that there are other caches and buffers on many
131 * busses. In paticular driver authors should read up on PCI writes
133 * It's useful if some control registers are in such an area and
134 * write combining or read caching is not desirable:
136 static inline void * ioremap_nocache (unsigned long offset, unsigned long size)
138 return (void *) (IO_SPACE_BASE | offset);
141 static inline void iounmap(void *addr)
145 #define readb(addr) (*(volatile unsigned char *)(addr))
146 #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
147 #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
149 #define __raw_readb(addr) (*(volatile unsigned char *)(addr))
150 #define __raw_readw(addr) (*(volatile unsigned short *)(addr))
151 #define __raw_readl(addr) (*(volatile unsigned int *)(addr))
153 #define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (__ioswab8(b)))
154 #define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
155 #define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
157 #define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
158 #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
159 #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
161 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
162 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
163 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
165 /* The ISA versions are supplied by system specific code */
168 * On MIPS I/O ports are memory mapped, so we access them using normal
169 * load/store instructions. mips_io_port_base is the virtual address to
170 * which all ports are being mapped. For sake of efficiency some code
171 * assumes that this is an address that can be loaded with a single lui
172 * instruction, so the lower 16 bits must be zero. Should be true on
173 * on any sane architecture; generic code does not use this assumption.
175 extern const unsigned long mips_io_port_base;
177 #define set_io_port_base(base) \
178 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
180 #define __SLOW_DOWN_IO \
181 __asm__ __volatile__( \
183 : : "r" (mips_io_port_base));
185 #ifdef CONF_SLOWDOWN_IO
186 #ifdef REALLY_SLOW_IO
187 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
189 #define SLOW_DOWN_IO __SLOW_DOWN_IO
196 * virt_to_phys - map virtual addresses to physical
197 * @address: address to remap
199 * The returned physical address is the physical (CPU) mapping for
200 * the memory address given. It is only valid to use this function on
201 * addresses directly mapped or allocated via kmalloc.
203 * This function does not give bus mappings for DMA transfers. In
204 * almost all conceivable cases a device driver should not be using
207 static inline unsigned long virt_to_phys(volatile void * address)
209 return (unsigned long)address - PAGE_OFFSET;
213 * phys_to_virt - map physical address to virtual
214 * @address: address to remap
216 * The returned virtual address is a current CPU mapping for
217 * the memory address given. It is only valid to use this function on
218 * addresses that have a kernel mapping
220 * This function does not handle bus mappings for DMA transfers. In
221 * almost all conceivable cases a device driver should not be using
224 static inline void * phys_to_virt(unsigned long address)
226 return (void *)(address + PAGE_OFFSET);
230 * ISA I/O bus memory addresses are 1:1 with the physical address.
232 static inline unsigned long isa_virt_to_bus(volatile void * address)
234 return PHYSADDR(address);
237 static inline void * isa_bus_to_virt(unsigned long address)
239 return (void *)KSEG0ADDR(address);
243 * However PCI ones are not necessarily 1:1 and therefore these interfaces
244 * are forbidden in portable PCI drivers.
246 * Allow them for x86 for legacy drivers, though.
248 #define virt_to_bus virt_to_phys
249 #define bus_to_virt phys_to_virt
251 /* This is too simpleminded for more sophisticated than dumb hardware ... */
252 #define page_to_bus page_to_phys
255 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
256 * for the processor. This implies the assumption that there is only
257 * one of these busses.
259 extern unsigned long isa_slot_offset;
262 * ISA space is 'always mapped' on currently supported MIPS systems, no need
263 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
264 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
265 * are physical addresses. The following constant pointer can be
266 * used as the IO-area pointer (it can be iounmapped as well, so the
267 * analogy with PCI is quite large):
269 #define __ISA_IO_base ((char *)(isa_slot_offset))
271 #define isa_readb(a) readb(__ISA_IO_base + (a))
272 #define isa_readw(a) readw(__ISA_IO_base + (a))
273 #define isa_readl(a) readl(__ISA_IO_base + (a))
274 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
275 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
276 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
277 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
278 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
279 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
282 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
283 * just copy it. The net code will then do the checksum later.
285 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
288 * check_signature - find BIOS signatures
289 * @io_addr: mmio address to check
290 * @signature: signature block
291 * @length: length of signature
293 * Perform a signature comparison with the mmio address io_addr. This
294 * address should have been obtained by ioremap.
295 * Returns 1 on a match.
297 static inline int check_signature(unsigned long io_addr,
298 const unsigned char *signature, int length)
302 if (readb(io_addr) != *signature)
314 * isa_check_signature - find BIOS signatures
315 * @io_addr: mmio address to check
316 * @signature: signature block
317 * @length: length of signature
319 * Perform a signature comparison with the ISA mmio address io_addr.
320 * Returns 1 on a match.
322 * This function is deprecated. New drivers should use ioremap and
325 #define isa_check_signature(io, s, l) check_signature(i,s,l)
327 #define outb(val,port) \
329 *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
332 #define outw(val,port) \
334 *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
337 #define outl(val,port) \
339 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
342 #define outb_p(val,port) \
344 *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
348 #define outw_p(val,port) \
350 *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
354 #define outl_p(val,port) \
356 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
360 static inline unsigned char inb(unsigned long port)
362 return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
365 static inline unsigned short inw(unsigned long port)
367 return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
370 static inline unsigned int inl(unsigned long port)
372 return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
375 static inline unsigned char inb_p(unsigned long port)
379 __val = *(volatile u8 *)(mips_io_port_base + port);
382 return __ioswab8(__val);
385 static inline unsigned short inw_p(unsigned long port)
389 __val = *(volatile u16 *)(mips_io_port_base + port);
392 return __ioswab16(__val);
395 static inline unsigned int inl_p(unsigned long port)
399 __val = *(volatile u32 *)(mips_io_port_base + port);
401 return __ioswab32(__val);
404 static inline void outsb(unsigned long port, void *addr, unsigned int count)
407 outb(*(u8 *)addr, port);
412 static inline void insb(unsigned long port, void *addr, unsigned int count)
415 *(u8 *)addr = inb(port);
420 static inline void outsw(unsigned long port, void *addr, unsigned int count)
423 outw(*(u16 *)addr, port);
428 static inline void insw(unsigned long port, void *addr, unsigned int count)
431 *(u16 *)addr = inw(port);
436 static inline void outsl(unsigned long port, void *addr, unsigned int count)
439 outl(*(u32 *)addr, port);
444 static inline void insl(unsigned long port, void *addr, unsigned int count)
447 *(u32 *)addr = inl(port);
453 * The caches on some architectures aren't dma-coherent and have need to
454 * handle this in software. There are three types of operations that
455 * can be applied to dma buffers.
457 * - dma_cache_wback_inv(start, size) makes caches and coherent by
458 * writing the content of the caches back to memory, if necessary.
459 * The function also invalidates the affected part of the caches as
460 * necessary before DMA transfers from outside to memory.
461 * - dma_cache_wback(start, size) makes caches and coherent by
462 * writing the content of the caches back to memory, if necessary.
463 * The function also invalidates the affected part of the caches as
464 * necessary before DMA transfers from outside to memory.
465 * - dma_cache_inv(start, size) invalidates the affected parts of the
466 * caches. Dirty lines of the caches may be written back or simply
467 * be discarded. This operation is necessary before dma operations
470 #ifdef CONFIG_NONCOHERENT_IO
472 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
473 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
474 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
476 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
477 #define dma_cache_wback(start,size) _dma_cache_wback(start,size)
478 #define dma_cache_inv(start,size) _dma_cache_inv(start,size)
480 #else /* Sane hardware */
482 #define dma_cache_wback_inv(start,size) \
483 do { (void) (start); (void) (size); } while (0)
484 #define dma_cache_wback(start,size) \
485 do { (void) (start); (void) (size); } while (0)
486 #define dma_cache_inv(start,size) \
487 do { (void) (start); (void) (size); } while (0)
489 #endif /* CONFIG_NONCOHERENT_IO */
491 #endif /* _ASM_IO_H */