2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999 by Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics
8 * Copyright (C) 2002 Maciej W. Rozycki
10 * Low level exception handling
12 #include <linux/init.h>
14 #include <asm/regdef.h>
15 #include <asm/fpregdef.h>
16 #include <asm/mipsregs.h>
17 #include <asm/stackframe.h>
18 #include <asm/exception.h>
19 #include <asm/cacheops.h>
21 BUILD_HANDLER adel ade ade silent /* #4 */
22 BUILD_HANDLER ades ade ade silent /* #5 */
23 BUILD_HANDLER ibe be cli silent /* #6 */
24 BUILD_HANDLER dbe be cli silent /* #7 */
25 BUILD_HANDLER bp bp sti silent /* #9 */
26 BUILD_HANDLER ri ri sti silent /* #10 */
27 BUILD_HANDLER cpu cpu sti silent /* #11 */
28 BUILD_HANDLER ov ov sti silent /* #12 */
29 BUILD_HANDLER tr tr sti silent /* #13 */
30 BUILD_HANDLER fpe fpe fpe silent /* #15 */
31 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
32 BUILD_HANDLER watch watch sti verbose /* #23 */
33 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
34 BUILD_HANDLER reserved reserved sti verbose /* others */
39 /* A temporary overflow handler used by check_daddi(). */
41 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
44 /* General exception handler for CPUs with virtual coherency exception.
46 * Be careful when changing this, it has to be at most 256 (as a special
47 * exception) bytes to fit into space reserved for the exception handler.
51 NESTED(except_vec3_r4000, 0, sp)
58 beq k1, k0, handle_vced
60 beq k1, k0, handle_vcei
63 ld k0, exception_handlers(k1)
67 * Big shit, we now may have two dirty primary cache lines for the same
68 * physical address. We can savely invalidate the line pointed to by
69 * c0_badvaddr because after return from this exception handler the load /
70 * store will be re-executed.
73 dmfc0 k0, CP0_BADVADDR
74 li k1, -4 # Is this ...
75 and k0, k1 # ... really needed?
77 cache Index_Store_Tag_D,(k0)
78 cache Hit_Writeback_Inv_SD,(k0)
86 dmfc0 k0, CP0_BADVADDR
87 cache Hit_Writeback_Inv_SD,(k0) # also cleans pi
93 END(except_vec3_r4000)
97 /* General exception vector for all other CPUs.
99 * Be careful when changing this, it has to be at most 128 bytes
100 * to fit into space reserved for the exception handler.
104 NESTED(except_vec3_generic, 0, sp)
105 #if R5432_CP0_INTERRUPT_WAR
111 ld k0, exception_handlers(k1)
113 END(except_vec3_generic)
118 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
119 * This is a dedicated interrupt exception vector which reduces the
120 * interrupt processing overhead. The jump instruction will be replaced
121 * at the initialization time.
123 * Be careful when changing this, it has to be at most 128 bytes
124 * to fit into space reserved for the exception handler.
126 NESTED(except_vec4, 0, sp)
127 1: j 1b /* Dummy, will be replaced */
131 * EJTAG debug exception handler.
132 * The EJTAG debug exception entry point is 0xbfc00480, which
133 * normally is in the boot PROM, so the boot PROM must do a
134 * unconditional jump to this vector.
136 NESTED(except_vec_ejtag_debug, 0, sp)
137 j ejtag_debug_handler
139 END(except_vec_ejtag_debug)
144 * EJTAG debug exception handler.
146 NESTED(ejtag_debug_handler, PT_SIZE, sp)
152 sll k0, k0, 30 # Check for SDBBP.
153 bgez k0, ejtag_return
155 la k0, ejtag_debug_buffer
158 jal ejtag_exception_handler
161 la k0, ejtag_debug_buffer
171 END(ejtag_debug_handler)
174 * This buffer is reserved for the use of the EJTAG debug
178 EXPORT(ejtag_debug_buffer)