2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Head.S contains the MIPS exception handler and startup code.
8 * Copyright (C) 1994, 1995 Waldorf Electronics
9 * Written by Ralf Baechle and Andreas Busse
10 * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999 Ralf Baechle
11 * Copyright (C) 1999 Silicon Graphics, Inc.
13 #include <linux/config.h>
14 #include <linux/init.h>
16 #include <asm/regdef.h>
17 #include <asm/processor.h>
18 #include <asm/mipsregs.h>
19 #include <asm/stackframe.h>
20 #include <asm/pgtable.h>
21 #include <asm/sn/addrs.h>
22 #include <asm/sn/sn0/hubni.h>
23 #include <asm/sn/klkernvars.h>
25 .macro ARC64_TWIDDLE_PC
26 #if defined(CONFIG_ARC64) || defined(CONFIG_MAPPED_KERNEL)
27 /* We get launched at a XKPHYS address but the kernel is linked to
28 run at a KSEG0 address, so jump there. */
35 #ifdef CONFIG_SGI_IP27
37 * outputs the local nasid into res. IP27 stuff.
39 .macro GET_NASID_ASM res
40 dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
42 and \res, NSRI_NODEID_MASK
43 dsrl \res, NSRI_NODEID_SHFT
45 #endif /* CONFIG_SGI_IP27 */
48 * inputs are the text nasid in t1, data nasid in t2.
50 .macro MAPPED_KERNEL_SETUP_TLB
51 #ifdef CONFIG_MAPPED_KERNEL
53 * This needs to read the nasid - assume 0 for now.
54 * Drop in 0xffffffffc0000000 in tlbhi, 0+VG in tlblo_0,
57 dli t0, 0xffffffffc0000000
59 li t0, 0x1c000 # Offset of text into node memory
60 dsll t1, NASID_SHFT # Shift text nasid into place
61 dsll t2, NASID_SHFT # Same for data nasid
62 or t1, t1, t0 # Physical load address of kernel text
63 or t2, t2, t0 # Physical load address of kernel data
66 dsll t1, 6 # Get pfn into place
67 dsll t2, 6 # Get pfn into place
68 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _CACHE_CACHABLE_COW) >> 6)
70 mtc0 t0, CP0_ENTRYLO0 # physaddr, VG, cach exlwr
71 li t0, ((_PAGE_GLOBAL|_PAGE_VALID| _PAGE_DIRTY|_CACHE_CACHABLE_COW) >> 6)
73 mtc0 t0, CP0_ENTRYLO1 # physaddr, DVG, cach exlwr
74 li t0, 0x1ffe000 # MAPPED_KERN_TLBMASK, TLBPGMASK_16M
88 EXPORT(stext) # used for profiling
93 NESTED(kernel_entry, 16, sp) # kernel entry point
95 ori sp, 0xf # align stack on 16 byte.
98 #ifdef CONFIG_SGI_IP27
100 move t2, t1 # text and data are here
101 MAPPED_KERNEL_SETUP_TLB
106 CLI # disable interrupts
108 PTR_LA $28, init_thread_union # init current pointer
109 daddiu sp, $28, KERNEL_STACK_SIZE-32
110 set_saved_sp sp, t0, t1
113 * The firmware/bootloader passes argc/argp/envp
114 * to us as arguments. But clear bss first because
115 * the romvec and other important info is stored there
118 PTR_LA t0, __bss_start
120 PTR_LA t1, __bss_stop - 8
126 dsubu sp, 4*SZREG # init stack pointer
133 * SMP slave cpus entry point. Board specific code for bootstrap calls this
134 * function after setting up the stack and gp registers.
136 NESTED(smp_bootstrap, 16, sp)
137 #ifdef CONFIG_SGI_IP27
139 li t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
140 KLDIR_OFF_POINTER + K0BASE
143 ld t0, 0(t0) # t0 points to kern_vars struct
144 lh t1, KV_RO_NASID_OFFSET(t0)
145 lh t2, KV_RW_NASID_OFFSET(t0)
146 MAPPED_KERNEL_SETUP_TLB
148 #endif /* CONFIG_SGI_IP27 */
153 * For the moment set ST0_KU so the CPU will not spit fire when
154 * executing 64-bit instructions. The full initialization of the
155 * CPU's status register is done later in per_cpu_trap_init().
164 #endif /* CONFIG_SMP */
171 #define PAGE_SIZE 0x1000
173 .macro page name, order=0
175 \name: .size \name, (PAGE_SIZE << \order)
176 .org . + (PAGE_SIZE << \order)
183 page swapper_pg_dir, 1
184 page invalid_pte_table, 0
185 page invalid_pmd_table, 1
186 page kptbl, _PGD_ORDER