drivers/i2c/busses/i2c-eg20t.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/i2c.h>
  24 #include <linux/fs.h>
  25 #include <linux/io.h>
  26 #include <linux/types.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/jiffies.h>
  29 #include <linux/pci.h>
  30 #include <linux/mutex.h>
  31 #include <linux/ktime.h>
  32 #include <linux/slab.h>
  33
  34 #define PCH_EVENT_SET   0       /* I2C Interrupt Event Set Status */
  35 #define PCH_EVENT_NONE  1       /* I2C Interrupt Event Clear Status */
  36 #define PCH_MAX_CLK             100000  /* Maximum Clock speed in MHz */
  37 #define PCH_BUFFER_MODE_ENABLE  0x0002  /* flag for Buffer mode enable */
  38 #define PCH_EEPROM_SW_RST_MODE_ENABLE   0x0008  /* EEPROM SW RST enable flag */
  39
  40 #define PCH_I2CSADR     0x00    /* I2C slave address register */
  41 #define PCH_I2CCTL      0x04    /* I2C control register */
  42 #define PCH_I2CSR       0x08    /* I2C status register */
  43 #define PCH_I2CDR       0x0C    /* I2C data register */
  44 #define PCH_I2CMON      0x10    /* I2C bus monitor register */
  45 #define PCH_I2CBC       0x14    /* I2C bus transfer rate setup counter */
  46 #define PCH_I2CMOD      0x18    /* I2C mode register */
  47 #define PCH_I2CBUFSLV   0x1C    /* I2C buffer mode slave address register */
  48 #define PCH_I2CBUFSUB   0x20    /* I2C buffer mode subaddress register */
  49 #define PCH_I2CBUFFOR   0x24    /* I2C buffer mode format register */
  50 #define PCH_I2CBUFCTL   0x28    /* I2C buffer mode control register */
  51 #define PCH_I2CBUFMSK   0x2C    /* I2C buffer mode interrupt mask register */
  52 #define PCH_I2CBUFSTA   0x30    /* I2C buffer mode status register */
  53 #define PCH_I2CBUFLEV   0x34    /* I2C buffer mode level register */
  54 #define PCH_I2CESRFOR   0x38    /* EEPROM software reset mode format register */
  55 #define PCH_I2CESRCTL   0x3C    /* EEPROM software reset mode ctrl register */
  56 #define PCH_I2CESRMSK   0x40    /* EEPROM software reset mode */
  57 #define PCH_I2CESRSTA   0x44    /* EEPROM software reset mode status register */
  58 #define PCH_I2CTMR      0x48    /* I2C timer register */
  59 #define PCH_I2CSRST     0xFC    /* I2C reset register */
  60 #define PCH_I2CNF       0xF8    /* I2C noise filter register */
  61
  62 #define BUS_IDLE_TIMEOUT        20
  63 #define PCH_I2CCTL_I2CMEN       0x0080
  64 #define TEN_BIT_ADDR_DEFAULT    0xF000
  65 #define TEN_BIT_ADDR_MASK       0xF0
  66 #define PCH_START               0x0020
  67 #define PCH_RESTART             0x0004
  68 #define PCH_ESR_START           0x0001
  69 #define PCH_BUFF_START          0x1
  70 #define PCH_REPSTART            0x0004
  71 #define PCH_ACK                 0x0008
  72 #define PCH_GETACK              0x0001
  73 #define CLR_REG                 0x0
  74 #define I2C_RD                  0x1
  75 #define I2CMCF_BIT              0x0080
  76 #define I2CMIF_BIT              0x0002
  77 #define I2CMAL_BIT              0x0010
  78 #define I2CBMFI_BIT             0x0001
  79 #define I2CBMAL_BIT             0x0002
  80 #define I2CBMNA_BIT             0x0004
  81 #define I2CBMTO_BIT             0x0008
  82 #define I2CBMIS_BIT             0x0010
  83 #define I2CESRFI_BIT            0X0001
  84 #define I2CESRTO_BIT            0x0002
  85 #define I2CESRFIIE_BIT          0x1
  86 #define I2CESRTOIE_BIT          0x2
  87 #define I2CBMDZ_BIT             0x0040
  88 #define I2CBMAG_BIT             0x0020
  89 #define I2CMBB_BIT              0x0020
  90 #define BUFFER_MODE_MASK        (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  91                                 I2CBMTO_BIT | I2CBMIS_BIT)
  92 #define I2C_ADDR_MSK            0xFF
  93 #define I2C_MSB_2B_MSK          0x300
  94 #define FAST_MODE_CLK           400
  95 #define FAST_MODE_EN            0x0001
  96 #define SUB_ADDR_LEN_MAX        4
  97 #define BUF_LEN_MAX             32
  98 #define PCH_BUFFER_MODE         0x1
  99 #define EEPROM_SW_RST_MODE      0x0002
 100 #define NORMAL_INTR_ENBL        0x0300
 101 #define EEPROM_RST_INTR_ENBL    (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
 102 #define EEPROM_RST_INTR_DISBL   0x0
 103 #define BUFFER_MODE_INTR_ENBL   0x001F
 104 #define BUFFER_MODE_INTR_DISBL  0x0
 105 #define NORMAL_MODE             0x0
 106 #define BUFFER_MODE             0x1
 107 #define EEPROM_SR_MODE          0x2
 108 #define I2C_TX_MODE             0x0010
 109 #define PCH_BUF_TX              0xFFF7
 110 #define PCH_BUF_RD              0x0008
 111 #define I2C_ERROR_MASK  (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
 112                         I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
 113 #define I2CMAL_EVENT            0x0001
 114 #define I2CMCF_EVENT            0x0002
 115 #define I2CBMFI_EVENT           0x0004
 116 #define I2CBMAL_EVENT           0x0008
 117 #define I2CBMNA_EVENT           0x0010
 118 #define I2CBMTO_EVENT           0x0020
 119 #define I2CBMIS_EVENT           0x0040
 120 #define I2CESRFI_EVENT          0x0080
 121 #define I2CESRTO_EVENT          0x0100
 122 #define PCI_DEVICE_ID_PCH_I2C   0x8817
 123
 124 #define pch_dbg(adap, fmt, arg...)  \
 125         dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 126
 127 #define pch_err(adap, fmt, arg...)  \
 128         dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
 129
 130 #define pch_pci_err(pdev, fmt, arg...)  \
 131         dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
 132
 133 #define pch_pci_dbg(pdev, fmt, arg...)  \
 134         dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
 135
 136 /*
 137 Set the number of I2C instance max
 138 Intel EG20T PCH :               1ch
 139 LAPIS Semiconductor ML7213 IOH :        2ch
 140 LAPIS Semiconductor ML7831 IOH :        1ch
 141 */
 142 #define PCH_I2C_MAX_DEV                 2
 143
 144 /**
 145  * struct i2c_algo_pch_data - for I2C driver functionalities
 146  * @pch_adapter:                stores the reference to i2c_adapter structure
 147  * @p_adapter_info:             stores the reference to adapter_info structure
 148  * @pch_base_address:           specifies the remapped base address
 149  * @pch_buff_mode_en:           specifies if buffer mode is enabled
 150  * @pch_event_flag:             specifies occurrence of interrupt events
 151  * @pch_i2c_xfer_in_progress:   specifies whether the transfer is completed
 152  */
 153 struct i2c_algo_pch_data {
 154         struct i2c_adapter pch_adapter;
 155         struct adapter_info *p_adapter_info;
 156         void __iomem *pch_base_address;
 157         int pch_buff_mode_en;
 158         u32 pch_event_flag;
 159         bool pch_i2c_xfer_in_progress;
 160 };
 161
 162 /**
 163  * struct adapter_info - This structure holds the adapter information for the
 164                          PCH i2c controller
 165  * @pch_data:           stores a list of i2c_algo_pch_data
 166  * @pch_i2c_suspended:  specifies whether the system is suspended or not
 167  *                      perhaps with more lines and words.
 168  * @ch_num:             specifies the number of i2c instance
 169  *
 170  * pch_data has as many elements as maximum I2C channels
 171  */
 172 struct adapter_info {
 173         struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
 174         bool pch_i2c_suspended;
 175         int ch_num;
 176 };
 177
 178
 179 static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
 180 static int pch_clk = 50000;     /* specifies I2C clock speed in KHz */
 181 static wait_queue_head_t pch_event;
 182 static DEFINE_MUTEX(pch_mutex);
 183
 184 /* Definition for ML7213 by LAPIS Semiconductor */
 185 #define PCI_VENDOR_ID_ROHM              0x10DB
 186 #define PCI_DEVICE_ID_ML7213_I2C        0x802D
 187 #define PCI_DEVICE_ID_ML7223_I2C        0x8010
 188 #define PCI_DEVICE_ID_ML7831_I2C        0x8817
 189
 190 static DEFINE_PCI_DEVICE_TABLE(pch_pcidev_id) = {
 191         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C),   1, },
 192         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
 193         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
 194         { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
 195         {0,}
 196 };
 197
 198 static irqreturn_t pch_i2c_handler(int irq, void *pData);
 199
 200 static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
 201 {
 202         u32 val;
 203         val = ioread32(addr + offset);
 204         val |= bitmask;
 205         iowrite32(val, addr + offset);
 206 }
 207
 208 static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
 209 {
 210         u32 val;
 211         val = ioread32(addr + offset);
 212         val &= (~bitmask);
 213         iowrite32(val, addr + offset);
 214 }
 215
 216 /**
 217  * pch_i2c_init() - hardware initialization of I2C module
 218  * @adap:       Pointer to struct i2c_algo_pch_data.
 219  */
 220 static void pch_i2c_init(struct i2c_algo_pch_data *adap)
 221 {
 222         void __iomem *p = adap->pch_base_address;
 223         u32 pch_i2cbc;
 224         u32 pch_i2ctmr;
 225         u32 reg_value;
 226
 227         /* reset I2C controller */
 228         iowrite32(0x01, p + PCH_I2CSRST);
 229         msleep(20);
 230         iowrite32(0x0, p + PCH_I2CSRST);
 231
 232         /* Initialize I2C registers */
 233         iowrite32(0x21, p + PCH_I2CNF);
 234
 235         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
 236
 237         if (pch_i2c_speed != 400)
 238                 pch_i2c_speed = 100;
 239
 240         reg_value = PCH_I2CCTL_I2CMEN;
 241         if (pch_i2c_speed == FAST_MODE_CLK) {
 242                 reg_value |= FAST_MODE_EN;
 243                 pch_dbg(adap, "Fast mode enabled\n");
 244         }
 245
 246         if (pch_clk > PCH_MAX_CLK)
 247                 pch_clk = 62500;
 248
 249         pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
 250         /* Set transfer speed in I2CBC */
 251         iowrite32(pch_i2cbc, p + PCH_I2CBC);
 252
 253         pch_i2ctmr = (pch_clk) / 8;
 254         iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
 255
 256         reg_value |= NORMAL_INTR_ENBL;  /* Enable interrupts in normal mode */
 257         iowrite32(reg_value, p + PCH_I2CCTL);
 258
 259         pch_dbg(adap,
 260                 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
 261                 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
 262
 263         init_waitqueue_head(&pch_event);
 264 }
 265
 266 static inline bool ktime_lt(const ktime_t cmp1, const ktime_t cmp2)
 267 {
 268         return cmp1.tv64 < cmp2.tv64;
 269 }
 270
 271 /**
 272  * pch_i2c_wait_for_bus_idle() - check the status of bus.
 273  * @adap:       Pointer to struct i2c_algo_pch_data.
 274  * @timeout:    waiting time counter (ms).
 275  */
 276 static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
 277                                      s32 timeout)
 278 {
 279         void __iomem *p = adap->pch_base_address;
 280         int schedule = 0;
 281         unsigned long end = jiffies + msecs_to_jiffies(timeout);
 282
 283         while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
 284                 if (time_after(jiffies, end)) {
 285                         pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 286                         pch_err(adap, "%s: Timeout Error.return%d\n",
 287                                         __func__, -ETIME);
 288                         pch_i2c_init(adap);
 289
 290                         return -ETIME;
 291                 }
 292
 293                 if (!schedule)
 294                         /* Retry after some usecs */
 295                         udelay(5);
 296                 else
 297                         /* Wait a bit more without consuming CPU */
 298                         usleep_range(20, 1000);
 299
 300                 schedule = 1;
 301         }
 302
 303         return 0;
 304 }
 305
 306 /**
 307  * pch_i2c_start() - Generate I2C start condition in normal mode.
 308  * @adap:       Pointer to struct i2c_algo_pch_data.
 309  *
 310  * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
 311  */
 312 static void pch_i2c_start(struct i2c_algo_pch_data *adap)
 313 {
 314         void __iomem *p = adap->pch_base_address;
 315         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 316         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 317 }
 318
 319 /**
 320  * pch_i2c_wait_for_xfer_complete() - initiates a wait for the tx complete event
 321  * @adap:       Pointer to struct i2c_algo_pch_data.
 322  */
 323 static s32 pch_i2c_wait_for_xfer_complete(struct i2c_algo_pch_data *adap)
 324 {
 325         long ret;
 326         ret = wait_event_timeout(pch_event,
 327                         (adap->pch_event_flag != 0), msecs_to_jiffies(50));
 328
 329         if (ret == 0) {
 330                 pch_err(adap, "timeout: %x\n", adap->pch_event_flag);
 331                 adap->pch_event_flag = 0;
 332                 return -ETIMEDOUT;
 333         }
 334
 335         if (adap->pch_event_flag & I2C_ERROR_MASK) {
 336                 pch_err(adap, "error bits set: %x\n", adap->pch_event_flag);
 337                 adap->pch_event_flag = 0;
 338                 return -EIO;
 339         }
 340
 341         adap->pch_event_flag = 0;
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * pch_i2c_getack() - to confirm ACK/NACK
 348  * @adap:       Pointer to struct i2c_algo_pch_data.
 349  */
 350 static s32 pch_i2c_getack(struct i2c_algo_pch_data *adap)
 351 {
 352         u32 reg_val;
 353         void __iomem *p = adap->pch_base_address;
 354         reg_val = ioread32(p + PCH_I2CSR) & PCH_GETACK;
 355
 356         if (reg_val != 0) {
 357                 pch_err(adap, "return%d\n", -EPROTO);
 358                 return -EPROTO;
 359         }
 360
 361         return 0;
 362 }
 363
 364 /**
 365  * pch_i2c_stop() - generate stop condition in normal mode.
 366  * @adap:       Pointer to struct i2c_algo_pch_data.
 367  */
 368 static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
 369 {
 370         void __iomem *p = adap->pch_base_address;
 371         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 372         /* clear the start bit */
 373         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
 374 }
 375
 376 /**
 377  * pch_i2c_repstart() - generate repeated start condition in normal mode
 378  * @adap:       Pointer to struct i2c_algo_pch_data.
 379  */
 380 static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
 381 {
 382         void __iomem *p = adap->pch_base_address;
 383         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 384         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
 385 }
 386
 387 /**
 388  * pch_i2c_writebytes() - write data to I2C bus in normal mode
 389  * @i2c_adap:   Pointer to the struct i2c_adapter.
 390  * @last:       specifies whether last message or not.
 391  *              In the case of compound mode it will be 1 for last message,
 392  *              otherwise 0.
 393  * @first:      specifies whether first message or not.
 394  *              1 for first message otherwise 0.
 395  */
 396 static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
 397                               struct i2c_msg *msgs, u32 last, u32 first)
 398 {
 399         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 400         u8 *buf;
 401         u32 length;
 402         u32 addr;
 403         u32 addr_2_msb;
 404         u32 addr_8_lsb;
 405         s32 wrcount;
 406         s32 rtn;
 407         void __iomem *p = adap->pch_base_address;
 408
 409         length = msgs->len;
 410         buf = msgs->buf;
 411         addr = msgs->addr;
 412
 413         /* enable master tx */
 414         pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 415
 416         pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
 417                 length);
 418
 419         if (first) {
 420                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 421                         return -ETIME;
 422         }
 423
 424         if (msgs->flags & I2C_M_TEN) {
 425                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
 426                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 427                 if (first)
 428                         pch_i2c_start(adap);
 429
 430                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 431                 if (rtn == 0) {
 432                         if (pch_i2c_getack(adap)) {
 433                                 pch_dbg(adap, "Receive NACK for slave address"
 434                                         "setting\n");
 435                                 return -EIO;
 436                         }
 437                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 438                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 439                 } else if (rtn == -EIO) { /* Arbitration Lost */
 440                         pch_err(adap, "Lost Arbitration\n");
 441                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 442                                    I2CMAL_BIT);
 443                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 444                                    I2CMIF_BIT);
 445                         pch_i2c_init(adap);
 446                         return -EAGAIN;
 447                 } else { /* wait-event timeout */
 448                         pch_i2c_stop(adap);
 449                         return -ETIME;
 450                 }
 451         } else {
 452                 /* set 7 bit slave address and R/W bit as 0 */
 453                 iowrite32(addr << 1, p + PCH_I2CDR);
 454                 if (first)
 455                         pch_i2c_start(adap);
 456         }
 457
 458         rtn = pch_i2c_wait_for_xfer_complete(adap);
 459         if (rtn == 0) {
 460                 if (pch_i2c_getack(adap)) {
 461                         pch_dbg(adap, "Receive NACK for slave address"
 462                                 "setting\n");
 463                         return -EIO;
 464                 }
 465         } else if (rtn == -EIO) { /* Arbitration Lost */
 466                 pch_err(adap, "Lost Arbitration\n");
 467                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 468                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 469                 pch_i2c_init(adap);
 470                 return -EAGAIN;
 471         } else { /* wait-event timeout */
 472                 pch_i2c_stop(adap);
 473                 return -ETIME;
 474         }
 475
 476         for (wrcount = 0; wrcount < length; ++wrcount) {
 477                 /* write buffer value to I2C data register */
 478                 iowrite32(buf[wrcount], p + PCH_I2CDR);
 479                 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
 480
 481                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 482                 if (rtn == 0) {
 483                         if (pch_i2c_getack(adap)) {
 484                                 pch_dbg(adap, "Receive NACK for slave address"
 485                                         "setting\n");
 486                                 return -EIO;
 487                         }
 488                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 489                                    I2CMCF_BIT);
 490                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 491                                    I2CMIF_BIT);
 492                 } else { /* wait-event timeout */
 493                         pch_i2c_stop(adap);
 494                         return -ETIME;
 495                 }
 496         }
 497
 498         /* check if this is the last message */
 499         if (last)
 500                 pch_i2c_stop(adap);
 501         else
 502                 pch_i2c_repstart(adap);
 503
 504         pch_dbg(adap, "return=%d\n", wrcount);
 505
 506         return wrcount;
 507 }
 508
 509 /**
 510  * pch_i2c_sendack() - send ACK
 511  * @adap:       Pointer to struct i2c_algo_pch_data.
 512  */
 513 static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
 514 {
 515         void __iomem *p = adap->pch_base_address;
 516         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 517         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 518 }
 519
 520 /**
 521  * pch_i2c_sendnack() - send NACK
 522  * @adap:       Pointer to struct i2c_algo_pch_data.
 523  */
 524 static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
 525 {
 526         void __iomem *p = adap->pch_base_address;
 527         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 528         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
 529 }
 530
 531 /**
 532  * pch_i2c_restart() - Generate I2C restart condition in normal mode.
 533  * @adap:       Pointer to struct i2c_algo_pch_data.
 534  *
 535  * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
 536  */
 537 static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
 538 {
 539         void __iomem *p = adap->pch_base_address;
 540         pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
 541         pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
 542 }
 543
 544 /**
 545  * pch_i2c_readbytes() - read data  from I2C bus in normal mode.
 546  * @i2c_adap:   Pointer to the struct i2c_adapter.
 547  * @msgs:       Pointer to i2c_msg structure.
 548  * @last:       specifies whether last message or not.
 549  * @first:      specifies whether first message or not.
 550  */
 551 static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
 552                              u32 last, u32 first)
 553 {
 554         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 555
 556         u8 *buf;
 557         u32 count;
 558         u32 length;
 559         u32 addr;
 560         u32 addr_2_msb;
 561         u32 addr_8_lsb;
 562         void __iomem *p = adap->pch_base_address;
 563         s32 rtn;
 564
 565         length = msgs->len;
 566         buf = msgs->buf;
 567         addr = msgs->addr;
 568
 569         /* enable master reception */
 570         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
 571
 572         if (first) {
 573                 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
 574                         return -ETIME;
 575         }
 576
 577         if (msgs->flags & I2C_M_TEN) {
 578                 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
 579                 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
 580                 if (first)
 581                         pch_i2c_start(adap);
 582
 583                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 584                 if (rtn == 0) {
 585                         if (pch_i2c_getack(adap)) {
 586                                 pch_dbg(adap, "Receive NACK for slave address"
 587                                         "setting\n");
 588                                 return -EIO;
 589                         }
 590                         addr_8_lsb = (addr & I2C_ADDR_MSK);
 591                         iowrite32(addr_8_lsb, p + PCH_I2CDR);
 592                 } else if (rtn == -EIO) { /* Arbitration Lost */
 593                         pch_err(adap, "Lost Arbitration\n");
 594                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 595                                    I2CMAL_BIT);
 596                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 597                                    I2CMIF_BIT);
 598                         pch_i2c_init(adap);
 599                         return -EAGAIN;
 600                 } else { /* wait-event timeout */
 601                         pch_i2c_stop(adap);
 602                         return -ETIME;
 603                 }
 604                 pch_i2c_restart(adap);
 605                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 606                 if (rtn == 0) {
 607                         if (pch_i2c_getack(adap)) {
 608                                 pch_dbg(adap, "Receive NACK for slave address"
 609                                         "setting\n");
 610                                 return -EIO;
 611                         }
 612                         addr_2_msb |= I2C_RD;
 613                         iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK,
 614                                   p + PCH_I2CDR);
 615                 } else if (rtn == -EIO) { /* Arbitration Lost */
 616                         pch_err(adap, "Lost Arbitration\n");
 617                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 618                                    I2CMAL_BIT);
 619                         pch_clrbit(adap->pch_base_address, PCH_I2CSR,
 620                                    I2CMIF_BIT);
 621                         pch_i2c_init(adap);
 622                         return -EAGAIN;
 623                 } else { /* wait-event timeout */
 624                         pch_i2c_stop(adap);
 625                         return -ETIME;
 626                 }
 627         } else {
 628                 /* 7 address bits + R/W bit */
 629                 addr = (((addr) << 1) | (I2C_RD));
 630                 iowrite32(addr, p + PCH_I2CDR);
 631         }
 632
 633         /* check if it is the first message */
 634         if (first)
 635                 pch_i2c_start(adap);
 636
 637         rtn = pch_i2c_wait_for_xfer_complete(adap);
 638         if (rtn == 0) {
 639                 if (pch_i2c_getack(adap)) {
 640                         pch_dbg(adap, "Receive NACK for slave address"
 641                                 "setting\n");
 642                         return -EIO;
 643                 }
 644         } else if (rtn == -EIO) { /* Arbitration Lost */
 645                 pch_err(adap, "Lost Arbitration\n");
 646                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
 647                 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
 648                 pch_i2c_init(adap);
 649                 return -EAGAIN;
 650         } else { /* wait-event timeout */
 651                 pch_i2c_stop(adap);
 652                 return -ETIME;
 653         }
 654
 655         if (length == 0) {
 656                 pch_i2c_stop(adap);
 657                 ioread32(p + PCH_I2CDR); /* Dummy read needs */
 658
 659                 count = length;
 660         } else {
 661                 int read_index;
 662                 int loop;
 663                 pch_i2c_sendack(adap);
 664
 665                 /* Dummy read */
 666                 for (loop = 1, read_index = 0; loop < length; loop++) {
 667                         buf[read_index] = ioread32(p + PCH_I2CDR);
 668
 669                         if (loop != 1)
 670                                 read_index++;
 671
 672                         rtn = pch_i2c_wait_for_xfer_complete(adap);
 673                         if (rtn == 0) {
 674                                 if (pch_i2c_getack(adap)) {
 675                                         pch_dbg(adap, "Receive NACK for slave"
 676                                                 "address setting\n");
 677                                         return -EIO;
 678                                 }
 679                         } else { /* wait-event timeout */
 680                                 pch_i2c_stop(adap);
 681                                 return -ETIME;
 682                         }
 683
 684                 }       /* end for */
 685
 686                 pch_i2c_sendnack(adap);
 687
 688                 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
 689
 690                 if (length != 1)
 691                         read_index++;
 692
 693                 rtn = pch_i2c_wait_for_xfer_complete(adap);
 694                 if (rtn == 0) {
 695                         if (pch_i2c_getack(adap)) {
 696                                 pch_dbg(adap, "Receive NACK for slave"
 697                                         "address setting\n");
 698                                 return -EIO;
 699                         }
 700                 } else { /* wait-event timeout */
 701                         pch_i2c_stop(adap);
 702                         return -ETIME;
 703                 }
 704
 705                 if (last)
 706                         pch_i2c_stop(adap);
 707                 else
 708                         pch_i2c_repstart(adap);
 709
 710                 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
 711                 count = read_index;
 712         }
 713
 714         return count;
 715 }
 716
 717 /**
 718  * pch_i2c_cb() - Interrupt handler Call back function
 719  * @adap:       Pointer to struct i2c_algo_pch_data.
 720  */
 721 static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
 722 {
 723         u32 sts;
 724         void __iomem *p = adap->pch_base_address;
 725
 726         sts = ioread32(p + PCH_I2CSR);
 727         sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
 728         if (sts & I2CMAL_BIT)
 729                 adap->pch_event_flag |= I2CMAL_EVENT;
 730
 731         if (sts & I2CMCF_BIT)
 732                 adap->pch_event_flag |= I2CMCF_EVENT;
 733
 734         /* clear the applicable bits */
 735         pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
 736
 737         pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
 738
 739         wake_up(&pch_event);
 740 }
 741
 742 /**
 743  * pch_i2c_handler() - interrupt handler for the PCH I2C controller
 744  * @irq:        irq number.
 745  * @pData:      cookie passed back to the handler function.
 746  */
 747 static irqreturn_t pch_i2c_handler(int irq, void *pData)
 748 {
 749         u32 reg_val;
 750         int flag;
 751         int i;
 752         struct adapter_info *adap_info = pData;
 753         void __iomem *p;
 754         u32 mode;
 755
 756         for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
 757                 p = adap_info->pch_data[i].pch_base_address;
 758                 mode = ioread32(p + PCH_I2CMOD);
 759                 mode &= BUFFER_MODE | EEPROM_SR_MODE;
 760                 if (mode != NORMAL_MODE) {
 761                         pch_err(adap_info->pch_data,
 762                                 "I2C-%d mode(%d) is not supported\n", mode, i);
 763                         continue;
 764                 }
 765                 reg_val = ioread32(p + PCH_I2CSR);
 766                 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
 767                         pch_i2c_cb(&adap_info->pch_data[i]);
 768                         flag = 1;
 769                 }
 770         }
 771
 772         return flag ? IRQ_HANDLED : IRQ_NONE;
 773 }
 774
 775 /**
 776  * pch_i2c_xfer() - Reading adnd writing data through I2C bus
 777  * @i2c_adap:   Pointer to the struct i2c_adapter.
 778  * @msgs:       Pointer to i2c_msg structure.
 779  * @num:        number of messages.
 780  */
 781 static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
 782                         struct i2c_msg *msgs, s32 num)
 783 {
 784         struct i2c_msg *pmsg;
 785         u32 i = 0;
 786         u32 status;
 787         s32 ret;
 788
 789         struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
 790
 791         ret = mutex_lock_interruptible(&pch_mutex);
 792         if (ret)
 793                 return -ERESTARTSYS;
 794
 795         if (adap->p_adapter_info->pch_i2c_suspended) {
 796                 mutex_unlock(&pch_mutex);
 797                 return -EBUSY;
 798         }
 799
 800         pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
 801                 adap->p_adapter_info->pch_i2c_suspended);
 802         /* transfer not completed */
 803         adap->pch_i2c_xfer_in_progress = true;
 804
 805         for (i = 0; i < num && ret >= 0; i++) {
 806                 pmsg = &msgs[i];
 807                 pmsg->flags |= adap->pch_buff_mode_en;
 808                 status = pmsg->flags;
 809                 pch_dbg(adap,
 810                         "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
 811
 812                 if ((status & (I2C_M_RD)) != false) {
 813                         ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
 814                                                 (i == 0));
 815                 } else {
 816                         ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
 817                                                  (i == 0));
 818                 }
 819         }
 820
 821         adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
 822
 823         mutex_unlock(&pch_mutex);
 824
 825         return (ret < 0) ? ret : num;
 826 }
 827
 828 /**
 829  * pch_i2c_func() - return the functionality of the I2C driver
 830  * @adap:       Pointer to struct i2c_algo_pch_data.
 831  */
 832 static u32 pch_i2c_func(struct i2c_adapter *adap)
 833 {
 834         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 835 }
 836
 837 static struct i2c_algorithm pch_algorithm = {
 838         .master_xfer = pch_i2c_xfer,
 839         .functionality = pch_i2c_func
 840 };
 841
 842 /**
 843  * pch_i2c_disbl_int() - Disable PCH I2C interrupts
 844  * @adap:       Pointer to struct i2c_algo_pch_data.
 845  */
 846 static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
 847 {
 848         void __iomem *p = adap->pch_base_address;
 849
 850         pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
 851
 852         iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
 853
 854         iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
 855 }
 856
 857 static int __devinit pch_i2c_probe(struct pci_dev *pdev,
 858                                    const struct pci_device_id *id)
 859 {
 860         void __iomem *base_addr;
 861         int ret;
 862         int i, j;
 863         struct adapter_info *adap_info;
 864         struct i2c_adapter *pch_adap;
 865
 866         pch_pci_dbg(pdev, "Entered.\n");
 867
 868         adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
 869         if (adap_info == NULL) {
 870                 pch_pci_err(pdev, "Memory allocation FAILED\n");
 871                 return -ENOMEM;
 872         }
 873
 874         ret = pci_enable_device(pdev);
 875         if (ret) {
 876                 pch_pci_err(pdev, "pci_enable_device FAILED\n");
 877                 goto err_pci_enable;
 878         }
 879
 880         ret = pci_request_regions(pdev, KBUILD_MODNAME);
 881         if (ret) {
 882                 pch_pci_err(pdev, "pci_request_regions FAILED\n");
 883                 goto err_pci_req;
 884         }
 885
 886         base_addr = pci_iomap(pdev, 1, 0);
 887
 888         if (base_addr == NULL) {
 889                 pch_pci_err(pdev, "pci_iomap FAILED\n");
 890                 ret = -ENOMEM;
 891                 goto err_pci_iomap;
 892         }
 893
 894         /* Set the number of I2C channel instance */
 895         adap_info->ch_num = id->driver_data;
 896
 897         ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
 898                   KBUILD_MODNAME, adap_info);
 899         if (ret) {
 900                 pch_pci_err(pdev, "request_irq FAILED\n");
 901                 goto err_request_irq;
 902         }
 903
 904         for (i = 0; i < adap_info->ch_num; i++) {
 905                 pch_adap = &adap_info->pch_data[i].pch_adapter;
 906                 adap_info->pch_i2c_suspended = false;
 907
 908                 adap_info->pch_data[i].p_adapter_info = adap_info;
 909
 910                 pch_adap->owner = THIS_MODULE;
 911                 pch_adap->class = I2C_CLASS_HWMON;
 912                 strcpy(pch_adap->name, KBUILD_MODNAME);
 913                 pch_adap->algo = &pch_algorithm;
 914                 pch_adap->algo_data = &adap_info->pch_data[i];
 915
 916                 /* base_addr + offset; */
 917                 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
 918
 919                 pch_adap->dev.parent = &pdev->dev;
 920
 921                 pch_i2c_init(&adap_info->pch_data[i]);
 922
 923                 pch_adap->nr = i;
 924                 ret = i2c_add_numbered_adapter(pch_adap);
 925                 if (ret) {
 926                         pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
 927                         goto err_add_adapter;
 928                 }
 929         }
 930
 931         pci_set_drvdata(pdev, adap_info);
 932         pch_pci_dbg(pdev, "returns %d.\n", ret);
 933         return 0;
 934
 935 err_add_adapter:
 936         for (j = 0; j < i; j++)
 937                 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
 938         free_irq(pdev->irq, adap_info);
 939 err_request_irq:
 940         pci_iounmap(pdev, base_addr);
 941 err_pci_iomap:
 942         pci_release_regions(pdev);
 943 err_pci_req:
 944         pci_disable_device(pdev);
 945 err_pci_enable:
 946         kfree(adap_info);
 947         return ret;
 948 }
 949
 950 static void __devexit pch_i2c_remove(struct pci_dev *pdev)
 951 {
 952         int i;
 953         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 954
 955         free_irq(pdev->irq, adap_info);
 956
 957         for (i = 0; i < adap_info->ch_num; i++) {
 958                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 959                 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
 960         }
 961
 962         if (adap_info->pch_data[0].pch_base_address)
 963                 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
 964
 965         for (i = 0; i < adap_info->ch_num; i++)
 966                 adap_info->pch_data[i].pch_base_address = 0;
 967
 968         pci_set_drvdata(pdev, NULL);
 969
 970         pci_release_regions(pdev);
 971
 972         pci_disable_device(pdev);
 973         kfree(adap_info);
 974 }
 975
 976 #ifdef CONFIG_PM
 977 static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
 978 {
 979         int ret;
 980         int i;
 981         struct adapter_info *adap_info = pci_get_drvdata(pdev);
 982         void __iomem *p = adap_info->pch_data[0].pch_base_address;
 983
 984         adap_info->pch_i2c_suspended = true;
 985
 986         for (i = 0; i < adap_info->ch_num; i++) {
 987                 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
 988                         /* Wait until all channel transfers are completed */
 989                         msleep(20);
 990                 }
 991         }
 992
 993         /* Disable the i2c interrupts */
 994         for (i = 0; i < adap_info->ch_num; i++)
 995                 pch_i2c_disbl_int(&adap_info->pch_data[i]);
 996
 997         pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
 998                 "invoked function pch_i2c_disbl_int successfully\n",
 999                 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
1000                 ioread32(p + PCH_I2CESRSTA));
1001
1002         ret = pci_save_state(pdev);
1003
1004         if (ret) {
1005                 pch_pci_err(pdev, "pci_save_state\n");
1006                 return ret;
1007         }
1008
1009         pci_enable_wake(pdev, PCI_D3hot, 0);
1010         pci_disable_device(pdev);
1011         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1012
1013         return 0;
1014 }
1015
1016 static int pch_i2c_resume(struct pci_dev *pdev)
1017 {
1018         int i;
1019         struct adapter_info *adap_info = pci_get_drvdata(pdev);
1020
1021         pci_set_power_state(pdev, PCI_D0);
1022         pci_restore_state(pdev);
1023
1024         if (pci_enable_device(pdev) < 0) {
1025                 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
1026                 return -EIO;
1027         }
1028
1029         pci_enable_wake(pdev, PCI_D3hot, 0);
1030
1031         for (i = 0; i < adap_info->ch_num; i++)
1032                 pch_i2c_init(&adap_info->pch_data[i]);
1033
1034         adap_info->pch_i2c_suspended = false;
1035
1036         return 0;
1037 }
1038 #else
1039 #define pch_i2c_suspend NULL
1040 #define pch_i2c_resume NULL
1041 #endif
1042
1043 static struct pci_driver pch_pcidriver = {
1044         .name = KBUILD_MODNAME,
1045         .id_table = pch_pcidev_id,
1046         .probe = pch_i2c_probe,
1047         .remove = __devexit_p(pch_i2c_remove),
1048         .suspend = pch_i2c_suspend,
1049         .resume = pch_i2c_resume
1050 };
1051
1052 static int __init pch_pci_init(void)
1053 {
1054         return pci_register_driver(&pch_pcidriver);
1055 }
1056 module_init(pch_pci_init);
1057
1058 static void __exit pch_pci_exit(void)
1059 {
1060         pci_unregister_driver(&pch_pcidriver);
1061 }
1062 module_exit(pch_pci_exit);
1063
1064 MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
1065 MODULE_LICENSE("GPL");
1066 MODULE_AUTHOR("Tomoya MORINAGA. <tomoya-linux@dsn.lapis-semi.com>");
1067 module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
1068 module_param(pch_clk, int, (S_IRUSR | S_IWUSR));