arch/arm/mach-s5p64x0/common.c

   1 /*
   2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for S5P64X0 machines
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/device.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/sched.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/gpio.h>
  26 #include <linux/irq.h>
  27
  28 #include <asm/irq.h>
  29 #include <asm/proc-fns.h>
  30 #include <asm/system_misc.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/map.h>
  33 #include <asm/mach/irq.h>
  34
  35 #include <mach/map.h>
  36 #include <mach/hardware.h>
  37 #include <mach/regs-clock.h>
  38 #include <mach/regs-gpio.h>
  39
  40 #include <plat/cpu.h>
  41 #include <plat/clock.h>
  42 #include <plat/devs.h>
  43 #include <plat/pm.h>
  44 #include <plat/sdhci.h>
  45 #include <plat/adc-core.h>
  46 #include <plat/fb-core.h>
  47 #include <plat/gpio-cfg.h>
  48 #include <plat/regs-irqtype.h>
  49 #include <plat/regs-serial.h>
  50 #include <plat/watchdog-reset.h>
  51
  52 #include "common.h"
  53
  54 static const char name_s5p6440[] = "S5P6440";
  55 static const char name_s5p6450[] = "S5P6450";
  56
  57 static struct cpu_table cpu_ids[] __initdata = {
  58         {
  59                 .idcode         = S5P6440_CPU_ID,
  60                 .idmask         = S5P64XX_CPU_MASK,
  61                 .map_io         = s5p6440_map_io,
  62                 .init_clocks    = s5p6440_init_clocks,
  63                 .init_uarts     = s5p6440_init_uarts,
  64                 .init           = s5p64x0_init,
  65                 .name           = name_s5p6440,
  66         }, {
  67                 .idcode         = S5P6450_CPU_ID,
  68                 .idmask         = S5P64XX_CPU_MASK,
  69                 .map_io         = s5p6450_map_io,
  70                 .init_clocks    = s5p6450_init_clocks,
  71                 .init_uarts     = s5p6450_init_uarts,
  72                 .init           = s5p64x0_init,
  73                 .name           = name_s5p6450,
  74         },
  75 };
  76
  77 /* Initial IO mappings */
  78
  79 static struct map_desc s5p64x0_iodesc[] __initdata = {
  80         {
  81                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  82                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
  83                 .length         = SZ_4K,
  84                 .type           = MT_DEVICE,
  85         }, {
  86                 .virtual        = (unsigned long)S3C_VA_SYS,
  87                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
  88                 .length         = SZ_64K,
  89                 .type           = MT_DEVICE,
  90         }, {
  91                 .virtual        = (unsigned long)S3C_VA_TIMER,
  92                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
  93                 .length         = SZ_16K,
  94                 .type           = MT_DEVICE,
  95         }, {
  96                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  97                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
  98                 .length         = SZ_4K,
  99                 .type           = MT_DEVICE,
 100         }, {
 101                 .virtual        = (unsigned long)S5P_VA_SROMC,
 102                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
 103                 .length         = SZ_4K,
 104                 .type           = MT_DEVICE,
 105         }, {
 106                 .virtual        = (unsigned long)S5P_VA_GPIO,
 107                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
 108                 .length         = SZ_4K,
 109                 .type           = MT_DEVICE,
 110         }, {
 111                 .virtual        = (unsigned long)VA_VIC0,
 112                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
 113                 .length         = SZ_16K,
 114                 .type           = MT_DEVICE,
 115         }, {
 116                 .virtual        = (unsigned long)VA_VIC1,
 117                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
 118                 .length         = SZ_16K,
 119                 .type           = MT_DEVICE,
 120         },
 121 };
 122
 123 static struct map_desc s5p6440_iodesc[] __initdata = {
 124         {
 125                 .virtual        = (unsigned long)S3C_VA_UART,
 126                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         },
 130 };
 131
 132 static struct map_desc s5p6450_iodesc[] __initdata = {
 133         {
 134                 .virtual        = (unsigned long)S3C_VA_UART,
 135                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
 136                 .length         = SZ_512K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
 140                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
 141                 .length         = SZ_4K,
 142                 .type           = MT_DEVICE,
 143         },
 144 };
 145
 146 static void s5p64x0_idle(void)
 147 {
 148         unsigned long val;
 149
 150         val = __raw_readl(S5P64X0_PWR_CFG);
 151         val &= ~(0x3 << 5);
 152         val |= (0x1 << 5);
 153         __raw_writel(val, S5P64X0_PWR_CFG);
 154
 155         cpu_do_idle();
 156 }
 157
 158 /*
 159  * s5p64x0_map_io
 160  *
 161  * register the standard CPU IO areas
 162  */
 163
 164 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 165 {
 166         /* initialize the io descriptors we need for initialization */
 167         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
 168         if (mach_desc)
 169                 iotable_init(mach_desc, size);
 170
 171         /* detect cpu id and rev. */
 172         s5p_init_cpu(S5P64X0_SYS_ID);
 173
 174         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 175 }
 176
 177 void __init s5p6440_map_io(void)
 178 {
 179         /* initialize any device information early */
 180         s3c_adc_setname("s3c64xx-adc");
 181         s3c_fb_setname("s5p64x0-fb");
 182
 183         s5p64x0_default_sdhci0();
 184         s5p64x0_default_sdhci1();
 185         s5p6440_default_sdhci2();
 186
 187         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 188         init_consistent_dma_size(SZ_8M);
 189 }
 190
 191 void __init s5p6450_map_io(void)
 192 {
 193         /* initialize any device information early */
 194         s3c_adc_setname("s3c64xx-adc");
 195         s3c_fb_setname("s5p64x0-fb");
 196
 197         s5p64x0_default_sdhci0();
 198         s5p64x0_default_sdhci1();
 199         s5p6450_default_sdhci2();
 200
 201         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 202         init_consistent_dma_size(SZ_8M);
 203 }
 204
 205 /*
 206  * s5p64x0_init_clocks
 207  *
 208  * register and setup the CPU clocks
 209  */
 210
 211 void __init s5p6440_init_clocks(int xtal)
 212 {
 213         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 214
 215         s3c24xx_register_baseclocks(xtal);
 216         s5p_register_clocks(xtal);
 217         s5p6440_register_clocks();
 218         s5p6440_setup_clocks();
 219 }
 220
 221 void __init s5p6450_init_clocks(int xtal)
 222 {
 223         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 224
 225         s3c24xx_register_baseclocks(xtal);
 226         s5p_register_clocks(xtal);
 227         s5p6450_register_clocks();
 228         s5p6450_setup_clocks();
 229 }
 230
 231 /*
 232  * s5p64x0_init_irq
 233  *
 234  * register the CPU interrupts
 235  */
 236
 237 void __init s5p6440_init_irq(void)
 238 {
 239         /* S5P6440 supports 2 VIC */
 240         u32 vic[2];
 241
 242         /*
 243          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
 244          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
 245          */
 246         vic[0] = 0xff800ae7;
 247         vic[1] = 0xffbf23e5;
 248
 249         s5p_init_irq(vic, ARRAY_SIZE(vic));
 250 }
 251
 252 void __init s5p6450_init_irq(void)
 253 {
 254         /* S5P6450 supports only 2 VIC */
 255         u32 vic[2];
 256
 257         /*
 258          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
 259          * VIC1 is missing IRQ VIC1[12, 14, 23]
 260          */
 261         vic[0] = 0xff9f1fff;
 262         vic[1] = 0xff7fafff;
 263
 264         s5p_init_irq(vic, ARRAY_SIZE(vic));
 265 }
 266
 267 struct bus_type s5p64x0_subsys = {
 268         .name           = "s5p64x0-core",
 269         .dev_name       = "s5p64x0-core",
 270 };
 271
 272 static struct device s5p64x0_dev = {
 273         .bus    = &s5p64x0_subsys,
 274 };
 275
 276 static int __init s5p64x0_core_init(void)
 277 {
 278         return subsys_system_register(&s5p64x0_subsys, NULL);
 279 }
 280 core_initcall(s5p64x0_core_init);
 281
 282 int __init s5p64x0_init(void)
 283 {
 284         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 285
 286         /* set idle function */
 287         arm_pm_idle = s5p64x0_idle;
 288
 289         return device_register(&s5p64x0_dev);
 290 }
 291
 292 /* uart registration process */
 293 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 294 {
 295         int uart;
 296
 297         for (uart = 0; uart < no; uart++) {
 298                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
 299                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
 300         }
 301
 302         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 303 }
 304
 305 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 306 {
 307         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 308 }
 309
 310 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 311
 312 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
 313 {
 314         int offs = eint_offset(data->irq);
 315         int shift;
 316         u32 ctrl, mask;
 317         u32 newvalue = 0;
 318
 319         if (offs > 15)
 320                 return -EINVAL;
 321
 322         switch (type) {
 323         case IRQ_TYPE_NONE:
 324                 printk(KERN_WARNING "No edge setting!\n");
 325                 break;
 326         case IRQ_TYPE_EDGE_RISING:
 327                 newvalue = S3C2410_EXTINT_RISEEDGE;
 328                 break;
 329         case IRQ_TYPE_EDGE_FALLING:
 330                 newvalue = S3C2410_EXTINT_FALLEDGE;
 331                 break;
 332         case IRQ_TYPE_EDGE_BOTH:
 333                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 334                 break;
 335         case IRQ_TYPE_LEVEL_LOW:
 336                 newvalue = S3C2410_EXTINT_LOWLEV;
 337                 break;
 338         case IRQ_TYPE_LEVEL_HIGH:
 339                 newvalue = S3C2410_EXTINT_HILEV;
 340                 break;
 341         default:
 342                 printk(KERN_ERR "No such irq type %d", type);
 343                 return -EINVAL;
 344         }
 345
 346         shift = (offs / 2) * 4;
 347         mask = 0x7 << shift;
 348
 349         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
 350         ctrl |= newvalue << shift;
 351         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 352
 353         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
 354         if (soc_is_s5p6450())
 355                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
 356         else
 357                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
 358
 359         return 0;
 360 }
 361
 362 /*
 363  * s5p64x0_irq_demux_eint
 364  *
 365  * This function demuxes the IRQ from the group0 external interrupts,
 366  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
 367  * the specific handlers s5p64x0_irq_demux_eintX_Y.
 368  */
 369 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
 370 {
 371         u32 status = __raw_readl(S5P64X0_EINT0PEND);
 372         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
 373         unsigned int irq;
 374
 375         status &= ~mask;
 376         status >>= start;
 377         status &= (1 << (end - start + 1)) - 1;
 378
 379         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 380                 if (status & 1)
 381                         generic_handle_irq(irq);
 382                 status >>= 1;
 383         }
 384 }
 385
 386 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 387 {
 388         s5p64x0_irq_demux_eint(0, 3);
 389 }
 390
 391 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 392 {
 393         s5p64x0_irq_demux_eint(4, 11);
 394 }
 395
 396 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 397                                         struct irq_desc *desc)
 398 {
 399         s5p64x0_irq_demux_eint(12, 15);
 400 }
 401
 402 static int s5p64x0_alloc_gc(void)
 403 {
 404         struct irq_chip_generic *gc;
 405         struct irq_chip_type *ct;
 406
 407         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 408                                     S5P_VA_GPIO, handle_level_irq);
 409         if (!gc) {
 410                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 411                         "external interrupts failed\n", __func__);
 412                 return -EINVAL;
 413         }
 414
 415         ct = gc->chip_types;
 416         ct->chip.irq_ack = irq_gc_ack_set_bit;
 417         ct->chip.irq_mask = irq_gc_mask_set_bit;
 418         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 419         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 420         ct->chip.irq_set_wake = s3c_irqext_wake;
 421         ct->regs.ack = EINT0PEND_OFFSET;
 422         ct->regs.mask = EINT0MASK_OFFSET;
 423         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 424                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 425         return 0;
 426 }
 427
 428 static int __init s5p64x0_init_irq_eint(void)
 429 {
 430         int ret = s5p64x0_alloc_gc();
 431         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 432         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 433         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 434
 435         return ret;
 436 }
 437 arch_initcall(s5p64x0_init_irq_eint);
 438
 439 void s5p64x0_restart(char mode, const char *cmd)
 440 {
 441         if (mode != 's')
 442                 arch_wdt_reset();
 443
 444         soft_restart(0);
 445 }