arch/arm/mach-omap2/omap-mpuss-lowpower.c

   1 /*
   2  * OMAP MPUSS low power code
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   6  *
   7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
   8  * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
   9  * CPU0 and CPU1 LPRM modules.
  10  * CPU0, CPU1 and MPUSS each have there own power domain and
  11  * hence multiple low power combinations of MPUSS are possible.
  12  *
  13  * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
  14  * because the mode is not supported by hw constraints of dormant
  15  * mode. While waking up from the dormant mode, a reset  signal
  16  * to the Cortex-A9 processor must be asserted by the external
  17  * power controller.
  18  *
  19  * With architectural inputs and hardware recommendations, only
  20  * below modes are supported from power gain vs latency point of view.
  21  *
  22  *      CPU0            CPU1            MPUSS
  23  *      ----------------------------------------------
  24  *      ON              ON              ON
  25  *      ON(Inactive)    OFF             ON(Inactive)
  26  *      OFF             OFF             CSWR
  27  *      OFF             OFF             OSWR
  28  *      OFF             OFF             OFF(Device OFF *TBD)
  29  *      ----------------------------------------------
  30  *
  31  * Note: CPU0 is the master core and it is the last CPU to go down
  32  * and first to wake-up when MPUSS low power states are excercised
  33  *
  34  *
  35  * This program is free software; you can redistribute it and/or modify
  36  * it under the terms of the GNU General Public License version 2 as
  37  * published by the Free Software Foundation.
  38  */
  39
  40 #include <linux/kernel.h>
  41 #include <linux/io.h>
  42 #include <linux/errno.h>
  43 #include <linux/linkage.h>
  44 #include <linux/smp.h>
  45
  46 #include <asm/cacheflush.h>
  47 #include <asm/tlbflush.h>
  48 #include <asm/smp_scu.h>
  49 #include <asm/pgalloc.h>
  50 #include <asm/suspend.h>
  51 #include <asm/hardware/cache-l2x0.h>
  52
  53 #include <plat/omap44xx.h>
  54
  55 #include "common.h"
  56 #include "omap4-sar-layout.h"
  57 #include "pm.h"
  58 #include "prcm_mpu44xx.h"
  59 #include "prminst44xx.h"
  60 #include "prcm44xx.h"
  61 #include "prm44xx.h"
  62 #include "prm-regbits-44xx.h"
  63
  64 #ifdef CONFIG_SMP
  65
  66 struct omap4_cpu_pm_info {
  67         struct powerdomain *pwrdm;
  68         void __iomem *scu_sar_addr;
  69         void __iomem *wkup_sar_addr;
  70         void __iomem *l2x0_sar_addr;
  71 };
  72
  73 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
  74 static struct powerdomain *mpuss_pd;
  75 static void __iomem *sar_base;
  76
  77 /*
  78  * Program the wakeup routine address for the CPU0 and CPU1
  79  * used for OFF or DORMANT wakeup.
  80  */
  81 static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
  82 {
  83         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
  84
  85         __raw_writel(addr, pm_info->wkup_sar_addr);
  86 }
  87
  88 /*
  89  * Set the CPUx powerdomain's previous power state
  90  */
  91 static inline void set_cpu_next_pwrst(unsigned int cpu_id,
  92                                 unsigned int power_state)
  93 {
  94         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
  95
  96         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
  97 }
  98
  99 /*
 100  * Read CPU's previous power state
 101  */
 102 static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
 103 {
 104         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 105
 106         return pwrdm_read_prev_pwrst(pm_info->pwrdm);
 107 }
 108
 109 /*
 110  * Clear the CPUx powerdomain's previous power state
 111  */
 112 static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
 113 {
 114         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 115
 116         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 117 }
 118
 119 /*
 120  * Store the SCU power status value to scratchpad memory
 121  */
 122 static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
 123 {
 124         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 125         u32 scu_pwr_st;
 126
 127         switch (cpu_state) {
 128         case PWRDM_POWER_RET:
 129                 scu_pwr_st = SCU_PM_DORMANT;
 130                 break;
 131         case PWRDM_POWER_OFF:
 132                 scu_pwr_st = SCU_PM_POWEROFF;
 133                 break;
 134         case PWRDM_POWER_ON:
 135         case PWRDM_POWER_INACTIVE:
 136         default:
 137                 scu_pwr_st = SCU_PM_NORMAL;
 138                 break;
 139         }
 140
 141         __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
 142 }
 143
 144 /* Helper functions for MPUSS OSWR */
 145 static inline void mpuss_clear_prev_logic_pwrst(void)
 146 {
 147         u32 reg;
 148
 149         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 150                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 151         omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
 152                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 153 }
 154
 155 static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
 156 {
 157         u32 reg;
 158
 159         if (cpu_id) {
 160                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
 161                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 162                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
 163                                         OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
 164         } else {
 165                 reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
 166                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 167                 omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
 168                                         OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
 169         }
 170 }
 171
 172 /**
 173  * omap4_mpuss_read_prev_context_state:
 174  * Function returns the MPUSS previous context state
 175  */
 176 u32 omap4_mpuss_read_prev_context_state(void)
 177 {
 178         u32 reg;
 179
 180         reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 181                 OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
 182         reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
 183         return reg;
 184 }
 185
 186 /*
 187  * Store the CPU cluster state for L2X0 low power operations.
 188  */
 189 static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 190 {
 191         struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
 192
 193         __raw_writel(save_state, pm_info->l2x0_sar_addr);
 194 }
 195
 196 /*
 197  * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
 198  * in every restore MPUSS OFF path.
 199  */
 200 #ifdef CONFIG_CACHE_L2X0
 201 static void save_l2x0_context(void)
 202 {
 203         u32 val;
 204         void __iomem *l2x0_base = omap4_get_l2cache_base();
 205
 206         val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
 207         __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
 208         val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
 209         __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
 210 }
 211 #else
 212 static void save_l2x0_context(void)
 213 {}
 214 #endif
 215
 216 /**
 217  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 218  * The purpose of this function is to manage low power programming
 219  * of OMAP4 MPUSS subsystem
 220  * @cpu : CPU ID
 221  * @power_state: Low power state.
 222  *
 223  * MPUSS states for the context save:
 224  * save_state =
 225  *      0 - Nothing lost and no need to save: MPUSS INACTIVE
 226  *      1 - CPUx L1 and logic lost: MPUSS CSWR
 227  *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
 228  *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
 229  */
 230 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 231 {
 232         unsigned int save_state = 0;
 233         unsigned int wakeup_cpu;
 234
 235         if (omap_rev() == OMAP4430_REV_ES1_0)
 236                 return -ENXIO;
 237
 238         switch (power_state) {
 239         case PWRDM_POWER_ON:
 240         case PWRDM_POWER_INACTIVE:
 241                 save_state = 0;
 242                 break;
 243         case PWRDM_POWER_OFF:
 244                 save_state = 1;
 245                 break;
 246         case PWRDM_POWER_RET:
 247         default:
 248                 /*
 249                  * CPUx CSWR is invalid hardware state. Also CPUx OSWR
 250                  * doesn't make much scense, since logic is lost and $L1
 251                  * needs to be cleaned because of coherency. This makes
 252                  * CPUx OSWR equivalent to CPUX OFF and hence not supported
 253                  */
 254                 WARN_ON(1);
 255                 return -ENXIO;
 256         }
 257
 258         pwrdm_pre_transition();
 259
 260         /*
 261          * Check MPUSS next state and save interrupt controller if needed.
 262          * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
 263          */
 264         mpuss_clear_prev_logic_pwrst();
 265         if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
 266                 (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
 267                 save_state = 2;
 268
 269         cpu_clear_prev_logic_pwrst(cpu);
 270         set_cpu_next_pwrst(cpu, power_state);
 271         set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
 272         scu_pwrst_prepare(cpu, power_state);
 273         l2x0_pwrst_prepare(cpu, save_state);
 274
 275         /*
 276          * Call low level function  with targeted low power state.
 277          */
 278         cpu_suspend(save_state, omap4_finish_suspend);
 279
 280         /*
 281          * Restore the CPUx power state to ON otherwise CPUx
 282          * power domain can transitions to programmed low power
 283          * state while doing WFI outside the low powe code. On
 284          * secure devices, CPUx does WFI which can result in
 285          * domain transition
 286          */
 287         wakeup_cpu = smp_processor_id();
 288         set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
 289
 290         pwrdm_post_transition();
 291
 292         return 0;
 293 }
 294
 295 /**
 296  * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
 297  * @cpu : CPU ID
 298  * @power_state: CPU low power state.
 299  */
 300 int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
 301 {
 302         unsigned int cpu_state = 0;
 303
 304         if (omap_rev() == OMAP4430_REV_ES1_0)
 305                 return -ENXIO;
 306
 307         if (power_state == PWRDM_POWER_OFF)
 308                 cpu_state = 1;
 309
 310         clear_cpu_prev_pwrst(cpu);
 311         set_cpu_next_pwrst(cpu, power_state);
 312         set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
 313         scu_pwrst_prepare(cpu, power_state);
 314
 315         /*
 316          * CPU never retuns back if targetted power state is OFF mode.
 317          * CPU ONLINE follows normal CPU ONLINE ptah via
 318          * omap_secondary_startup().
 319          */
 320         omap4_finish_suspend(cpu_state);
 321
 322         set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
 323         return 0;
 324 }
 325
 326
 327 /*
 328  * Initialise OMAP4 MPUSS
 329  */
 330 int __init omap4_mpuss_init(void)
 331 {
 332         struct omap4_cpu_pm_info *pm_info;
 333
 334         if (omap_rev() == OMAP4430_REV_ES1_0) {
 335                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
 336                 return -ENODEV;
 337         }
 338
 339         sar_base = omap4_get_sar_ram_base();
 340
 341         /* Initilaise per CPU PM information */
 342         pm_info = &per_cpu(omap4_pm_info, 0x0);
 343         pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
 344         pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
 345         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
 346         pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
 347         if (!pm_info->pwrdm) {
 348                 pr_err("Lookup failed for CPU0 pwrdm\n");
 349                 return -ENODEV;
 350         }
 351
 352         /* Clear CPU previous power domain state */
 353         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 354         cpu_clear_prev_logic_pwrst(0);
 355
 356         /* Initialise CPU0 power domain state to ON */
 357         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 358
 359         pm_info = &per_cpu(omap4_pm_info, 0x1);
 360         pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
 361         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
 362         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
 363         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
 364         if (!pm_info->pwrdm) {
 365                 pr_err("Lookup failed for CPU1 pwrdm\n");
 366                 return -ENODEV;
 367         }
 368
 369         /* Clear CPU previous power domain state */
 370         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
 371         cpu_clear_prev_logic_pwrst(1);
 372
 373         /* Initialise CPU1 power domain state to ON */
 374         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
 375
 376         mpuss_pd = pwrdm_lookup("mpu_pwrdm");
 377         if (!mpuss_pd) {
 378                 pr_err("Failed to lookup MPUSS power domain\n");
 379                 return -ENODEV;
 380         }
 381         pwrdm_clear_all_prev_pwrst(mpuss_pd);
 382         mpuss_clear_prev_logic_pwrst();
 383
 384         /* Save device type on scratchpad for low level code to use */
 385         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 386                 __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
 387         else
 388                 __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
 389
 390         save_l2x0_context();
 391
 392         return 0;
 393 }
 394
 395 #endif