arch/arm/mach-integrator/core.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/core.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/memblock.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/termios.h>
  21 #include <linux/amba/bus.h>
  22 #include <linux/amba/serial.h>
  23 #include <linux/io.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <mach/hardware.h>
  27 #include <mach/platform.h>
  28 #include <asm/irq.h>
  29 #include <mach/cm.h>
  30 #include <asm/leds.h>
  31 #include <asm/mach-types.h>
  32 #include <asm/mach/time.h>
  33 #include <asm/pgtable.h>
  34
  35 static struct amba_pl010_data integrator_uart_data;
  36
  37 #define INTEGRATOR_RTC_IRQ      { IRQ_RTCINT }
  38 #define INTEGRATOR_UART0_IRQ    { IRQ_UARTINT0 }
  39 #define INTEGRATOR_UART1_IRQ    { IRQ_UARTINT1 }
  40 #define KMI0_IRQ                { IRQ_KMIINT0 }
  41 #define KMI1_IRQ                { IRQ_KMIINT1 }
  42
  43 static AMBA_APB_DEVICE(rtc, "mb:15", 0,
  44         INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
  45
  46 static AMBA_APB_DEVICE(uart0, "mb:16", 0,
  47         INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
  48
  49 static AMBA_APB_DEVICE(uart1, "mb:17", 0,
  50         INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
  51
  52 static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
  53 static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
  54
  55 static struct amba_device *amba_devs[] __initdata = {
  56         &rtc_device,
  57         &uart0_device,
  58         &uart1_device,
  59         &kmi0_device,
  60         &kmi1_device,
  61 };
  62
  63 /*
  64  * These are fixed clocks.
  65  */
  66 static struct clk clk24mhz = {
  67         .rate   = 24000000,
  68 };
  69
  70 static struct clk uartclk = {
  71         .rate   = 14745600,
  72 };
  73
  74 static struct clk dummy_apb_pclk;
  75
  76 static struct clk_lookup lookups[] = {
  77         {       /* Bus clock */
  78                 .con_id         = "apb_pclk",
  79                 .clk            = &dummy_apb_pclk,
  80         }, {
  81                 /* Integrator/AP timer frequency */
  82                 .dev_id         = "ap_timer",
  83                 .clk            = &clk24mhz,
  84         }, {    /* UART0 */
  85                 .dev_id         = "mb:16",
  86                 .clk            = &uartclk,
  87         }, {    /* UART1 */
  88                 .dev_id         = "mb:17",
  89                 .clk            = &uartclk,
  90         }, {    /* KMI0 */
  91                 .dev_id         = "mb:18",
  92                 .clk            = &clk24mhz,
  93         }, {    /* KMI1 */
  94                 .dev_id         = "mb:19",
  95                 .clk            = &clk24mhz,
  96         }, {    /* MMCI - IntegratorCP */
  97                 .dev_id         = "mb:1c",
  98                 .clk            = &uartclk,
  99         }
 100 };
 101
 102 void __init integrator_init_early(void)
 103 {
 104         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 105 }
 106
 107 static int __init integrator_init(void)
 108 {
 109         int i;
 110
 111         /*
 112          * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
 113          * hard-code them. The Integator/CP and forward have proper cell IDs.
 114          * Else we leave them undefined to the bus driver can autoprobe them.
 115          */
 116         if (machine_is_integrator()) {
 117                 rtc_device.periphid     = 0x00041030;
 118                 uart0_device.periphid   = 0x00041010;
 119                 uart1_device.periphid   = 0x00041010;
 120                 kmi0_device.periphid    = 0x00041050;
 121                 kmi1_device.periphid    = 0x00041050;
 122         }
 123
 124         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 125                 struct amba_device *d = amba_devs[i];
 126                 amba_device_register(d, &iomem_resource);
 127         }
 128
 129         return 0;
 130 }
 131
 132 arch_initcall(integrator_init);
 133
 134 /*
 135  * On the Integrator platform, the port RTS and DTR are provided by
 136  * bits in the following SC_CTRLS register bits:
 137  *        RTS  DTR
 138  *  UART0  7    6
 139  *  UART1  5    4
 140  */
 141 #define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
 142 #define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
 143
 144 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 145 {
 146         unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
 147
 148         if (dev == &uart0_device) {
 149                 rts_mask = 1 << 4;
 150                 dtr_mask = 1 << 5;
 151         } else {
 152                 rts_mask = 1 << 6;
 153                 dtr_mask = 1 << 7;
 154         }
 155
 156         if (mctrl & TIOCM_RTS)
 157                 ctrlc |= rts_mask;
 158         else
 159                 ctrls |= rts_mask;
 160
 161         if (mctrl & TIOCM_DTR)
 162                 ctrlc |= dtr_mask;
 163         else
 164                 ctrls |= dtr_mask;
 165
 166         __raw_writel(ctrls, SC_CTRLS);
 167         __raw_writel(ctrlc, SC_CTRLC);
 168 }
 169
 170 static struct amba_pl010_data integrator_uart_data = {
 171         .set_mctrl = integrator_uart_set_mctrl,
 172 };
 173
 174 #define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_CTRL)
 175
 176 static DEFINE_RAW_SPINLOCK(cm_lock);
 177
 178 /**
 179  * cm_control - update the CM_CTRL register.
 180  * @mask: bits to change
 181  * @set: bits to set
 182  */
 183 void cm_control(u32 mask, u32 set)
 184 {
 185         unsigned long flags;
 186         u32 val;
 187
 188         raw_spin_lock_irqsave(&cm_lock, flags);
 189         val = readl(CM_CTRL) & ~mask;
 190         writel(val | set, CM_CTRL);
 191         raw_spin_unlock_irqrestore(&cm_lock, flags);
 192 }
 193
 194 EXPORT_SYMBOL(cm_control);
 195
 196 /*
 197  * We need to stop things allocating the low memory; ideally we need a
 198  * better implementation of GFP_DMA which does not assume that DMA-able
 199  * memory starts at zero.
 200  */
 201 void __init integrator_reserve(void)
 202 {
 203         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 204 }
 205
 206 /*
 207  * To reset, we hit the on-board reset register in the system FPGA
 208  */
 209 void integrator_restart(char mode, const char *cmd)
 210 {
 211         cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
 212 }