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(parent: 8824178) | patch
drm/i915: Include TLB miss overhead for computing WM
authorChris Wilson <chris@chris-wilson.co.uk>
Sat, 8 Jan 2011 09:02:21 +0000 (09:02 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 11 Jan 2011 20:44:54 +0000 (20:44 +0000)
commitdb66e37d239b45f36a3f6495cf4ec49391b2c089
treed16899c361fb77e7732eb603835cb95c3af49421tree | snapshot
parent882417851a0f2e09e110038a13e88e9b5a100800commit | diff
drm/i915: Include TLB miss overhead for computing WM

The docs recommend that if 8 display lines fit inside the FIFO buffer,
then the number of watermark entries should be increased to hide the
latency of filling the rest of the FIFO buffer.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
drivers/gpu/drm/i915/intel_display.c diff | blob | history
Port of xen3.3 xenlinux code to Ubuntu Natty kernel