x86, intel, power: Correct the MSR_IA32_ENERGY_PERF_BIAS message

[linux-flexiantxendom0-natty.git] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 1366c7c..24cba78 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -12,7 +12,6 @@
 #include <asm/processor.h>
 #include <asm/pgtable.h>
 #include <asm/msr.h>
-#include <asm/ds.h>
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 
@@ -40,6 +39,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                        misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
                        c->cpuid_level = cpuid_eax(0);
+                       get_cpu_cap(c);
                }
        }
 
@@ -170,7 +170,7 @@ static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
        /* calling is from identify_secondary_cpu() ? */
-       if (c->cpu_index == boot_cpu_id)
+       if (!c->cpu_index)
                return;
 
        /*
@@ -284,9 +284,7 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
        /* Don't do the funky fallback heuristics the AMD version employs
           for now. */
        node = apicid_to_node[apicid];
-       if (node == NUMA_NO_NODE)
-               node = first_node(node_online_map);
-       else if (!node_online(node)) {
+       if (node == NUMA_NO_NODE || !node_online(node)) {
                /* reuse the value from init_cpu_to_node() */
                node = cpu_to_node(cpu);
        }
@@ -373,12 +371,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                        set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
        }
 
-       if (c->cpuid_level > 6) {
-               unsigned ecx = cpuid_ecx(6);
-               if (ecx & 0x01)
-                       set_cpu_cap(c, X86_FEATURE_APERFMPERF);
-       }
-
        if (cpu_has_xmm2)
                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
        if (cpu_has_ds) {
@@ -388,7 +380,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                        set_cpu_cap(c, X86_FEATURE_BTS);
                if (!(l1 & (1<<12)))
                        set_cpu_cap(c, X86_FEATURE_PEBS);
-               ds_init_intel(c);
        }
 
        if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
@@ -457,6 +448,24 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
        if (cpu_has(c, X86_FEATURE_VMX))
                detect_vmx_virtcap(c);
+
+       /*
+        * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
+        * x86_energy_perf_policy(8) is available to change it at run-time
+        */
+       if (cpu_has(c, X86_FEATURE_EPB)) {
+               u64 epb;
+
+               rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+               if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
+                       printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
+                               " Set to 'normal', was 'performance'\n"
+                               "ENERGY_PERF_BIAS: View and update with"
+                               " x86_energy_perf_policy(8)\n");
+                       epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
+                       wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
+               }
+       }
 }
 
 #ifdef CONFIG_X86_32