- Update to 2.6.25-rc3.
[linux-flexiantxendom0-3.2.10.git] / arch / powerpc / boot / dts / sequoia.dts
index 10784ff..8db9515 100644 (file)
        #size-cells = <1>;
        model = "amcc,sequoia";
        compatible = "amcc,sequoia";
-       dcr-parent = <&/cpus/PowerPC,440EPx@0>;
+       dcr-parent = <&/cpus/cpu@0>;
+
+       aliases {
+               ethernet0 = &EMAC0;
+               ethernet1 = &EMAC1;
+               serial0 = &UART0;
+               serial1 = &UART1;
+               serial2 = &UART2;
+               serial3 = &UART3;
+       };
 
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
 
-               PowerPC,440EPx@0 {
+               cpu@0 {
                        device_type = "cpu";
+                       model = "PowerPC,440EPx";
                        reg = <0>;
                        clock-frequency = <0>; /* Filled in by zImage */
                        timebase-frequency = <0>; /* Filled in by zImage */
                clock-frequency = <0>; /* Filled in by zImage */
 
                SDRAM0: sdram {
-                       device_type = "memory-controller";
                        compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali";
                        dcr-reg = <010 2>;
                };
                        interrupt-map-mask = <ffffffff>;
                };
 
+               USB1: usb@e0000400 {
+                       compatible = "ohci-be";
+                       reg = <0 e0000400 60>;
+                       interrupt-parent = <&UIC0>;
+                       interrupts = <15 8>;
+               };
+
+               USB0: ehci@e0000300 {
+                       compatible = "ibm,usb-ehci-440epx", "usb-ehci";
+                       interrupt-parent = <&UIC0>;
+                       interrupts = <1a 4>;
+                       reg = <0 e0000300 90 0 e0000390 70>;
+                       big-endian;
+               };
+
                POB0: opb {
                        compatible = "ibm,opb-440epx", "ibm,opb";
                        #address-cells = <1>;
                        };
 
                        IIC0: i2c@ef600700 {
-                               device_type = "i2c";
                                compatible = "ibm,iic-440epx", "ibm,iic";
                                reg = <ef600700 14>;
                                interrupt-parent = <&UIC0>;
                        };
 
                        IIC1: i2c@ef600800 {
-                               device_type = "i2c";
                                compatible = "ibm,iic-440epx", "ibm,iic";
                                reg = <ef600800 14>;
                                interrupt-parent = <&UIC0>;
                        };
 
                        ZMII0: emac-zmii@ef600d00 {
-                               device_type = "zmii-interface";
                                compatible = "ibm,zmii-440epx", "ibm,zmii";
                                reg = <ef600d00 c>;
                        };
 
                        RGMII0: emac-rgmii@ef601000 {
-                               device_type = "rgmii-interface";
                                compatible = "ibm,rgmii-440epx", "ibm,rgmii";
                                reg = <ef601000 8>;
                                has-mdio;
                                has-new-stacr-staopc;
                        };
                };
+
+               PCI0: pci@1ec000000 {
+                       device_type = "pci";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       compatible = "ibm,plb440epx-pci", "ibm,plb-pci";
+                       primary;
+                       reg = <1 eec00000 8     /* Config space access */
+                              1 eed00000 4     /* IACK */
+                              1 eed00000 4     /* Special cycle */
+                              1 ef400000 40>;  /* Internal registers */
+
+                       /* Outbound ranges, one memory and one IO,
+                        * later cannot be changed. Chip supports a second
+                        * IO range but we don't use it for now
+                        */
+                       ranges = <02000000 0 80000000 1 80000000 0 10000000
+                               01000000 0 00000000 1 e8000000 0 00100000>;
+
+                       /* Inbound 2GB range starting at 0 */
+                       dma-ranges = <42000000 0 0 0 0 0 80000000>;
+
+                       /* All PCI interrupts are routed to IRQ 67 */
+                       interrupt-map-mask = <0000 0 0 0>;
+                       interrupt-map = < 0000 0 0 0 &UIC2 3 8 >;
+               };
        };
 
        chosen {