- patches.apparmor/remove_suid_new_case_in_2.6.22.diff: Merge fix.

[linux-flexiantxendom0-3.2.10.git] / include / asm-arm / arch-omap / irqs.h

diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index c5bb05a..3ede58b 100644 (file)
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -37,8 +37,6 @@
 #define INT_DSP_MMU_ABORT      7
 #define INT_HOST               8
 #define INT_ABORT              9
-#define INT_DSP_MAILBOX1       10
-#define INT_DSP_MAILBOX2       11
 #define INT_BRIDGE_PRIV                13
 #define INT_GPIO_BANK1         14
 #define INT_UART3              15
@@ -63,6 +61,8 @@
 #define INT_1510_RES2          2
 #define INT_1510_SPI_TX                4
 #define INT_1510_SPI_RX                5
+#define INT_1510_DSP_MAILBOX1  10
+#define INT_1510_DSP_MAILBOX2  11
 #define INT_1510_RES12         12
 #define INT_1510_LB_MMU                17
 #define INT_1510_RES18         18
@@ -75,6 +75,8 @@
 #define INT_1610_IH2_FIQ       2
 #define INT_1610_McBSP2_TX     4
 #define INT_1610_McBSP2_RX     5
+#define INT_1610_DSP_MAILBOX1  10
+#define INT_1610_DSP_MAILBOX2  11
 #define INT_1610_LCD_LINE      12
 #define INT_1610_GPTIMER1      17
 #define INT_1610_GPTIMER2      18
@@ -131,11 +133,11 @@
 #define INT_RTC_TIMER          (25 + IH2_BASE)
 #define INT_RTC_ALARM          (26 + IH2_BASE)
 #define INT_MEM_STICK          (27 + IH2_BASE)
-#define INT_DSP_MMU            (28 + IH2_BASE)
 
 /*
  * OMAP-1510 specific IRQ numbers for interrupt handler 2
  */
+#define INT_1510_DSP_MMU       (28 + IH2_BASE)
 #define INT_1510_COM_SPI_RO    (31 + IH2_BASE)
 
 /*
@@ -146,6 +148,7 @@
 #define INT_1610_USB_OTG       (8 + IH2_BASE)
 #define INT_1610_SoSSI         (9 + IH2_BASE)
 #define INT_1610_SoSSI_MATCH   (19 + IH2_BASE)
+#define INT_1610_DSP_MMU       (28 + IH2_BASE)
 #define INT_1610_McBSP2RX_OF   (31 + IH2_BASE)
 #define INT_1610_STI           (32 + IH2_BASE)
 #define INT_1610_STI_WAKEUP    (33 + IH2_BASE)
@@ -239,10 +242,15 @@
 #define INT_24XX_SDMA_IRQ3     15
 #define INT_24XX_CAM_IRQ       24
 #define INT_24XX_DSS_IRQ       25
+#define INT_24XX_MAIL_U0_MPU   26
+#define INT_24XX_DSP_UMA       27
+#define INT_24XX_DSP_MMU       28
 #define INT_24XX_GPIO_BANK1    29
 #define INT_24XX_GPIO_BANK2    30
 #define INT_24XX_GPIO_BANK3    31
 #define INT_24XX_GPIO_BANK4    32
+#define INT_24XX_GPIO_BANK5    33
+#define INT_24XX_MAIL_U3_MPU   34
 #define INT_24XX_GPTIMER1      37
 #define INT_24XX_GPTIMER2      38
 #define INT_24XX_GPTIMER3      39
@@ -262,6 +270,12 @@
 #define INT_24XX_UART1_IRQ     72
 #define INT_24XX_UART2_IRQ     73
 #define INT_24XX_UART3_IRQ     74
+#define INT_24XX_USB_IRQ_GEN   75
+#define INT_24XX_USB_IRQ_NISO  76
+#define INT_24XX_USB_IRQ_ISO   77
+#define INT_24XX_USB_IRQ_HGEN  78
+#define INT_24XX_USB_IRQ_HSOF  79
+#define INT_24XX_USB_IRQ_OTG   80
 #define INT_24XX_MMC_IRQ       83
 
 /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and