- patches.apparmor/remove_suid_new_case_in_2.6.22.diff: Merge fix.

[linux-flexiantxendom0-3.2.10.git] / arch / arm / mm / Kconfig

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e684e9b..5f472a8 100644 (file)
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -131,8 +131,8 @@ config CPU_ARM920T
 # ARM922T
 config CPU_ARM922T
        bool "Support ARM922T processor" if ARCH_INTEGRATOR
-       depends on ARCH_LH7A40X || ARCH_INTEGRATOR
-       default y if ARCH_LH7A40X
+       depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
+       default y if ARCH_LH7A40X || ARCH_KS8695
        select CPU_32v4T
        select CPU_ABRT_EV4T
        select CPU_CACHE_V4WT
@@ -143,7 +143,7 @@ config CPU_ARM922T
        help
          The ARM922T is a version of the ARM920T, but with smaller
          instruction and data caches. It is used in Altera's
-         Excalibur XA device family.
+         Excalibur XA device family and Micrel's KS8695 Centaur.
 
          Say Y if you want support for the ARM922T processor.
          Otherwise, say N.
@@ -171,8 +171,8 @@ config CPU_ARM925T
 # ARM926T
 config CPU_ARM926T
        bool "Support ARM926T processor"
-       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
-       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_NS9XXX
+       depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
+       default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
        select CPU_32v5
        select CPU_ABRT_EV5TJ
        select CPU_CACHE_VIVT
@@ -351,6 +351,7 @@ config CPU_V6
        select CPU_CACHE_V6
        select CPU_CACHE_VIPT
        select CPU_CP15_MMU
+       select CPU_HAS_ASID
        select CPU_COPY_V6 if MMU
        select CPU_TLB_V6 if MMU
 
@@ -366,6 +367,20 @@ config CPU_32v6K
          enabled will not boot on processors with do not support these
          instructions.
 
+# ARMv7
+config CPU_V7
+       bool "Support ARM V7 processor"
+       depends on ARCH_INTEGRATOR
+       select CPU_32v6K
+       select CPU_32v7
+       select CPU_ABRT_EV7
+       select CPU_CACHE_V7
+       select CPU_CACHE_VIPT
+       select CPU_CP15_MMU
+       select CPU_HAS_ASID
+       select CPU_COPY_V6 if MMU
+       select CPU_TLB_V6 if MMU
+
 # Figure out what processor architecture version we should be using.
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
@@ -391,6 +406,9 @@ config CPU_32v5
 config CPU_32v6
        bool
 
+config CPU_32v7
+       bool
+
 # The abort model
 config CPU_ABRT_NOMMU
        bool
@@ -413,6 +431,9 @@ config CPU_ABRT_EV5TJ
 config CPU_ABRT_EV6
        bool
 
+config CPU_ABRT_EV7
+       bool
+
 # The cache model
 config CPU_CACHE_V3
        bool
@@ -429,6 +450,9 @@ config CPU_CACHE_V4WB
 config CPU_CACHE_V6
        bool
 
+config CPU_CACHE_V7
+       bool
+
 config CPU_CACHE_VIVT
        bool
 
@@ -476,6 +500,12 @@ config CPU_TLB_V6
 
 endif
 
+config CPU_HAS_ASID
+       bool
+       help
+         This indicates whether the CPU has the ASID register; used to
+         tag TLB and possibly cache entries.
+
 config CPU_CP15
        bool
        help
@@ -503,7 +533,7 @@ comment "Processor Features"
 
 config ARM_THUMB
        bool "Support Thumb user binaries"
-       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
+       depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7
        default y
        help
          Say Y if you want to include kernel support for running user space
@@ -578,9 +608,15 @@ config CPU_CACHE_ROUND_ROBIN
          Say Y here to use the predictable round-robin cache replacement
          policy.  Unless you specifically require this or are unsure, say N.
 
+config CPU_L2CACHE_DISABLE
+       bool "Disable level 2 cache"
+       depends on CPU_V7
+       help
+         Say Y here to disable the level 2 cache.  If unsure, say N.
+
 config CPU_BPREDICT_DISABLE
        bool "Disable branch prediction"
-       depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3
+       depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
        help
          Say Y here to disable branch prediction.  If unsure, say N.