- patches.arch/x86_mce_intel_decode_physical_address.patch:

[linux-flexiantxendom0-3.2.10.git] / arch / arm / mach-s3c2410 / include / mach / regs-dsc.h

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
index 3c3853c..98fd4a0 100644 (file)
--- a/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-dsc.h
@@ -19,6 +19,42 @@
 #define S3C2412_DSC1      S3C2410_GPIOREG(0xe0)
 #endif
 
+#if defined(CONFIG_CPU_S3C2416)
+#define S3C2416_DSC0      S3C2410_GPIOREG(0xc0)
+#define S3C2416_DSC1      S3C2410_GPIOREG(0xc4)
+#define S3C2416_DSC2      S3C2410_GPIOREG(0xc8)
+#define S3C2416_DSC3      S3C2410_GPIOREG(0x110)
+
+#define S3C2416_SELECT_DSC0    (0 << 30)
+#define S3C2416_SELECT_DSC1    (1 << 30)
+#define S3C2416_SELECT_DSC2    (2 << 30)
+#define S3C2416_SELECT_DSC3    (3 << 30)
+
+#define S3C2416_DSC_GETSHIFT(x)        (x & 30)
+
+#define S3C2416_DSC0_CF                (S3C2416_SELECT_DSC0 | 28)
+#define        S3C2416_DSC0_CF_5mA     (0 << 28)
+#define        S3C2416_DSC0_CF_10mA    (1 << 28)
+#define        S3C2416_DSC0_CF_15mA    (2 << 28)
+#define        S3C2416_DSC0_CF_21mA    (3 << 28)
+#define        S3C2416_DSC0_CF_MASK    (3 << 28)
+
+#define S3C2416_DSC0_nRBE      (S3C2416_SELECT_DSC0 | 26)
+#define        S3C2416_DSC0_nRBE_5mA   (0 << 26)
+#define        S3C2416_DSC0_nRBE_10mA  (1 << 26)
+#define        S3C2416_DSC0_nRBE_15mA  (2 << 26)
+#define        S3C2416_DSC0_nRBE_21mA  (3 << 26)
+#define        S3C2416_DSC0_nRBE_MASK  (3 << 26)
+
+#define S3C2416_DSC0_nROE      (S3C2416_SELECT_DSC0 | 24)
+#define        S3C2416_DSC0_nROE_5mA   (0 << 24)
+#define        S3C2416_DSC0_nROE_10mA  (1 << 24)
+#define        S3C2416_DSC0_nROE_15mA  (2 << 24)
+#define        S3C2416_DSC0_nROE_21mA  (3 << 24)
+#define        S3C2416_DSC0_nROE_MASK  (3 << 24)
+
+#endif
+
 #if defined(CONFIG_CPU_S3C244X)
 
 #define S3C2440_DSC0      S3C2410_GPIOREG(0xc4)