- Update Xen patches to 3.3-rc5 and c/s 1157.

[linux-flexiantxendom0-3.2.10.git] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 3e6ff6c..c55ce62 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -36,10 +36,15 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 
                if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
+#ifndef CONFIG_XEN
                        misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
                        wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
                        c->cpuid_level = cpuid_eax(0);
                        get_cpu_cap(c);
+#else
+                       pr_warning("CPUID levels are restricted -"
+                                  " update hypervisor\n");
+#endif
                }
        }
 
@@ -47,6 +52,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                (c->x86 == 0x6 && c->x86_model >= 0x0e))
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 
+#ifndef CONFIG_XEN
        if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
                unsigned lower_word;
 
@@ -69,6 +75,7 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
                clear_cpu_cap(c, X86_FEATURE_PSE);
        }
+#endif
 
 #ifdef CONFIG_X86_64
        set_cpu_cap(c, X86_FEATURE_SYSENTER32);
@@ -93,8 +100,10 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
        if (c->x86_power & (1 << 8)) {
                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
                set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
+#ifndef CONFIG_XEN
                if (!check_tsc_unstable())
                        sched_clock_stable = 1;
+#endif
        }
 
        /*
@@ -238,9 +247,13 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
                rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
                if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
                        printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
+#ifndef CONFIG_XEN
                        printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
                        wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
+#else
+                       pr_warning("CPU: Hypervisor update needed\n");
+#endif
                }
        }
 
@@ -285,6 +298,7 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 }
 #endif
 
+#ifndef CONFIG_XEN
 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_NUMA
@@ -357,6 +371,7 @@ static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
                        set_cpu_cap(c, X86_FEATURE_VPID);
        }
 }
+#endif
 
 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 {
@@ -440,6 +455,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_P3);
 #endif
 
+#ifndef CONFIG_XEN
        if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
                /*
                 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
@@ -456,6 +472,7 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
        if (cpu_has(c, X86_FEATURE_VMX))
                detect_vmx_virtcap(c);
+#endif
 
        /*
         * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.