- patches.suse/slab-handle-memoryless-nodes-v2a.patch: Refresh.

[linux-flexiantxendom0-3.2.10.git] / drivers / gpu / drm / i915 / dvo_ivch.c

diff --git a/drivers/gpu/drm/i915/dvo_ivch.c b/drivers/gpu/drm/i915/dvo_ivch.c
index aa176f9..24169e5 100644 (file)
--- a/drivers/gpu/drm/i915/dvo_ivch.c
+++ b/drivers/gpu/drm/i915/dvo_ivch.c
@@ -202,7 +202,8 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
        };
 
        if (!priv->quiet) {
-               DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
+               DRM_DEBUG_KMS("Unable to read register 0x%02x from "
+                               "%s:%02x.\n",
                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
        return false;
@@ -230,7 +231,7 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
                return true;
 
        if (!priv->quiet) {
-               DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
+               DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
                          addr, i2cbus->adapter.name, dvo->slave_addr);
        }
 
@@ -261,7 +262,7 @@ static bool ivch_init(struct intel_dvo_device *dvo,
         * the address it's responding on.
         */
        if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
-               DRM_DEBUG("ivch detect failed due to address mismatch "
+               DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
                          "(%d vs %d)\n",
                          (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
                goto out;
@@ -367,41 +368,41 @@ static void ivch_dump_regs(struct intel_dvo_device *dvo)
        uint16_t val;
 
        ivch_read(dvo, VR00, &val);
-       DRM_DEBUG("VR00: 0x%04x\n", val);
+       DRM_LOG_KMS("VR00: 0x%04x\n", val);
        ivch_read(dvo, VR01, &val);
-       DRM_DEBUG("VR01: 0x%04x\n", val);
+       DRM_LOG_KMS("VR01: 0x%04x\n", val);
        ivch_read(dvo, VR30, &val);
-       DRM_DEBUG("VR30: 0x%04x\n", val);
+       DRM_LOG_KMS("VR30: 0x%04x\n", val);
        ivch_read(dvo, VR40, &val);
-       DRM_DEBUG("VR40: 0x%04x\n", val);
+       DRM_LOG_KMS("VR40: 0x%04x\n", val);
 
        /* GPIO registers */
        ivch_read(dvo, VR80, &val);
-       DRM_DEBUG("VR80: 0x%04x\n", val);
+       DRM_LOG_KMS("VR80: 0x%04x\n", val);
        ivch_read(dvo, VR81, &val);
-       DRM_DEBUG("VR81: 0x%04x\n", val);
+       DRM_LOG_KMS("VR81: 0x%04x\n", val);
        ivch_read(dvo, VR82, &val);
-       DRM_DEBUG("VR82: 0x%04x\n", val);
+       DRM_LOG_KMS("VR82: 0x%04x\n", val);
        ivch_read(dvo, VR83, &val);
-       DRM_DEBUG("VR83: 0x%04x\n", val);
+       DRM_LOG_KMS("VR83: 0x%04x\n", val);
        ivch_read(dvo, VR84, &val);
-       DRM_DEBUG("VR84: 0x%04x\n", val);
+       DRM_LOG_KMS("VR84: 0x%04x\n", val);
        ivch_read(dvo, VR85, &val);
-       DRM_DEBUG("VR85: 0x%04x\n", val);
+       DRM_LOG_KMS("VR85: 0x%04x\n", val);
        ivch_read(dvo, VR86, &val);
-       DRM_DEBUG("VR86: 0x%04x\n", val);
+       DRM_LOG_KMS("VR86: 0x%04x\n", val);
        ivch_read(dvo, VR87, &val);
-       DRM_DEBUG("VR87: 0x%04x\n", val);
+       DRM_LOG_KMS("VR87: 0x%04x\n", val);
        ivch_read(dvo, VR88, &val);
-       DRM_DEBUG("VR88: 0x%04x\n", val);
+       DRM_LOG_KMS("VR88: 0x%04x\n", val);
 
        /* Scratch register 0 - AIM Panel type */
        ivch_read(dvo, VR8E, &val);
-       DRM_DEBUG("VR8E: 0x%04x\n", val);
+       DRM_LOG_KMS("VR8E: 0x%04x\n", val);
 
        /* Scratch register 1 - Status register */
        ivch_read(dvo, VR8F, &val);
-       DRM_DEBUG("VR8F: 0x%04x\n", val);
+       DRM_LOG_KMS("VR8F: 0x%04x\n", val);
 }
 
 static void ivch_save(struct intel_dvo_device *dvo)