- patches.suse/slab-handle-memoryless-nodes-v2a.patch: Refresh.

[linux-flexiantxendom0-3.2.10.git] / drivers / edac / amd64_edac.h

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index bba6c94..41bc561 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -129,19 +129,15 @@
  *         sections 3.5.4 and 3.5.5 for more information.
  */
 
-#define EDAC_AMD64_VERSION             " Ver: 3.2.0 " __DATE__
+#define EDAC_AMD64_VERSION             " Ver: 3.3.0 " __DATE__
 #define EDAC_MOD_STR                   "amd64_edac"
 
 #define EDAC_MAX_NUMNODES              8
 
 /* Extended Model from CPUID, for CPU Revision numbers */
-#define OPTERON_CPU_LE_REV_C           0
-#define OPTERON_CPU_REV_D              1
-#define OPTERON_CPU_REV_E              2
-
-/* NPT processors have the following Extended Models */
-#define OPTERON_CPU_REV_F              4
-#define OPTERON_CPU_REV_FA             5
+#define K8_REV_D                       1
+#define K8_REV_E                       2
+#define K8_REV_F                       4
 
 /* Hardware limit on ChipSelect rows per MC and processors per system */
 #define MAX_CS_COUNT                   8
@@ -243,7 +239,7 @@
 #define F10_DCHR_1                     0x194
 
 #define F10_DCHR_FOUR_RANK_DIMM                BIT(18)
-#define F10_DCHR_Ddr3Mode              BIT(8)
+#define DDR3_MODE                      BIT(8)
 #define F10_DCHR_MblMode               BIT(6)
 
 
@@ -384,8 +380,6 @@ enum {
 #define K8_NBCAP_CORES                 (BIT(12)|BIT(13))
 #define K8_NBCAP_CHIPKILL              BIT(4)
 #define K8_NBCAP_SECDED                        BIT(3)
-#define K8_NBCAP_8_NODE                        BIT(2)
-#define K8_NBCAP_DUAL_NODE             BIT(1)
 #define K8_NBCAP_DCT_DUAL              BIT(0)
 
 /* MSRs */
@@ -503,7 +497,6 @@ struct scrubrate {
 };
 
 extern struct scrubrate scrubrates[23];
-extern u32 revf_quad_ddr2_shift[16];
 extern const char *tt_msgs[4];
 extern const char *ll_msgs[4];
 extern const char *rrrr_msgs[16];
@@ -533,17 +526,15 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
  * functions and per device encoding/decoding logic.
  */
 struct low_ops {
-       int (*probe_valid_hardware)(struct amd64_pvt *pvt);
-       int (*early_channel_count)(struct amd64_pvt *pvt);
-
-       u64 (*get_error_address)(struct mem_ctl_info *mci,
-                       struct err_regs *info);
-       void (*read_dram_base_limit)(struct amd64_pvt *pvt, int dram);
-       void (*read_dram_ctl_register)(struct amd64_pvt *pvt);
-       void (*map_sysaddr_to_csrow)(struct mem_ctl_info *mci,
-                                       struct err_regs *info,
-                                       u64 SystemAddr);
-       int (*dbam_map_to_pages)(struct amd64_pvt *pvt, int dram_map);
+       int (*early_channel_count)      (struct amd64_pvt *pvt);
+
+       u64 (*get_error_address)        (struct mem_ctl_info *mci,
+                                        struct err_regs *info);
+       void (*read_dram_base_limit)    (struct amd64_pvt *pvt, int dram);
+       void (*read_dram_ctl_register)  (struct amd64_pvt *pvt);
+       void (*map_sysaddr_to_csrow)    (struct mem_ctl_info *mci,
+                                        struct err_regs *info, u64 SystemAddr);
+       int (*dbam_to_cs)               (struct amd64_pvt *pvt, int cs_mode);
 };
 
 struct amd64_family_type {
@@ -565,6 +556,22 @@ static inline struct low_ops *family_ops(int index)
        return &amd64_family_types[index].ops;
 }
 
+static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
+                                          u32 *val, const char *func)
+{
+       int err = 0;
+
+       err = pci_read_config_dword(pdev, offset, val);
+       if (err)
+               amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
+                            func, PCI_FUNC(pdev->devfn), offset);
+
+       return err;
+}
+
+#define amd64_read_pci_cfg(pdev, offset, val)  \
+       amd64_read_pci_cfg_dword(pdev, offset, val, __func__)
+
 /*
  * For future CPU versions, verify the following as new 'slow' rates appear and
  * modify the necessary skip values for the supported CPU.