/*
* We need the APIC definitions automatically as part of 'smp.h'
*/
-#ifndef ASSEMBLY
+#ifndef __ASSEMBLY__
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/ptrace.h>
#endif
#ifdef CONFIG_X86_LOCAL_APIC
-#ifndef ASSEMBLY
+#ifndef __ASSEMBLY__
#include <asm/fixmap.h>
#include <asm/bitops.h>
#include <asm/mpspec.h>
#endif
#endif
-#if CONFIG_SMP
+#ifdef CONFIG_SMP
# ifdef CONFIG_MULTIQUAD
# define TARGET_CPUS 0xf /* all CPUs in *THIS* quad */
# define INT_DELIVERY_MODE 0 /* physical delivery on LOCAL quad */
# define INT_DELIVERY_MODE 1 /* logical delivery broadcast to all procs */
# endif
#else
+# define INT_DELIVERY_MODE 0 /* physical delivery on LOCAL quad */
# define TARGET_CPUS 0x01
#endif
+#ifndef clustered_apic_mode
+ #ifdef CONFIG_MULTIQUAD
+ #define clustered_apic_mode (1)
+ #define esr_disable (1)
+ #else /* !CONFIG_MULTIQUAD */
+ #define clustered_apic_mode (0)
+ #define esr_disable (0)
+ #endif /* CONFIG_MULTIQUAD */
+#endif
+
#ifdef CONFIG_SMP
-#ifndef ASSEMBLY
+#ifndef __ASSEMBLY__
/*
* Private routines/data
extern volatile int cpu_to_logical_apicid[NR_CPUS];
extern volatile int logical_apicid_to_cpu[MAX_APICID];
-#ifndef clustered_apic_mode
- #ifdef CONFIG_MULTIQUAD
- #define clustered_apic_mode (1)
- #define esr_disable (1)
- #else /* !CONFIG_MULTIQUAD */
- #define clustered_apic_mode (0)
- #define esr_disable (0)
- #endif /* CONFIG_MULTIQUAD */
-#endif
-
/*
* General functions that each host system must provide.
*/
return GET_APIC_LOGICAL_ID(*(unsigned long *)(APIC_BASE+APIC_LDR));
}
-#endif /* !ASSEMBLY */
+#endif /* !__ASSEMBLY__ */
#define NO_PROC_ID 0xFF /* No processor magic marker */