static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-static struct pci_device_id snd_cs4281_ids[] __devinitdata = {
+static struct pci_device_id snd_cs4281_ids[] = {
{ 0x1013, 0x6005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* CS4281 */
{ 0, }
};
* common I/O routines
*/
-static void snd_cs4281_delay(unsigned int delay, int can_schedule)
+static void snd_cs4281_delay(unsigned int delay)
{
if (delay > 999) {
- if (can_schedule) {
- unsigned long end_time;
- delay = (delay * HZ) / 1000000;
- if (delay < 1)
- delay = 1;
- end_time = jiffies + delay;
- do {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(1);
- } while (time_after_eq(end_time, jiffies));
- } else {
- delay += 999;
- delay /= 1000;
- mdelay(delay > 0 ? delay : 1);
- }
+ unsigned long end_time;
+ delay = (delay * HZ) / 1000000;
+ if (delay < 1)
+ delay = 1;
+ end_time = jiffies + delay;
+ do {
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
+ } while (time_after_eq(end_time, jiffies));
} else {
udelay(delay);
}
}
-inline static void snd_cs4281_delay_long(int can_schedule)
+inline static void snd_cs4281_delay_long(void)
{
- if (can_schedule) {
- set_current_state(TASK_UNINTERRUPTIBLE);
- schedule_timeout(1);
- } else
- mdelay(10);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_timeout(1);
}
static inline void snd_cs4281_pokeBA0(cs4281_t *chip, unsigned long offset, unsigned int val)
* joystick support
*/
-#if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
+#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
typedef struct snd_cs4281_gameport {
struct gameport info;
#else
#define snd_cs4281_gameport(chip) /*NOP*/
-#endif /* CONFIG_GAMEPORT || CONFIG_GAMEPORT_MODULE */
+#endif /* CONFIG_GAMEPORT || (MODULE && CONFIG_GAMEPORT_MODULE) */
/*
static int snd_cs4281_free(cs4281_t *chip)
{
-#if defined(CONFIG_GAMEPORT) || defined(CONFIG_GAMEPORT_MODULE)
+#if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
if (chip->gameport) {
gameport_unregister_port(&chip->gameport->info);
kfree(chip->gameport);
return snd_cs4281_free(chip);
}
-static int snd_cs4281_chip_init(cs4281_t *chip, int can_schedule); /* defined below */
+static int snd_cs4281_chip_init(cs4281_t *chip); /* defined below */
#ifdef CONFIG_PM
static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state);
#endif
return -ENOMEM;
}
- tmp = snd_cs4281_chip_init(chip, 1);
+ tmp = snd_cs4281_chip_init(chip);
if (tmp) {
snd_cs4281_free(chip);
return tmp;
return 0;
}
-static int snd_cs4281_chip_init(cs4281_t *chip, int can_schedule)
+static int snd_cs4281_chip_init(cs4281_t *chip)
{
unsigned int tmp;
int timeout;
snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
udelay(50);
snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
- snd_cs4281_delay(50000, can_schedule);
+ snd_cs4281_delay(50000);
if (chip->dual_codec)
snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
* Start the DLL Clock logic.
*/
snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
- snd_cs4281_delay(50000, can_schedule);
+ snd_cs4281_delay(50000);
snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
/*
*/
if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
goto __ok0;
- snd_cs4281_delay_long(can_schedule);
+ snd_cs4281_delay_long();
} while (timeout-- > 0);
snd_printk(KERN_ERR "DLLRDY not seen\n");
*/
if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
goto __ok1;
- snd_cs4281_delay_long(can_schedule);
+ snd_cs4281_delay_long();
} while (timeout-- > 0);
snd_printk(KERN_ERR "never read codec ready from AC'97 (0x%x)\n", snd_cs4281_peekBA0(chip, BA0_ACSTS));
do {
if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
goto __codec2_ok;
- snd_cs4281_delay_long(can_schedule);
+ snd_cs4281_delay_long();
} while (timeout-- > 0);
snd_printk(KERN_INFO "secondary codec doesn't respond. disable it...\n");
chip->dual_codec = 0;
*/
if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
goto __ok2;
- snd_cs4281_delay_long(can_schedule);
+ snd_cs4281_delay_long();
} while (timeout-- > 0);
snd_printk(KERN_ERR "never read ISV3 and ISV4 from AC'97\n");
ulCLK |= CLKCR1_CKRA;
snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
- snd_cs4281_chip_init(chip, 0);
+ snd_cs4281_chip_init(chip);
/* restore the status registers */
for (i = 0; i < number_of(saved_regs); i++)
snd_power_change_state(card, SNDRV_CTL_POWER_D0);
}
-#ifndef PCI_OLD_SUSPEND
static int snd_cs4281_suspend(struct pci_dev *dev, u32 state)
{
cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return -ENXIO);
cs4281_resume(chip);
return 0;
}
-#else
-static void snd_cs4281_suspend(struct pci_dev *dev)
-{
- cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return);
- cs4281_suspend(chip);
-}
-static void snd_cs4281_resume(struct pci_dev *dev)
-{
- cs4281_t *chip = snd_magic_cast(cs4281_t, pci_get_drvdata(dev), return);
- cs4281_resume(chip);
-}
-#endif
/* callback */
static int snd_cs4281_set_power_state(snd_card_t *card, unsigned int power_state)