commented early_printk patch because of rejects.

[linux-flexiantxendom0-3.2.10.git] / include / asm-mips / sibyte / sb1250_dma.h

diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index c26be02..f1b08d3 100644 (file)
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -9,7 +9,7 @@
     *  
     *  SB1250 specification level:  User's manual 1/02/02
     *  
-    *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
+    *  Author:  Mitch Lichtenberg
     *  
     *********************************************************************  
     *
@@ -65,10 +65,10 @@
 #define K_DMA_DESC_TYPE_RING_AL                0
 #define K_DMA_DESC_TYPE_CHAIN_AL       1
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define K_DMA_DESC_TYPE_RING_UAL_WI    2
 #define K_DMA_DESC_TYPE_RING_UAL_RMW   3
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
 #define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
@@ -111,11 +111,11 @@
 #define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
 #define M_DMA_L2CA                 _SB_MAKEMASK1(5)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_DMA_RX_XTRA_STATUS       _SB_MAKEMASK1(6)
 #define M_DMA_TX_CPU_PAUSE         _SB_MAKEMASK1(6)
 #define M_DMA_TX_FC_PAUSE_EN       _SB_MAKEMASK1(7)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define M_DMA_MBZ1                  _SB_MAKEMASK(6,15)
 
@@ -165,14 +165,14 @@
 #define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
 #define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_DMA_TX_CH_PAUSE_ON       _SB_MAKEMASK1(56)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 /*
  * Receive Packet Drop Registers
  */
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define S_DMA_OODLOST_RX           _SB_MAKE64(0)
 #define M_DMA_OODLOST_RX           _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
 #define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
@@ -180,7 +180,7 @@
 #define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
 #define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
 #define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 /*  *********************************************************************
     *  DMA Descriptors
@@ -201,21 +201,21 @@
 
 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
 #define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
 #define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
 #define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
 #define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define S_DMA_DSCRA_DSCR_CNT       _SB_MAKE64(40)
 #define M_DMA_DSCRA_DSCR_CNT       _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
 #define G_DMA_DSCRA_DSCR_CNT(x)            _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
 #define M_DMA_DSCRA_OFFSETB        _SB_MAKEMASK1(50)
@@ -235,12 +235,12 @@
 #define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
 #define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
 #define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
 #define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
 #define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
 
@@ -255,12 +255,12 @@
 
 #define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 #define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
 #define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
@@ -287,10 +287,10 @@
 #define M_DMA_ETHRX_BADTCPCS   _SB_MAKEMASK1(0)
 #endif /* 1250 PASS2 || 112x PASS1 */
 
-#if SIBYTE_HDR_FEATURE(112x, PASS3)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_DMA_ETH_VLAN_FLAG    _SB_MAKEMASK1(1)
 #define M_DMA_ETH_CRC_FLAG     _SB_MAKEMASK1(2)
-#endif
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define S_DMA_ETHRX_RXCH            53
 #define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
@@ -438,7 +438,7 @@
                                      M_DM_CUR_DSCR_DSCR_COUNT)
 
 
-#if SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 /*
  * Data Mover Channel Partial Result Registers
  * Register: DM_PARTIAL_0
@@ -459,10 +459,10 @@
                                        M_DM_PARTIAL_TCPCS_PARTIAL)
 
 #define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
-#endif /* 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 
-#if SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 /*
  * Data Mover CRC Definition Registers
  * Register: CRC_DEF_0
@@ -479,10 +479,10 @@
 #define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
 #define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
                                        M_CRC_DEF_CRC_POLY)
-#endif /* 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 
-#if SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 /*
  * Data Mover CRC/Checksum Definition Registers
  * Register: CTCP_DEF_0
@@ -511,7 +511,7 @@
 #define K_CTCP_DEF_CRC_WIDTH_1        2
 
 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
-#endif /* 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 
 /*
@@ -565,7 +565,7 @@
 #define M_DM_DSCRA_WR_BKOFF        _SB_MAKEMASK1(53)
 #endif /* 1250 PASS2 || 112x PASS1 */
 
-#if SIBYTE_HDR_FEATURE(112x, PASS1)
+#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
 #define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
 #define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
@@ -574,7 +574,7 @@
 #define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
 #define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
 #define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
-#endif /* 112x PASS1 */
+#endif /* 1250 PASS3 || 112x PASS1 */
 
 #define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3,61)